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ed
2026-06-14 09:08:52 -04:00
parent 4603a3bb9a
commit 66facd79dd
3 changed files with 18 additions and 5 deletions
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code/duffle/gte.h
+8 -3
View File
@@ -395,12 +395,17 @@ enum { _C2_OPS_ = 0
* `base` is the GPR number to bake into the .word constant's `rs` field. * `base` is the GPR number to bake into the .word constant's `rs` field.
* These are pure compile-time integers; the C compiler constant-folds * These are pure compile-time integers; the C compiler constant-folds
* them into .word directives. */ * them into .word directives. */
enum {
GTE_Z_Offset = 4
};
#define gte_lwc2_v0(base) enc_cop2_lwc2(gte_in_v0_xy, (base), 0) #define gte_lwc2_v0(base) enc_cop2_lwc2(gte_in_v0_xy, (base), 0)
#define gte_lwc2_v0z(base) enc_cop2_lwc2(gte_in_v0_z, (base), 4) #define gte_lwc2_v0z(base) enc_cop2_lwc2(gte_in_v0_z, (base), GTE_Z_Offset)
#define gte_lwc2_v1(base) enc_cop2_lwc2(gte_in_v1_xy, (base), 0) #define gte_lwc2_v1(base) enc_cop2_lwc2(gte_in_v1_xy, (base), 0)
#define gte_lwc2_v1z(base) enc_cop2_lwc2(gte_in_v1_z, (base), 4) #define gte_lwc2_v1z(base) enc_cop2_lwc2(gte_in_v1_z, (base), GTE_Z_Offset)
#define gte_lwc2_v2(base) enc_cop2_lwc2(gte_in_v2_xy, (base), 0) #define gte_lwc2_v2(base) enc_cop2_lwc2(gte_in_v2_xy, (base), 0)
#define gte_lwc2_v2z(base) enc_cop2_lwc2(gte_in_v2_z, (base), 4) #define gte_lwc2_v2z(base) enc_cop2_lwc2(gte_in_v2_z, (base), GTE_Z_Offset)
/* gte_load_vN(r_ptr, base) — placeholder-punned lwc2 loaders /* gte_load_vN(r_ptr, base) — placeholder-punned lwc2 loaders
* *
code/gte_hello/hello_gte.c
+8
View File
@@ -247,6 +247,14 @@ void update(PrimitiveArena* pa, U4* ordering_buf)
// Three independent bases — full register discretion at the call site // Three independent bases — full register discretion at the call site
gte_load_v0(p0, R_T4); gte_load_v0(p0, R_T4);
/*
asm volatile( ".word " "%0" ", %1" : :
"i"(((op_lwc2 & OPCODE_MASK) << OPCODE_SHIFT) | ((R_T4 & REG_MASK) << RS_SHIFT) | ((gte_in_v0_xy & REG_MASK) << RT_SHIFT) | (0 & IMM_MASK)),
"i"(((op_lwc2 & OPCODE_MASK) << OPCODE_SHIFT) | ((R_T4 & REG_MASK) << RS_SHIFT) | ((gte_in_v0_z & REG_MASK) << RT_SHIFT) | (GTE_Z_Offset & IMM_MASK)),
"r"(p0) :
"$2", "$8", "$9", "$31", "memory"
);
*/
gte_load_v1(p1, R_T5); gte_load_v1(p1, R_T5);
gte_load_v2(p2, R_T6); gte_load_v2(p2, R_T6);