From 66facd79dd08b15df3c4bcfd6e3b04b1576796b4 Mon Sep 17 00:00:00 2001 From: Ed_ Date: Sun, 14 Jun 2026 09:08:52 -0400 Subject: [PATCH] minor --- code/duffle/gte.h | 11 ++++++++--- code/duffle/mips.h | 4 ++-- code/gte_hello/hello_gte.c | 8 ++++++++ 3 files changed, 18 insertions(+), 5 deletions(-) diff --git a/code/duffle/gte.h b/code/duffle/gte.h index 09fb8de..e16d8d8 100644 --- a/code/duffle/gte.h +++ b/code/duffle/gte.h @@ -395,12 +395,17 @@ enum { _C2_OPS_ = 0 * `base` is the GPR number to bake into the .word constant's `rs` field. * These are pure compile-time integers; the C compiler constant-folds * them into .word directives. */ + +enum { + GTE_Z_Offset = 4 +}; + #define gte_lwc2_v0(base) enc_cop2_lwc2(gte_in_v0_xy, (base), 0) -#define gte_lwc2_v0z(base) enc_cop2_lwc2(gte_in_v0_z, (base), 4) +#define gte_lwc2_v0z(base) enc_cop2_lwc2(gte_in_v0_z, (base), GTE_Z_Offset) #define gte_lwc2_v1(base) enc_cop2_lwc2(gte_in_v1_xy, (base), 0) -#define gte_lwc2_v1z(base) enc_cop2_lwc2(gte_in_v1_z, (base), 4) +#define gte_lwc2_v1z(base) enc_cop2_lwc2(gte_in_v1_z, (base), GTE_Z_Offset) #define gte_lwc2_v2(base) enc_cop2_lwc2(gte_in_v2_xy, (base), 0) -#define gte_lwc2_v2z(base) enc_cop2_lwc2(gte_in_v2_z, (base), 4) +#define gte_lwc2_v2z(base) enc_cop2_lwc2(gte_in_v2_z, (base), GTE_Z_Offset) /* gte_load_vN(r_ptr, base) — placeholder-punned lwc2 loaders * diff --git a/code/duffle/mips.h b/code/duffle/mips.h index 8676148..09e70d0 100644 --- a/code/duffle/mips.h +++ b/code/duffle/mips.h @@ -57,8 +57,8 @@ enum { /* --- MIPS CPU Registers --- */ - R_0 = R_0_Code, R_AT = R_AT_Code, R_V0 = R_V0_Code, R_V1 = R_V1_Code, - R_A0 = R_A0_Code, R_A1 = R_A1_Code, R_A2 = R_A2_Code, R_A3 = R_A3_Code, + R_0 = R_0_Code, R_AT = R_AT_Code, R_V0 = R_V0_Code, R_V1 = R_V1_Code, + R_A0 = R_A0_Code, R_A1 = R_A1_Code, R_A2 = R_A2_Code, R_A3 = R_A3_Code, R_T0 = R_T0_Code, R_T1 = R_T1_Code, R_T2 = R_T2_Code, R_T3 = R_T3_Code, R_T4 = R_T4_Code, R_T5 = R_T5_Code, R_T6 = R_T6_Code, R_T7 = R_T7_Code, R_S0 = R_S0_Code, R_S1 = R_S1_Code, R_S2 = R_S2_Code, R_S3 = R_S3_Code, diff --git a/code/gte_hello/hello_gte.c b/code/gte_hello/hello_gte.c index 73375eb..d921b08 100644 --- a/code/gte_hello/hello_gte.c +++ b/code/gte_hello/hello_gte.c @@ -247,6 +247,14 @@ void update(PrimitiveArena* pa, U4* ordering_buf) // Three independent bases — full register discretion at the call site gte_load_v0(p0, R_T4); + /* + asm volatile( ".word " "%0" ", %1" : : + "i"(((op_lwc2 & OPCODE_MASK) << OPCODE_SHIFT) | ((R_T4 & REG_MASK) << RS_SHIFT) | ((gte_in_v0_xy & REG_MASK) << RT_SHIFT) | (0 & IMM_MASK)), + "i"(((op_lwc2 & OPCODE_MASK) << OPCODE_SHIFT) | ((R_T4 & REG_MASK) << RS_SHIFT) | ((gte_in_v0_z & REG_MASK) << RT_SHIFT) | (GTE_Z_Offset & IMM_MASK)), + "r"(p0) : + "$2", "$8", "$9", "$31", "memory" + ); + */ gte_load_v1(p1, R_T5); gte_load_v2(p2, R_T6);