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5-post thread, 0 media, July 2026. SAR (signed shift-right) trick: HW uses only 5|6 LSBs of shift-by so mixed-use control words don't need MSB masking - saves an instruction. Working through a single uber-instruction interpreted language for code generation: never misses the instruction cache, executes fully out of micro-op cache, fully data driven, direct map 64K entry symbol table. Borrows from SIMD GPU programming: instead of branching/predicating to avoid stores, just store to a discarded area (negative offset on GPU, designated trash address on CPU). No exit condition logic in infinite loop - exit via storing to set address, external watchdog polls at some sleep frequency. SAR trick can grab 3 values: SF (MSB), CF (shift-out bit -1), and output - SF+CF for CMOVcc, output for next shift. Sibling to the 2079746130309415185 micro macro-forth and 2078349730204078527 8-byte aligned Forth word threads - the uber-instruction version of the runtime-language work.
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title, author, handle, post_url, post_id, timestamp, post_count, reply_count, repost_count, like_count, view_count
| title | author | handle | post_url | post_id | timestamp | post_count | reply_count | repost_count | like_count | view_count |
|---|---|---|---|---|---|---|---|---|---|---|
| SAR on a control word can in theory grab 3 values. | NOTimothyLottes | @NOTimothyLottes | https://x.com/NOTimothyLottes/status/2077241596869751029 | 2077241596869751029 | 2026-07-15 03:59:24 | 5 | 0 | 0 | 2 | 428 |
@NOTimothyLottes — SAR on a control word can in theory grab 3 values.
Post 1 (2026-07-15 02:51:51)
One advantage of SAR (aka signed '>>') is that the shift-by operand HW uses only the 5|6 LSBs automatically. So if you have a mixed used control word, you don't have to mask out the MSBs. Can save an instruction.
Post 2 (2026-07-15 02:54:50) — reply to Post 1
Working through an idea of a single uber-instruction interpreted language for code generation. Meaning something that never misses the instruction cache and executes fully out of the micro-op cache. Fully data driven with a direct map 64k entry symbol table.
Post 3 (2026-07-15 03:03:02) — reply to Post 2
Borrows some ideas from SIMD GPU programming. Like instead of branching/predicating to avoid stores, just store to a discarded area (like a negative offset on the GPU, or a designated trash address on the CPU).
Post 4 (2026-07-15 03:31:21) — reply to Post 3
Don't want exit condition logic in the infinite loop, so exit will have to be having the program store an exit value into a set address, and an external watchdog polling for exit at some sleep frequency.
Post 5 (2026-07-15 03:59:24) — reply to Post 4
SAR on a control word can in theory grab 3 values. SF (sign flag) is set to MSB bit CF (carry flag) is set to what shifts into bit -1 and output
The SF and CF can be used for CMOVcc Output can be used for another shift (after CMOVccs)