ed/raddebugger
1
0
Fork 0
mirror of https://github.com/Ed94/raddebugger.git synced 2026-07-18 07:01:31 -07:00
Code Issues Packages Projects Releases Wiki Activity

do not use complex register union types for common registers; just use primitive integer types instead

Browse Source
This commit is contained in:
Ryan Fleury
2025-10-07 14:41:51 -07:00
parent ab841035c0
commit ec978d8d46
4 changed files with 217 additions and 199 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/regs/generated/regs.meta.c
+96 -96
View File
@@ -166,38 +166,38 @@ REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
@@ -268,46 +268,46 @@ REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
};
String8 regs_g_reg_code_x64_string_table[103] =
@@ -779,14 +779,14 @@ REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
};
REGS_UsageKind regs_g_alias_code_x86_usage_kind_table[36] =
@@ -811,22 +811,22 @@ REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
};
String8 regs_g_reg_code_x86_string_table[61] =
src/regs/regs.mdesk
+96 -96
View File
@@ -67,38 +67,38 @@ REGS_RegTableX64:
{es 16 Normal}
{fs 16 Normal}
{gs 16 Normal}
{zmm0 512 Normal}
{zmm1 512 Normal}
{zmm2 512 Normal}
{zmm3 512 Normal}
{zmm4 512 Normal}
{zmm5 512 Normal}
{zmm6 512 Normal}
{zmm7 512 Normal}
{zmm8 512 Normal}
{zmm9 512 Normal}
{zmm10 512 Normal}
{zmm11 512 Normal}
{zmm12 512 Normal}
{zmm13 512 Normal}
{zmm14 512 Normal}
{zmm15 512 Normal}
{zmm16 512 Normal}
{zmm17 512 Normal}
{zmm18 512 Normal}
{zmm19 512 Normal}
{zmm20 512 Normal}
{zmm21 512 Normal}
{zmm22 512 Normal}
{zmm23 512 Normal}
{zmm24 512 Normal}
{zmm25 512 Normal}
{zmm26 512 Normal}
{zmm27 512 Normal}
{zmm28 512 Normal}
{zmm29 512 Normal}
{zmm30 512 Normal}
{zmm31 512 Normal}
{zmm0 512 Vector}
{zmm1 512 Vector}
{zmm2 512 Vector}
{zmm3 512 Vector}
{zmm4 512 Vector}
{zmm5 512 Vector}
{zmm6 512 Vector}
{zmm7 512 Vector}
{zmm8 512 Vector}
{zmm9 512 Vector}
{zmm10 512 Vector}
{zmm11 512 Vector}
{zmm12 512 Vector}
{zmm13 512 Vector}
{zmm14 512 Vector}
{zmm15 512 Vector}
{zmm16 512 Vector}
{zmm17 512 Vector}
{zmm18 512 Vector}
{zmm19 512 Vector}
{zmm20 512 Vector}
{zmm21 512 Vector}
{zmm22 512 Vector}
{zmm23 512 Vector}
{zmm24 512 Vector}
{zmm25 512 Vector}
{zmm26 512 Vector}
{zmm27 512 Vector}
{zmm28 512 Vector}
{zmm29 512 Vector}
{zmm30 512 Vector}
{zmm31 512 Vector}
{k0 64 Normal}
{k1 64 Normal}
{k2 64 Normal}
@@ -172,46 +172,46 @@ REGS_AliasTableX64:
{ch rcx 8 8 Normal}
{dh rdx 8 8 Normal}
{bh rbx 8 8 Normal}
{xmm0 zmm0 0 128 Normal}
{xmm1 zmm1 0 128 Normal}
{xmm2 zmm2 0 128 Normal}
{xmm3 zmm3 0 128 Normal}
{xmm4 zmm4 0 128 Normal}
{xmm5 zmm5 0 128 Normal}
{xmm6 zmm6 0 128 Normal}
{xmm7 zmm7 0 128 Normal}
{xmm8 zmm8 0 128 Normal}
{xmm9 zmm9 0 128 Normal}
{xmm10 zmm10 0 128 Normal}
{xmm11 zmm11 0 128 Normal}
{xmm12 zmm12 0 128 Normal}
{xmm13 zmm13 0 128 Normal}
{xmm14 zmm14 0 128 Normal}
{xmm15 zmm15 0 128 Normal}
{ymm0 zmm0 0 256 Normal}
{ymm1 zmm1 0 256 Normal}
{ymm2 zmm2 0 256 Normal}
{ymm3 zmm3 0 256 Normal}
{ymm4 zmm4 0 256 Normal}
{ymm5 zmm5 0 256 Normal}
{ymm6 zmm6 0 256 Normal}
{ymm7 zmm7 0 256 Normal}
{ymm8 zmm8 0 256 Normal}
{ymm9 zmm9 0 256 Normal}
{ymm10 zmm10 0 256 Normal}
{ymm11 zmm11 0 256 Normal}
{ymm12 zmm12 0 256 Normal}
{ymm13 zmm13 0 256 Normal}
{ymm14 zmm14 0 256 Normal}
{ymm15 zmm15 0 256 Normal}
{mm0 fpr0 0 64 Normal}
{mm1 fpr1 0 64 Normal}
{mm2 fpr2 0 64 Normal}
{mm3 fpr3 0 64 Normal}
{mm4 fpr4 0 64 Normal}
{mm5 fpr5 0 64 Normal}
{mm6 fpr6 0 64 Normal}
{mm7 fpr7 0 64 Normal}
{xmm0 zmm0 0 128 Vector}
{xmm1 zmm1 0 128 Vector}
{xmm2 zmm2 0 128 Vector}
{xmm3 zmm3 0 128 Vector}
{xmm4 zmm4 0 128 Vector}
{xmm5 zmm5 0 128 Vector}
{xmm6 zmm6 0 128 Vector}
{xmm7 zmm7 0 128 Vector}
{xmm8 zmm8 0 128 Vector}
{xmm9 zmm9 0 128 Vector}
{xmm10 zmm10 0 128 Vector}
{xmm11 zmm11 0 128 Vector}
{xmm12 zmm12 0 128 Vector}
{xmm13 zmm13 0 128 Vector}
{xmm14 zmm14 0 128 Vector}
{xmm15 zmm15 0 128 Vector}
{ymm0 zmm0 0 256 Vector}
{ymm1 zmm1 0 256 Vector}
{ymm2 zmm2 0 256 Vector}
{ymm3 zmm3 0 256 Vector}
{ymm4 zmm4 0 256 Vector}
{ymm5 zmm5 0 256 Vector}
{ymm6 zmm6 0 256 Vector}
{ymm7 zmm7 0 256 Vector}
{ymm8 zmm8 0 256 Vector}
{ymm9 zmm9 0 256 Vector}
{ymm10 zmm10 0 256 Vector}
{ymm11 zmm11 0 256 Vector}
{ymm12 zmm12 0 256 Vector}
{ymm13 zmm13 0 256 Vector}
{ymm14 zmm14 0 256 Vector}
{ymm15 zmm15 0 256 Vector}
{mm0 fpr0 0 64 Vector}
{mm1 fpr1 0 64 Vector}
{mm2 fpr2 0 64 Vector}
{mm3 fpr3 0 64 Vector}
{mm4 fpr4 0 64 Vector}
{mm5 fpr5 0 64 Vector}
{mm6 fpr6 0 64 Vector}
{mm7 fpr7 0 64 Vector}
}
////////////////////////////////
@@ -278,14 +278,14 @@ REGS_RegTableX86:
{fs 16 Normal}
{gs 16 Normal}
// SIMD REGISTERS
{ymm0 256 Normal}
{ymm1 256 Normal}
{ymm2 256 Normal}
{ymm3 256 Normal}
{ymm4 256 Normal}
{ymm5 256 Normal}
{ymm6 256 Normal}
{ymm7 256 Normal}
{ymm0 256 Vector}
{ymm1 256 Vector}
{ymm2 256 Vector}
{ymm3 256 Vector}
{ymm4 256 Vector}
{ymm5 256 Vector}
{ymm6 256 Vector}
{ymm7 256 Vector}
}
@table(name base off size usage)
@@ -310,22 +310,22 @@ REGS_AliasTableX86:
{bl ebx 0 8 Normal}
{bpl ebp 0 8 Normal}
{spl esp 0 8 Normal}
{xmm0 ymm0 0 128 Normal}
{xmm1 ymm1 0 128 Normal}
{xmm2 ymm2 0 128 Normal}
{xmm3 ymm3 0 128 Normal}
{xmm4 ymm4 0 128 Normal}
{xmm5 ymm5 0 128 Normal}
{xmm6 ymm6 0 128 Normal}
{xmm7 ymm7 0 128 Normal}
{mm0 fpr0 0 64 Normal}
{mm1 fpr1 0 64 Normal}
{mm2 fpr2 0 64 Normal}
{mm3 fpr3 0 64 Normal}
{mm4 fpr4 0 64 Normal}
{mm5 fpr5 0 64 Normal}
{mm6 fpr6 0 64 Normal}
{mm7 fpr7 0 64 Normal}
{xmm0 ymm0 0 128 Vector}
{xmm1 ymm1 0 128 Vector}
{xmm2 ymm2 0 128 Vector}
{xmm3 ymm3 0 128 Vector}
{xmm4 ymm4 0 128 Vector}
{xmm5 ymm5 0 128 Vector}
{xmm6 ymm6 0 128 Vector}
{xmm7 ymm7 0 128 Vector}
{mm0 fpr0 0 64 Vector}
{mm1 fpr1 0 64 Vector}
{mm2 fpr2 0 64 Vector}
{mm3 fpr3 0 64 Vector}
{mm4 fpr4 0 64 Vector}
{mm5 fpr5 0 64 Vector}
{mm6 fpr6 0 64 Vector}
{mm7 fpr7 0 64 Vector}
}
////////////////////////////////