From ec978d8d4639b1a5e3dfdafce3c6b0a2c543c91e Mon Sep 17 00:00:00 2001 From: Ryan Fleury Date: Tue, 7 Oct 2025 14:41:51 -0700 Subject: [PATCH] do not use complex register union types for common registers; just use primitive integer types instead --- src/eval/eval_ir.c | 22 +++- src/raddbg/raddbg_views.c | 10 +- src/regs/generated/regs.meta.c | 192 ++++++++++++++++----------------- src/regs/regs.mdesk | 192 ++++++++++++++++----------------- 4 files changed, 217 insertions(+), 199 deletions(-) diff --git a/src/eval/eval_ir.c b/src/eval/eval_ir.c index 359a5b0d..2187a178 100644 --- a/src/eval/eval_ir.c +++ b/src/eval/eval_ir.c @@ -2044,7 +2044,16 @@ e_push_irtree_and_type_from_expr(Arena *arena, E_IRTreeAndType *root_parent, E_I mapped_bytecode = e_bytecode_from_oplist(arena, &oplist); mapped_bytecode_mode = E_Mode_Offset; mapped_bytecode_space = e_base_ctx->thread_reg_space; - mapped_type_key = e_type_key_reg(e_base_ctx->primary_module->arch, reg_num); + REGS_UsageKind reg_usage_kind = regs_reg_code_usage_kind_table_from_arch(e_base_ctx->primary_module->arch)[reg_num]; + if(0){} + else if(reg_usage_kind == REGS_UsageKind_Normal && reg_rng.byte_size == 1) {mapped_type_key = e_type_key_basic(E_TypeKind_U8);} + else if(reg_usage_kind == REGS_UsageKind_Normal && reg_rng.byte_size == 2) {mapped_type_key = e_type_key_basic(E_TypeKind_U16);} + else if(reg_usage_kind == REGS_UsageKind_Normal && reg_rng.byte_size == 4) {mapped_type_key = e_type_key_basic(E_TypeKind_U32);} + else if(reg_usage_kind == REGS_UsageKind_Normal && reg_rng.byte_size == 8) {mapped_type_key = e_type_key_basic(E_TypeKind_U64);} + else + { + mapped_type_key = e_type_key_reg(e_base_ctx->primary_module->arch, reg_num); + } } }break; @@ -2063,7 +2072,16 @@ e_push_irtree_and_type_from_expr(Arena *arena, E_IRTreeAndType *root_parent, E_I mapped_bytecode = e_bytecode_from_oplist(arena, &oplist); mapped_bytecode_mode = E_Mode_Offset; mapped_bytecode_space = e_base_ctx->thread_reg_space; - mapped_type_key = e_type_key_reg_alias(e_base_ctx->primary_module->arch, alias_num); + REGS_UsageKind reg_usage_kind = regs_alias_code_usage_kind_table_from_arch(e_base_ctx->primary_module->arch)[alias_num]; + if(0){} + else if(reg_usage_kind == REGS_UsageKind_Normal && alias_slice.byte_size == 1) {mapped_type_key = e_type_key_basic(E_TypeKind_U8);} + else if(reg_usage_kind == REGS_UsageKind_Normal && alias_slice.byte_size == 2) {mapped_type_key = e_type_key_basic(E_TypeKind_U16);} + else if(reg_usage_kind == REGS_UsageKind_Normal && alias_slice.byte_size == 4) {mapped_type_key = e_type_key_basic(E_TypeKind_U32);} + else if(reg_usage_kind == REGS_UsageKind_Normal && alias_slice.byte_size == 8) {mapped_type_key = e_type_key_basic(E_TypeKind_U64);} + else + { + mapped_type_key = e_type_key_reg_alias(e_base_ctx->primary_module->arch, alias_num); + } } }break; diff --git a/src/raddbg/raddbg_views.c b/src/raddbg/raddbg_views.c index 80c42766..82f01992 100644 --- a/src/raddbg/raddbg_views.c +++ b/src/raddbg/raddbg_views.c @@ -2240,25 +2240,25 @@ RD_VIEW_UI_FUNCTION_DEF(text) { MD5 md5 = rd_md5_from_hash(hash); String8 md5_string = str8_struct(&md5); - file_is_out_of_date = !str8_match(md5_string, checksum_expected, 0); + file_is_out_of_date = !MemoryIsZeroStruct(&md5) && !str8_match(md5_string, checksum_expected, 0); }break; case RDI_ChecksumKind_SHA1: { SHA1 sha1 = rd_sha1_from_hash(hash); String8 sha1_string = str8_struct(&sha1); - file_is_out_of_date = !str8_match(sha1_string, checksum_expected, 0); + file_is_out_of_date = !MemoryIsZeroStruct(&sha1) && !str8_match(sha1_string, checksum_expected, 0); }break; case RDI_ChecksumKind_SHA256: { SHA256 sha256 = rd_sha256_from_hash(hash); String8 sha256_string = str8_struct(&sha256); - file_is_out_of_date = !str8_match(sha256_string, checksum_expected, 0); + file_is_out_of_date = !MemoryIsZeroStruct(&sha256) && !str8_match(sha256_string, checksum_expected, 0); }break; case RDI_ChecksumKind_Timestamp: { FileProperties props = os_properties_from_file_path(rd_regs()->file_path); String8 timestamp_string = str8_struct(&props.modified); - file_is_out_of_date = !str8_match(timestamp_string, checksum_expected, 0); + file_is_out_of_date = !MemoryIsZeroStruct(&props.modified) && !str8_match(timestamp_string, checksum_expected, 0); }break; } @@ -2381,7 +2381,7 @@ RD_VIEW_UI_FUNCTION_DEF(disasm) { auto_selected = 1; auto_space = rd_eval_space_from_ctrl_entity(ctrl_entity_from_handle(&d_state->ctrl_entity_store->ctx, rd_regs()->process), RD_EvalSpaceKind_CtrlEntity); - eval = e_eval_from_stringf("(reg:rip.u64 & (~(0x4000 - 1)))"); + eval = e_eval_from_stringf("(reg:rip & (~(0x4000 - 1)))"); } } diff --git a/src/regs/generated/regs.meta.c b/src/regs/generated/regs.meta.c index fab1e6c9..f1a01b06 100644 --- a/src/regs/generated/regs.meta.c +++ b/src/regs/generated/regs.meta.c @@ -166,38 +166,38 @@ REGS_UsageKind_Normal, REGS_UsageKind_Normal, REGS_UsageKind_Normal, REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, REGS_UsageKind_Normal, REGS_UsageKind_Normal, REGS_UsageKind_Normal, @@ -268,46 +268,46 @@ REGS_UsageKind_Normal, REGS_UsageKind_Normal, REGS_UsageKind_Normal, REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, }; String8 regs_g_reg_code_x64_string_table[103] = @@ -779,14 +779,14 @@ REGS_UsageKind_Normal, REGS_UsageKind_Normal, REGS_UsageKind_Normal, REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, }; REGS_UsageKind regs_g_alias_code_x86_usage_kind_table[36] = @@ -811,22 +811,22 @@ REGS_UsageKind_Normal, REGS_UsageKind_Normal, REGS_UsageKind_Normal, REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, +REGS_UsageKind_Vector, }; String8 regs_g_reg_code_x86_string_table[61] = diff --git a/src/regs/regs.mdesk b/src/regs/regs.mdesk index 25d35691..a26bdf09 100644 --- a/src/regs/regs.mdesk +++ b/src/regs/regs.mdesk @@ -67,38 +67,38 @@ REGS_RegTableX64: {es 16 Normal} {fs 16 Normal} {gs 16 Normal} - {zmm0 512 Normal} - {zmm1 512 Normal} - {zmm2 512 Normal} - {zmm3 512 Normal} - {zmm4 512 Normal} - {zmm5 512 Normal} - {zmm6 512 Normal} - {zmm7 512 Normal} - {zmm8 512 Normal} - {zmm9 512 Normal} - {zmm10 512 Normal} - {zmm11 512 Normal} - {zmm12 512 Normal} - {zmm13 512 Normal} - {zmm14 512 Normal} - {zmm15 512 Normal} - {zmm16 512 Normal} - {zmm17 512 Normal} - {zmm18 512 Normal} - {zmm19 512 Normal} - {zmm20 512 Normal} - {zmm21 512 Normal} - {zmm22 512 Normal} - {zmm23 512 Normal} - {zmm24 512 Normal} - {zmm25 512 Normal} - {zmm26 512 Normal} - {zmm27 512 Normal} - {zmm28 512 Normal} - {zmm29 512 Normal} - {zmm30 512 Normal} - {zmm31 512 Normal} + {zmm0 512 Vector} + {zmm1 512 Vector} + {zmm2 512 Vector} + {zmm3 512 Vector} + {zmm4 512 Vector} + {zmm5 512 Vector} + {zmm6 512 Vector} + {zmm7 512 Vector} + {zmm8 512 Vector} + {zmm9 512 Vector} + {zmm10 512 Vector} + {zmm11 512 Vector} + {zmm12 512 Vector} + {zmm13 512 Vector} + {zmm14 512 Vector} + {zmm15 512 Vector} + {zmm16 512 Vector} + {zmm17 512 Vector} + {zmm18 512 Vector} + {zmm19 512 Vector} + {zmm20 512 Vector} + {zmm21 512 Vector} + {zmm22 512 Vector} + {zmm23 512 Vector} + {zmm24 512 Vector} + {zmm25 512 Vector} + {zmm26 512 Vector} + {zmm27 512 Vector} + {zmm28 512 Vector} + {zmm29 512 Vector} + {zmm30 512 Vector} + {zmm31 512 Vector} {k0 64 Normal} {k1 64 Normal} {k2 64 Normal} @@ -172,46 +172,46 @@ REGS_AliasTableX64: {ch rcx 8 8 Normal} {dh rdx 8 8 Normal} {bh rbx 8 8 Normal} - {xmm0 zmm0 0 128 Normal} - {xmm1 zmm1 0 128 Normal} - {xmm2 zmm2 0 128 Normal} - {xmm3 zmm3 0 128 Normal} - {xmm4 zmm4 0 128 Normal} - {xmm5 zmm5 0 128 Normal} - {xmm6 zmm6 0 128 Normal} - {xmm7 zmm7 0 128 Normal} - {xmm8 zmm8 0 128 Normal} - {xmm9 zmm9 0 128 Normal} - {xmm10 zmm10 0 128 Normal} - {xmm11 zmm11 0 128 Normal} - {xmm12 zmm12 0 128 Normal} - {xmm13 zmm13 0 128 Normal} - {xmm14 zmm14 0 128 Normal} - {xmm15 zmm15 0 128 Normal} - {ymm0 zmm0 0 256 Normal} - {ymm1 zmm1 0 256 Normal} - {ymm2 zmm2 0 256 Normal} - {ymm3 zmm3 0 256 Normal} - {ymm4 zmm4 0 256 Normal} - {ymm5 zmm5 0 256 Normal} - {ymm6 zmm6 0 256 Normal} - {ymm7 zmm7 0 256 Normal} - {ymm8 zmm8 0 256 Normal} - {ymm9 zmm9 0 256 Normal} - {ymm10 zmm10 0 256 Normal} - {ymm11 zmm11 0 256 Normal} - {ymm12 zmm12 0 256 Normal} - {ymm13 zmm13 0 256 Normal} - {ymm14 zmm14 0 256 Normal} - {ymm15 zmm15 0 256 Normal} - {mm0 fpr0 0 64 Normal} - {mm1 fpr1 0 64 Normal} - {mm2 fpr2 0 64 Normal} - {mm3 fpr3 0 64 Normal} - {mm4 fpr4 0 64 Normal} - {mm5 fpr5 0 64 Normal} - {mm6 fpr6 0 64 Normal} - {mm7 fpr7 0 64 Normal} + {xmm0 zmm0 0 128 Vector} + {xmm1 zmm1 0 128 Vector} + {xmm2 zmm2 0 128 Vector} + {xmm3 zmm3 0 128 Vector} + {xmm4 zmm4 0 128 Vector} + {xmm5 zmm5 0 128 Vector} + {xmm6 zmm6 0 128 Vector} + {xmm7 zmm7 0 128 Vector} + {xmm8 zmm8 0 128 Vector} + {xmm9 zmm9 0 128 Vector} + {xmm10 zmm10 0 128 Vector} + {xmm11 zmm11 0 128 Vector} + {xmm12 zmm12 0 128 Vector} + {xmm13 zmm13 0 128 Vector} + {xmm14 zmm14 0 128 Vector} + {xmm15 zmm15 0 128 Vector} + {ymm0 zmm0 0 256 Vector} + {ymm1 zmm1 0 256 Vector} + {ymm2 zmm2 0 256 Vector} + {ymm3 zmm3 0 256 Vector} + {ymm4 zmm4 0 256 Vector} + {ymm5 zmm5 0 256 Vector} + {ymm6 zmm6 0 256 Vector} + {ymm7 zmm7 0 256 Vector} + {ymm8 zmm8 0 256 Vector} + {ymm9 zmm9 0 256 Vector} + {ymm10 zmm10 0 256 Vector} + {ymm11 zmm11 0 256 Vector} + {ymm12 zmm12 0 256 Vector} + {ymm13 zmm13 0 256 Vector} + {ymm14 zmm14 0 256 Vector} + {ymm15 zmm15 0 256 Vector} + {mm0 fpr0 0 64 Vector} + {mm1 fpr1 0 64 Vector} + {mm2 fpr2 0 64 Vector} + {mm3 fpr3 0 64 Vector} + {mm4 fpr4 0 64 Vector} + {mm5 fpr5 0 64 Vector} + {mm6 fpr6 0 64 Vector} + {mm7 fpr7 0 64 Vector} } //////////////////////////////// @@ -278,14 +278,14 @@ REGS_RegTableX86: {fs 16 Normal} {gs 16 Normal} // SIMD REGISTERS - {ymm0 256 Normal} - {ymm1 256 Normal} - {ymm2 256 Normal} - {ymm3 256 Normal} - {ymm4 256 Normal} - {ymm5 256 Normal} - {ymm6 256 Normal} - {ymm7 256 Normal} + {ymm0 256 Vector} + {ymm1 256 Vector} + {ymm2 256 Vector} + {ymm3 256 Vector} + {ymm4 256 Vector} + {ymm5 256 Vector} + {ymm6 256 Vector} + {ymm7 256 Vector} } @table(name base off size usage) @@ -310,22 +310,22 @@ REGS_AliasTableX86: {bl ebx 0 8 Normal} {bpl ebp 0 8 Normal} {spl esp 0 8 Normal} - {xmm0 ymm0 0 128 Normal} - {xmm1 ymm1 0 128 Normal} - {xmm2 ymm2 0 128 Normal} - {xmm3 ymm3 0 128 Normal} - {xmm4 ymm4 0 128 Normal} - {xmm5 ymm5 0 128 Normal} - {xmm6 ymm6 0 128 Normal} - {xmm7 ymm7 0 128 Normal} - {mm0 fpr0 0 64 Normal} - {mm1 fpr1 0 64 Normal} - {mm2 fpr2 0 64 Normal} - {mm3 fpr3 0 64 Normal} - {mm4 fpr4 0 64 Normal} - {mm5 fpr5 0 64 Normal} - {mm6 fpr6 0 64 Normal} - {mm7 fpr7 0 64 Normal} + {xmm0 ymm0 0 128 Vector} + {xmm1 ymm1 0 128 Vector} + {xmm2 ymm2 0 128 Vector} + {xmm3 ymm3 0 128 Vector} + {xmm4 ymm4 0 128 Vector} + {xmm5 ymm5 0 128 Vector} + {xmm6 ymm6 0 128 Vector} + {xmm7 ymm7 0 128 Vector} + {mm0 fpr0 0 64 Vector} + {mm1 fpr1 0 64 Vector} + {mm2 fpr2 0 64 Vector} + {mm3 fpr3 0 64 Vector} + {mm4 fpr4 0 64 Vector} + {mm5 fpr5 0 64 Vector} + {mm6 fpr6 0 64 Vector} + {mm7 fpr7 0 64 Vector} } ////////////////////////////////