ed/raddebugger
1
0
Fork 0
mirror of https://github.com/Ed94/raddebugger.git synced 2026-10-07 16:35:41 +00:00
Code Issues Packages Projects Releases Wiki Activity

fix x87 register layout

Browse Source
This commit is contained in:
Nikita Smith
2025-12-05 16:36:46 -08:00
parent f4ceaecf75
commit ce77442d37
13 changed files with 404 additions and 655 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/regs/generated/regs.meta.c
+23 -77
View File
@@ -103,7 +103,7 @@ case Arch_x86:{result = regs_g_alias_code_x86_usage_kind_table;}break;
return result;
}
C_LINKAGE_BEGIN
REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[105] =
REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[95] =
{
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
@@ -156,16 +156,6 @@ REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
@@ -312,7 +302,7 @@ REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
};
String8 regs_g_reg_code_x64_string_table[105] =
String8 regs_g_reg_code_x64_string_table[95] =
{
str8_lit_comp(""),
str8_lit_comp("rax"),
@@ -343,14 +333,6 @@ str8_lit_comp("dr4"),
str8_lit_comp("dr5"),
str8_lit_comp("dr6"),
str8_lit_comp("dr7"),
str8_lit_comp("fpr0"),
str8_lit_comp("fpr1"),
str8_lit_comp("fpr2"),
str8_lit_comp("fpr3"),
str8_lit_comp("fpr4"),
str8_lit_comp("fpr5"),
str8_lit_comp("fpr6"),
str8_lit_comp("fpr7"),
str8_lit_comp("st0"),
str8_lit_comp("st1"),
str8_lit_comp("st2"),
@@ -363,8 +345,6 @@ str8_lit_comp("fcw"),
str8_lit_comp("fsw"),
str8_lit_comp("ftw"),
str8_lit_comp("fop"),
str8_lit_comp("fcs"),
str8_lit_comp("fds"),
str8_lit_comp("fip"),
str8_lit_comp("fdp"),
str8_lit_comp("mxcsr"),
@@ -521,7 +501,7 @@ str8_lit_comp("mm6"),
str8_lit_comp("mm7"),
};
REGS_Rng regs_g_reg_code_x64_rng_table[105] =
REGS_Rng regs_g_reg_code_x64_rng_table[95] =
{
{0},
{(U16)OffsetOf(REGS_RegBlockX64, rax), 8},
@@ -552,14 +532,6 @@ REGS_Rng regs_g_reg_code_x64_rng_table[105] =
{(U16)OffsetOf(REGS_RegBlockX64, dr5), 8},
{(U16)OffsetOf(REGS_RegBlockX64, dr6), 8},
{(U16)OffsetOf(REGS_RegBlockX64, dr7), 8},
{(U16)OffsetOf(REGS_RegBlockX64, fpr0), 10},
{(U16)OffsetOf(REGS_RegBlockX64, fpr1), 10},
{(U16)OffsetOf(REGS_RegBlockX64, fpr2), 10},
{(U16)OffsetOf(REGS_RegBlockX64, fpr3), 10},
{(U16)OffsetOf(REGS_RegBlockX64, fpr4), 10},
{(U16)OffsetOf(REGS_RegBlockX64, fpr5), 10},
{(U16)OffsetOf(REGS_RegBlockX64, fpr6), 10},
{(U16)OffsetOf(REGS_RegBlockX64, fpr7), 10},
{(U16)OffsetOf(REGS_RegBlockX64, st0), 10},
{(U16)OffsetOf(REGS_RegBlockX64, st1), 10},
{(U16)OffsetOf(REGS_RegBlockX64, st2), 10},
@@ -570,10 +542,8 @@ REGS_Rng regs_g_reg_code_x64_rng_table[105] =
{(U16)OffsetOf(REGS_RegBlockX64, st7), 10},
{(U16)OffsetOf(REGS_RegBlockX64, fcw), 2},
{(U16)OffsetOf(REGS_RegBlockX64, fsw), 2},
{(U16)OffsetOf(REGS_RegBlockX64, ftw), 2},
{(U16)OffsetOf(REGS_RegBlockX64, ftw), 1},
{(U16)OffsetOf(REGS_RegBlockX64, fop), 2},
{(U16)OffsetOf(REGS_RegBlockX64, fcs), 2},
{(U16)OffsetOf(REGS_RegBlockX64, fds), 2},
{(U16)OffsetOf(REGS_RegBlockX64, fip), 8},
{(U16)OffsetOf(REGS_RegBlockX64, fdp), 8},
{(U16)OffsetOf(REGS_RegBlockX64, mxcsr), 4},
@@ -720,17 +690,17 @@ REGS_Slice regs_g_alias_code_x64_slice_table[96] =
{REGS_RegCodeX64_zmm13, 0, 32},
{REGS_RegCodeX64_zmm14, 0, 32},
{REGS_RegCodeX64_zmm15, 0, 32},
{REGS_RegCodeX64_fpr0, 0, 8},
{REGS_RegCodeX64_fpr1, 0, 8},
{REGS_RegCodeX64_fpr2, 0, 8},
{REGS_RegCodeX64_fpr3, 0, 8},
{REGS_RegCodeX64_fpr4, 0, 8},
{REGS_RegCodeX64_fpr5, 0, 8},
{REGS_RegCodeX64_fpr6, 0, 8},
{REGS_RegCodeX64_fpr7, 0, 8},
{REGS_RegCodeX64_st0, 0, 8},
{REGS_RegCodeX64_st1, 0, 8},
{REGS_RegCodeX64_st2, 0, 8},
{REGS_RegCodeX64_st3, 0, 8},
{REGS_RegCodeX64_st4, 0, 8},
{REGS_RegCodeX64_st5, 0, 8},
{REGS_RegCodeX64_st6, 0, 8},
{REGS_RegCodeX64_st7, 0, 8},
};
REGS_UsageKind regs_g_reg_code_x86_usage_kind_table[63] =
REGS_UsageKind regs_g_reg_code_x86_usage_kind_table[55] =
{
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
@@ -779,14 +749,6 @@ REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
@@ -837,7 +799,7 @@ REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
};
String8 regs_g_reg_code_x86_string_table[63] =
String8 regs_g_reg_code_x86_string_table[55] =
{
str8_lit_comp(""),
str8_lit_comp("eax"),
@@ -860,14 +822,6 @@ str8_lit_comp("dr4"),
str8_lit_comp("dr5"),
str8_lit_comp("dr6"),
str8_lit_comp("dr7"),
str8_lit_comp("fpr0"),
str8_lit_comp("fpr1"),
str8_lit_comp("fpr2"),
str8_lit_comp("fpr3"),
str8_lit_comp("fpr4"),
str8_lit_comp("fpr5"),
str8_lit_comp("fpr6"),
str8_lit_comp("fpr7"),
str8_lit_comp("st0"),
str8_lit_comp("st1"),
str8_lit_comp("st2"),
@@ -944,7 +898,7 @@ str8_lit_comp("mm6"),
str8_lit_comp("mm7"),
};
REGS_Rng regs_g_reg_code_x86_rng_table[63] =
REGS_Rng regs_g_reg_code_x86_rng_table[55] =
{
{0},
{(U16)OffsetOf(REGS_RegBlockX86, eax), 4},
@@ -967,14 +921,6 @@ REGS_Rng regs_g_reg_code_x86_rng_table[63] =
{(U16)OffsetOf(REGS_RegBlockX86, dr5), 4},
{(U16)OffsetOf(REGS_RegBlockX86, dr6), 4},
{(U16)OffsetOf(REGS_RegBlockX86, dr7), 4},
{(U16)OffsetOf(REGS_RegBlockX86, fpr0), 10},
{(U16)OffsetOf(REGS_RegBlockX86, fpr1), 10},
{(U16)OffsetOf(REGS_RegBlockX86, fpr2), 10},
{(U16)OffsetOf(REGS_RegBlockX86, fpr3), 10},
{(U16)OffsetOf(REGS_RegBlockX86, fpr4), 10},
{(U16)OffsetOf(REGS_RegBlockX86, fpr5), 10},
{(U16)OffsetOf(REGS_RegBlockX86, fpr6), 10},
{(U16)OffsetOf(REGS_RegBlockX86, fpr7), 10},
{(U16)OffsetOf(REGS_RegBlockX86, st0), 10},
{(U16)OffsetOf(REGS_RegBlockX86, st1), 10},
{(U16)OffsetOf(REGS_RegBlockX86, st2), 10},
@@ -1041,14 +987,14 @@ REGS_Slice regs_g_alias_code_x86_slice_table[36] =
{REGS_RegCodeX86_ymm5, 0, 16},
{REGS_RegCodeX86_ymm6, 0, 16},
{REGS_RegCodeX86_ymm7, 0, 16},
{REGS_RegCodeX86_fpr0, 0, 8},
{REGS_RegCodeX86_fpr1, 0, 8},
{REGS_RegCodeX86_fpr2, 0, 8},
{REGS_RegCodeX86_fpr3, 0, 8},
{REGS_RegCodeX86_fpr4, 0, 8},
{REGS_RegCodeX86_fpr5, 0, 8},
{REGS_RegCodeX86_fpr6, 0, 8},
{REGS_RegCodeX86_fpr7, 0, 8},
{REGS_RegCodeX86_st0, 0, 8},
{REGS_RegCodeX86_st1, 0, 8},
{REGS_RegCodeX86_st2, 0, 8},
{REGS_RegCodeX86_st3, 0, 8},
{REGS_RegCodeX86_st4, 0, 8},
{REGS_RegCodeX86_st5, 0, 8},
{REGS_RegCodeX86_st6, 0, 8},
{REGS_RegCodeX86_st7, 0, 8},
};
C_LINKAGE_END
src/regs/generated/regs.meta.h
+7 -43
View File
@@ -37,14 +37,6 @@ REGS_RegCodeX64_dr4,
REGS_RegCodeX64_dr5,
REGS_RegCodeX64_dr6,
REGS_RegCodeX64_dr7,
REGS_RegCodeX64_fpr0,
REGS_RegCodeX64_fpr1,
REGS_RegCodeX64_fpr2,
REGS_RegCodeX64_fpr3,
REGS_RegCodeX64_fpr4,
REGS_RegCodeX64_fpr5,
REGS_RegCodeX64_fpr6,
REGS_RegCodeX64_fpr7,
REGS_RegCodeX64_st0,
REGS_RegCodeX64_st1,
REGS_RegCodeX64_st2,
@@ -57,8 +49,6 @@ REGS_RegCodeX64_fcw,
REGS_RegCodeX64_fsw,
REGS_RegCodeX64_ftw,
REGS_RegCodeX64_fop,
REGS_RegCodeX64_fcs,
REGS_RegCodeX64_fds,
REGS_RegCodeX64_fip,
REGS_RegCodeX64_fdp,
REGS_RegCodeX64_mxcsr,
@@ -240,14 +230,6 @@ REGS_RegCodeX86_dr4,
REGS_RegCodeX86_dr5,
REGS_RegCodeX86_dr6,
REGS_RegCodeX86_dr7,
REGS_RegCodeX86_fpr0,
REGS_RegCodeX86_fpr1,
REGS_RegCodeX86_fpr2,
REGS_RegCodeX86_fpr3,
REGS_RegCodeX86_fpr4,
REGS_RegCodeX86_fpr5,
REGS_RegCodeX86_fpr6,
REGS_RegCodeX86_fpr7,
REGS_RegCodeX86_st0,
REGS_RegCodeX86_st1,
REGS_RegCodeX86_st2,
@@ -357,14 +339,6 @@ REGS_Reg64 dr4;
REGS_Reg64 dr5;
REGS_Reg64 dr6;
REGS_Reg64 dr7;
REGS_Reg80 fpr0;
REGS_Reg80 fpr1;
REGS_Reg80 fpr2;
REGS_Reg80 fpr3;
REGS_Reg80 fpr4;
REGS_Reg80 fpr5;
REGS_Reg80 fpr6;
REGS_Reg80 fpr7;
REGS_Reg80 st0;
REGS_Reg80 st1;
REGS_Reg80 st2;
@@ -375,10 +349,8 @@ REGS_Reg80 st6;
REGS_Reg80 st7;
REGS_Reg16 fcw;
REGS_Reg16 fsw;
REGS_Reg16 ftw;
REGS_Reg8 ftw;
REGS_Reg16 fop;
REGS_Reg16 fcs;
REGS_Reg16 fds;
REGS_Reg64 fip;
REGS_Reg64 fdp;
REGS_Reg32 mxcsr;
@@ -458,14 +430,6 @@ REGS_Reg32 dr4;
REGS_Reg32 dr5;
REGS_Reg32 dr6;
REGS_Reg32 dr7;
REGS_Reg80 fpr0;
REGS_Reg80 fpr1;
REGS_Reg80 fpr2;
REGS_Reg80 fpr3;
REGS_Reg80 fpr4;
REGS_Reg80 fpr5;
REGS_Reg80 fpr6;
REGS_Reg80 fpr7;
REGS_Reg80 st0;
REGS_Reg80 st1;
REGS_Reg80 st2;
@@ -503,17 +467,17 @@ REGS_Reg256 ymm7;
};
C_LINKAGE_BEGIN
extern REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[105];
extern REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[95];
extern REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[96];
extern String8 regs_g_reg_code_x64_string_table[105];
extern String8 regs_g_reg_code_x64_string_table[95];
extern String8 regs_g_alias_code_x64_string_table[96];
extern REGS_Rng regs_g_reg_code_x64_rng_table[105];
extern REGS_Rng regs_g_reg_code_x64_rng_table[95];
extern REGS_Slice regs_g_alias_code_x64_slice_table[96];
extern REGS_UsageKind regs_g_reg_code_x86_usage_kind_table[63];
extern REGS_UsageKind regs_g_reg_code_x86_usage_kind_table[55];
extern REGS_UsageKind regs_g_alias_code_x86_usage_kind_table[36];
extern String8 regs_g_reg_code_x86_string_table[63];
extern String8 regs_g_reg_code_x86_string_table[55];
extern String8 regs_g_alias_code_x86_string_table[36];
extern REGS_Rng regs_g_reg_code_x86_rng_table[63];
extern REGS_Rng regs_g_reg_code_x86_rng_table[55];
extern REGS_Slice regs_g_alias_code_x86_slice_table[36];
C_LINKAGE_END
src/regs/rdi/generated/regs_rdi.meta.c
-36
View File
@@ -42,14 +42,6 @@ case REGS_RegCodeX64_dr4:{result = RDI_RegCodeX64_dr4;}break;
case REGS_RegCodeX64_dr5:{result = RDI_RegCodeX64_dr5;}break;
case REGS_RegCodeX64_dr6:{result = RDI_RegCodeX64_dr6;}break;
case REGS_RegCodeX64_dr7:{result = RDI_RegCodeX64_dr7;}break;
case REGS_RegCodeX64_fpr0:{result = RDI_RegCodeX64_fpr0;}break;
case REGS_RegCodeX64_fpr1:{result = RDI_RegCodeX64_fpr1;}break;
case REGS_RegCodeX64_fpr2:{result = RDI_RegCodeX64_fpr2;}break;
case REGS_RegCodeX64_fpr3:{result = RDI_RegCodeX64_fpr3;}break;
case REGS_RegCodeX64_fpr4:{result = RDI_RegCodeX64_fpr4;}break;
case REGS_RegCodeX64_fpr5:{result = RDI_RegCodeX64_fpr5;}break;
case REGS_RegCodeX64_fpr6:{result = RDI_RegCodeX64_fpr6;}break;
case REGS_RegCodeX64_fpr7:{result = RDI_RegCodeX64_fpr7;}break;
case REGS_RegCodeX64_st0:{result = RDI_RegCodeX64_st0;}break;
case REGS_RegCodeX64_st1:{result = RDI_RegCodeX64_st1;}break;
case REGS_RegCodeX64_st2:{result = RDI_RegCodeX64_st2;}break;
@@ -62,8 +54,6 @@ case REGS_RegCodeX64_fcw:{result = RDI_RegCodeX64_fcw;}break;
case REGS_RegCodeX64_fsw:{result = RDI_RegCodeX64_fsw;}break;
case REGS_RegCodeX64_ftw:{result = RDI_RegCodeX64_ftw;}break;
case REGS_RegCodeX64_fop:{result = RDI_RegCodeX64_fop;}break;
case REGS_RegCodeX64_fcs:{result = RDI_RegCodeX64_fcs;}break;
case REGS_RegCodeX64_fds:{result = RDI_RegCodeX64_fds;}break;
case REGS_RegCodeX64_fip:{result = RDI_RegCodeX64_fip;}break;
case REGS_RegCodeX64_fdp:{result = RDI_RegCodeX64_fdp;}break;
case REGS_RegCodeX64_mxcsr:{result = RDI_RegCodeX64_mxcsr;}break;
@@ -145,14 +135,6 @@ case REGS_RegCodeX86_dr4:{result = RDI_RegCodeX86_dr4;}break;
case REGS_RegCodeX86_dr5:{result = RDI_RegCodeX86_dr5;}break;
case REGS_RegCodeX86_dr6:{result = RDI_RegCodeX86_dr6;}break;
case REGS_RegCodeX86_dr7:{result = RDI_RegCodeX86_dr7;}break;
case REGS_RegCodeX86_fpr0:{result = RDI_RegCodeX86_fpr0;}break;
case REGS_RegCodeX86_fpr1:{result = RDI_RegCodeX86_fpr1;}break;
case REGS_RegCodeX86_fpr2:{result = RDI_RegCodeX86_fpr2;}break;
case REGS_RegCodeX86_fpr3:{result = RDI_RegCodeX86_fpr3;}break;
case REGS_RegCodeX86_fpr4:{result = RDI_RegCodeX86_fpr4;}break;
case REGS_RegCodeX86_fpr5:{result = RDI_RegCodeX86_fpr5;}break;
case REGS_RegCodeX86_fpr6:{result = RDI_RegCodeX86_fpr6;}break;
case REGS_RegCodeX86_fpr7:{result = RDI_RegCodeX86_fpr7;}break;
case REGS_RegCodeX86_st0:{result = RDI_RegCodeX86_st0;}break;
case REGS_RegCodeX86_st1:{result = RDI_RegCodeX86_st1;}break;
case REGS_RegCodeX86_st2:{result = RDI_RegCodeX86_st2;}break;
@@ -231,14 +213,6 @@ case RDI_RegCodeX64_dr4:{result = REGS_RegCodeX64_dr4;}break;
case RDI_RegCodeX64_dr5:{result = REGS_RegCodeX64_dr5;}break;
case RDI_RegCodeX64_dr6:{result = REGS_RegCodeX64_dr6;}break;
case RDI_RegCodeX64_dr7:{result = REGS_RegCodeX64_dr7;}break;
case RDI_RegCodeX64_fpr0:{result = REGS_RegCodeX64_fpr0;}break;
case RDI_RegCodeX64_fpr1:{result = REGS_RegCodeX64_fpr1;}break;
case RDI_RegCodeX64_fpr2:{result = REGS_RegCodeX64_fpr2;}break;
case RDI_RegCodeX64_fpr3:{result = REGS_RegCodeX64_fpr3;}break;
case RDI_RegCodeX64_fpr4:{result = REGS_RegCodeX64_fpr4;}break;
case RDI_RegCodeX64_fpr5:{result = REGS_RegCodeX64_fpr5;}break;
case RDI_RegCodeX64_fpr6:{result = REGS_RegCodeX64_fpr6;}break;
case RDI_RegCodeX64_fpr7:{result = REGS_RegCodeX64_fpr7;}break;
case RDI_RegCodeX64_st0:{result = REGS_RegCodeX64_st0;}break;
case RDI_RegCodeX64_st1:{result = REGS_RegCodeX64_st1;}break;
case RDI_RegCodeX64_st2:{result = REGS_RegCodeX64_st2;}break;
@@ -251,8 +225,6 @@ case RDI_RegCodeX64_fcw:{result = REGS_RegCodeX64_fcw;}break;
case RDI_RegCodeX64_fsw:{result = REGS_RegCodeX64_fsw;}break;
case RDI_RegCodeX64_ftw:{result = REGS_RegCodeX64_ftw;}break;
case RDI_RegCodeX64_fop:{result = REGS_RegCodeX64_fop;}break;
case RDI_RegCodeX64_fcs:{result = REGS_RegCodeX64_fcs;}break;
case RDI_RegCodeX64_fds:{result = REGS_RegCodeX64_fds;}break;
case RDI_RegCodeX64_fip:{result = REGS_RegCodeX64_fip;}break;
case RDI_RegCodeX64_fdp:{result = REGS_RegCodeX64_fdp;}break;
case RDI_RegCodeX64_mxcsr:{result = REGS_RegCodeX64_mxcsr;}break;
@@ -334,14 +306,6 @@ case RDI_RegCodeX86_dr4:{result = REGS_RegCodeX86_dr4;}break;
case RDI_RegCodeX86_dr5:{result = REGS_RegCodeX86_dr5;}break;
case RDI_RegCodeX86_dr6:{result = REGS_RegCodeX86_dr6;}break;
case RDI_RegCodeX86_dr7:{result = REGS_RegCodeX86_dr7;}break;
case RDI_RegCodeX86_fpr0:{result = REGS_RegCodeX86_fpr0;}break;
case RDI_RegCodeX86_fpr1:{result = REGS_RegCodeX86_fpr1;}break;
case RDI_RegCodeX86_fpr2:{result = REGS_RegCodeX86_fpr2;}break;
case RDI_RegCodeX86_fpr3:{result = REGS_RegCodeX86_fpr3;}break;
case RDI_RegCodeX86_fpr4:{result = REGS_RegCodeX86_fpr4;}break;
case RDI_RegCodeX86_fpr5:{result = REGS_RegCodeX86_fpr5;}break;
case RDI_RegCodeX86_fpr6:{result = REGS_RegCodeX86_fpr6;}break;
case RDI_RegCodeX86_fpr7:{result = REGS_RegCodeX86_fpr7;}break;
case RDI_RegCodeX86_st0:{result = REGS_RegCodeX86_st0;}break;
case RDI_RegCodeX86_st1:{result = REGS_RegCodeX86_st1;}break;
case RDI_RegCodeX86_st2:{result = REGS_RegCodeX86_st2;}break;
src/regs/regs.h
+3
View File
@@ -20,6 +20,8 @@ REGS_UsageKind;
typedef U8 REGS_RegCode;
typedef U8 REGS_AliasCode;
typedef U8 REGS_Reg8;
typedef union REGS_Reg16 REGS_Reg16;
union REGS_Reg16
{
@@ -39,6 +41,7 @@ typedef union REGS_Reg64 REGS_Reg64;
union REGS_Reg64
{
U8 v[8];
U32 u32[2];
U64 u64;
F64 f64;
};
src/regs/regs.mdesk
+17 -35
View File
@@ -35,14 +35,6 @@ REGS_RegTableX64:
{dr5 64 Normal}
{dr6 64 Normal}
{dr7 64 Normal}
{fpr0 80 Normal}
{fpr1 80 Normal}
{fpr2 80 Normal}
{fpr3 80 Normal}
{fpr4 80 Normal}
{fpr5 80 Normal}
{fpr6 80 Normal}
{fpr7 80 Normal}
{st0 80 Normal}
{st1 80 Normal}
{st2 80 Normal}
@@ -53,10 +45,8 @@ REGS_RegTableX64:
{st7 80 Normal}
{fcw 16 Normal}
{fsw 16 Normal}
{ftw 16 Normal}
{ftw 8 Normal}
{fop 16 Normal}
{fcs 16 Normal}
{fds 16 Normal}
{fip 64 Normal}
{fdp 64 Normal}
{mxcsr 32 Normal}
@@ -206,14 +196,14 @@ REGS_AliasTableX64:
{ymm13 zmm13 0 256 Vector}
{ymm14 zmm14 0 256 Vector}
{ymm15 zmm15 0 256 Vector}
{mm0 fpr0 0 64 Vector}
{mm1 fpr1 0 64 Vector}
{mm2 fpr2 0 64 Vector}
{mm3 fpr3 0 64 Vector}
{mm4 fpr4 0 64 Vector}
{mm5 fpr5 0 64 Vector}
{mm6 fpr6 0 64 Vector}
{mm7 fpr7 0 64 Vector}
{mm0 st0 0 64 Vector}
{mm1 st1 0 64 Vector}
{mm2 st2 0 64 Vector}
{mm3 st3 0 64 Vector}
{mm4 st4 0 64 Vector}
{mm5 st5 0 64 Vector}
{mm6 st6 0 64 Vector}
{mm7 st7 0 64 Vector}
}
////////////////////////////////
@@ -246,14 +236,6 @@ REGS_RegTableX86:
// TODO(allen): I am suspicious of this stuff here.
// Are fpr0-7 and st0-7 actually different things? Visual studio doesn't show
// frp0-7. Not sure if the mm0-7 aliases are setup the right way either.
{fpr0 80 Normal}
{fpr1 80 Normal}
{fpr2 80 Normal}
{fpr3 80 Normal}
{fpr4 80 Normal}
{fpr5 80 Normal}
{fpr6 80 Normal}
{fpr7 80 Normal}
{st0 80 Normal}
{st1 80 Normal}
{st2 80 Normal}
@@ -322,14 +304,14 @@ REGS_AliasTableX86:
{xmm5 ymm5 0 128 Vector}
{xmm6 ymm6 0 128 Vector}
{xmm7 ymm7 0 128 Vector}
{mm0 fpr0 0 64 Vector}
{mm1 fpr1 0 64 Vector}
{mm2 fpr2 0 64 Vector}
{mm3 fpr3 0 64 Vector}
{mm4 fpr4 0 64 Vector}
{mm5 fpr5 0 64 Vector}
{mm6 fpr6 0 64 Vector}
{mm7 fpr7 0 64 Vector}
{mm0 st0 0 64 Vector}
{mm1 st1 0 64 Vector}
{mm2 st2 0 64 Vector}
{mm3 st3 0 64 Vector}
{mm4 st4 0 64 Vector}
{mm5 st5 0 64 Vector}
{mm6 st6 0 64 Vector}
{mm7 st7 0 64 Vector}
}
////////////////////////////////