diff --git a/src/codeview/codeview.h b/src/codeview/codeview.h index fa8f4e09..fbd0649a 100644 --- a/src/codeview/codeview.h +++ b/src/codeview/codeview.h @@ -78,14 +78,14 @@ X(IP, 31, eip, 0, 2) \ X(FLAGS, 32, eflags, 0, 2) \ X(EIP, 33, eip, 0, 4) \ X(EFLAGS, 34, eflags, 0, 4) \ -X(MM0, 146, fpr0, 0, 8) \ -X(MM1, 147, fpr1, 0, 8) \ -X(MM2, 148, fpr2, 0, 8) \ -X(MM3, 149, fpr3, 0, 8) \ -X(MM4, 150, fpr4, 0, 8) \ -X(MM5, 151, fpr5, 0, 8) \ -X(MM6, 152, fpr6, 0, 8) \ -X(MM7, 153, fpr7, 0, 8) \ +X(MM0, 146, st0, 0, 8) \ +X(MM1, 147, st1, 0, 8) \ +X(MM2, 148, st2, 0, 8) \ +X(MM3, 149, st3, 0, 8) \ +X(MM4, 150, st4, 0, 8) \ +X(MM5, 151, st5, 0, 8) \ +X(MM6, 152, st6, 0, 8) \ +X(MM7, 153, st7, 0, 8) \ X(XMM0, 154, ymm0, 0, 16) \ X(XMM1, 155, ymm1, 0, 16) \ X(XMM2, 156, ymm2, 0, 16) \ @@ -382,14 +382,14 @@ X(FPDS, 142, nil, 0, 0) \ X(ISEM, 143, nil, 0, 0) \ X(FPEIP, 144, nil, 0, 0) \ X(FPEDO, 145, nil, 0, 0) \ -X(MM0, 146, fpr0, 0, 8) \ -X(MM1, 147, fpr1, 0, 8) \ -X(MM2, 148, fpr2, 0, 8) \ -X(MM3, 149, fpr3, 0, 8) \ -X(MM4, 150, fpr4, 0, 8) \ -X(MM5, 151, fpr5, 0, 8) \ -X(MM6, 152, fpr6, 0, 8) \ -X(MM7, 153, fpr7, 0, 8) \ +X(MM0, 146, st0, 0, 8) \ +X(MM1, 147, st1, 0, 8) \ +X(MM2, 148, st2, 0, 8) \ +X(MM3, 149, st3, 0, 8) \ +X(MM4, 150, st4, 0, 8) \ +X(MM5, 151, st5, 0, 8) \ +X(MM6, 152, st6, 0, 8) \ +X(MM7, 153, st7, 0, 8) \ X(XMM0, 154, zmm0, 0, 16) \ X(XMM1, 155, zmm1, 0, 16) \ X(XMM2, 156, zmm2, 0, 16) \ @@ -463,22 +463,22 @@ X(EMM4H, 232, zmm4, 8, 8) \ X(EMM5H, 233, zmm5, 8, 8) \ X(EMM6H, 234, zmm6, 8, 8) \ X(EMM7H, 235, zmm7, 8, 8) \ -X(MM00, 236, fpr0, 0, 4) \ -X(MM01, 237, fpr0, 4, 4) \ -X(MM10, 238, fpr1, 0, 4) \ -X(MM11, 239, fpr1, 4, 4) \ -X(MM20, 240, fpr2, 0, 4) \ -X(MM21, 241, fpr2, 4, 4) \ -X(MM30, 242, fpr3, 0, 4) \ -X(MM31, 243, fpr3, 4, 4) \ -X(MM40, 244, fpr4, 0, 4) \ -X(MM41, 245, fpr4, 4, 4) \ -X(MM50, 246, fpr5, 0, 4) \ -X(MM51, 247, fpr5, 4, 4) \ -X(MM60, 248, fpr6, 0, 4) \ -X(MM61, 249, fpr6, 4, 4) \ -X(MM70, 250, fpr7, 0, 4) \ -X(MM71, 251, fpr7, 4, 4) \ +X(MM00, 236, st0, 0, 4) \ +X(MM01, 237, st0, 4, 4) \ +X(MM10, 238, st1, 0, 4) \ +X(MM11, 239, st1, 4, 4) \ +X(MM20, 240, st2, 0, 4) \ +X(MM21, 241, st2, 4, 4) \ +X(MM30, 242, st3, 0, 4) \ +X(MM31, 243, st3, 4, 4) \ +X(MM40, 244, st4, 0, 4) \ +X(MM41, 245, st4, 4, 4) \ +X(MM50, 246, st5, 0, 4) \ +X(MM51, 247, st5, 4, 4) \ +X(MM60, 248, st6, 0, 4) \ +X(MM61, 249, st6, 4, 4) \ +X(MM70, 250, st7, 0, 4) \ +X(MM71, 251, st7, 4, 4) \ X(XMM8, 252, zmm8, 0, 16) \ X(XMM9, 253, zmm9, 0, 16) \ X(XMM10, 254, zmm10, 0, 16) \ diff --git a/src/demon/linux/demon_core_linux.c b/src/demon/linux/demon_core_linux.c index ba963fb1..86a9d9fd 100644 --- a/src/demon/linux/demon_core_linux.c +++ b/src/demon/linux/demon_core_linux.c @@ -1038,10 +1038,10 @@ dmn_lnx_thread_read_reg_block(DMN_LNX_Entity *thread) // copy x87 registers dst->fcw.u16 = src->fcw; dst->fsw.u16 = src->fsw; - dst->ftw.u16 = x64_xsave_tag_word_from_real_tag_word(src->ftw); + dst->ftw = src->ftw; dst->fop.u16 = src->fop; - dst->fip.u64 = src->b64.fip; - dst->fdp.u64 = src->b64.fdp; + dst->fip.u64 = src->fip; + dst->fdp.u64 = src->fdp; dst->mxcsr.u32 = src->mxcsr; dst->mxcsr_mask.u32 = src->mxcsr_mask; for EachIndex(i, 8) @@ -1063,6 +1063,9 @@ dmn_lnx_thread_read_reg_block(DMN_LNX_Entity *thread) // copy xsave registers if(xsave) { + // compact register layout is not supported + AssertAlways(xsave->header.xcomp_bv == 0); + if(xsave->header.xstate_bv & X64_XStateComponentFlag_AVX) { AssertAlways(process->xsave_layout.avx_offset + 16*sizeof(REGS_Reg128) <= process->xsave_size); @@ -1219,14 +1222,14 @@ dmn_lnx_thread_write_reg_block(DMN_LNX_Entity *thread) X64_FXSave dst_fxsave = {0}; { - dst_fxsave.fcw = src->fcw.u16; - dst_fxsave.fsw = src->fsw.u16; - dst_fxsave.ftw = src->ftw.u16; - dst_fxsave.fop = src->fop.u16; - dst_fxsave.b64.fip = src->fip.u64; - dst_fxsave.b64.fdp = src->fdp.u64; - dst_fxsave.mxcsr = src->mxcsr.u32; - dst_fxsave.mxcsr_mask = src->mxcsr_mask.u32; + dst_fxsave.fcw = src->fcw.u16; + dst_fxsave.fsw = src->fsw.u16; + dst_fxsave.ftw = src->ftw; + dst_fxsave.fop = src->fop.u16; + dst_fxsave.fip = src->fip.u64; + dst_fxsave.fdp = src->fdp.u64; + dst_fxsave.mxcsr = src->mxcsr.u32; + dst_fxsave.mxcsr_mask = src->mxcsr_mask.u32; REGS_Reg128 *st_d = (REGS_Reg128 *)dst_fxsave.st_space; REGS_Reg80 *st_s = &src->st0; @@ -1248,6 +1251,7 @@ dmn_lnx_thread_write_reg_block(DMN_LNX_Entity *thread) U8 *xsave_raw = push_array(scratch.arena, U8, process->xsave_size); X64_XSave *dst = (X64_XSave *)xsave_raw; dst->fxsave = dst_fxsave; + dst->header.xstate_bv |= X64_XStateComponentFlag_FP; dst->header.xstate_bv |= X64_XStateComponentFlag_SSE; if(process->xsave_layout.avx_offset) diff --git a/src/demon/win32/demon_core_win32.c b/src/demon/win32/demon_core_win32.c index b2fe81f9..57a13702 100644 --- a/src/demon/win32/demon_core_win32.c +++ b/src/demon/win32/demon_core_win32.c @@ -582,57 +582,6 @@ dmn_w32_image_info_from_process_base_vaddr(HANDLE process, U64 base_vaddr) //- rjf: threads -internal U16 -dmn_w32_real_tag_word_from_xsave(XSAVE_FORMAT *fxsave) -{ - U16 result = 0; - U32 top = (fxsave->StatusWord >> 11) & 7; - for(U32 fpr = 0; fpr < 8; fpr += 1) - { - U32 tag = 3; - if(fxsave->TagWord & (1 << fpr)) - { - U32 st = (fpr - top)&7; - - REGS_Reg80 *fp = (REGS_Reg80*)&fxsave->FloatRegisters[st*16]; - U16 exponent = fp->sign1_exp15 & bitmask15; - U64 integer_part = fp->int1_frac63 >> 63; - U64 fraction_part = fp->int1_frac63 & bitmask63; - - // tag: 0 - normal; 1 - zero; 2 - special - tag = 2; - if(exponent == 0) - { - if(integer_part == 0 && fraction_part == 0) - { - tag = 1; - } - } - else if(exponent != bitmask15 && integer_part != 0) - { - tag = 0; - } - } - result |= tag << (2 * fpr); - } - return result; -} - -internal U16 -dmn_w32_xsave_tag_word_from_real_tag_word(U16 ftw) -{ - U16 compact = 0; - for(U32 fpr = 0; fpr < 8; fpr++) - { - U32 tag = (ftw >> (fpr * 2)) & 3; - if(tag != 3) - { - compact |= (1 << fpr); - } - } - return compact; -} - internal B32 dmn_w32_thread_read_reg_block(Arch arch, HANDLE thread, void *reg_block) { @@ -694,7 +643,7 @@ dmn_w32_thread_read_reg_block(Arch arch, HANDLE thread, void *reg_block) dst->eflags.u32 = ctx.EFlags | 0x2; dst->fcw.u16 = fxsave->ControlWord; dst->fsw.u16 = fxsave->StatusWord; - dst->ftw.u16 = dmn_w32_real_tag_word_from_xsave(fxsave); + dst->ftw.u16 = fxsave->TagWord; dst->fop.u16 = fxsave->ErrorOpcode; dst->fip.u32 = fxsave->ErrorOffset; dst->fcs.u16 = fxsave->ErrorSelector; @@ -704,7 +653,7 @@ dmn_w32_thread_read_reg_block(Arch arch, HANDLE thread, void *reg_block) dst->mxcsr_mask.u32 = fxsave->MxCsr_Mask; { M128A *float_s = fxsave->FloatRegisters; - REGS_Reg80 *float_d = &dst->fpr0; + REGS_Reg80 *float_d = &dst->st0; for(U32 n = 0; n < 8; n += 1, float_s += 1, float_d += 1) { MemoryCopy(float_d, float_s, sizeof(*float_d)); @@ -817,17 +766,15 @@ dmn_w32_thread_read_reg_block(Arch arch, HANDLE thread, void *reg_block) dst->rflags.u64 = ctx->EFlags | 0x2; dst->fcw.u16 = xsave->ControlWord; dst->fsw.u16 = xsave->StatusWord; - dst->ftw.u16 = dmn_w32_real_tag_word_from_xsave(xsave); + dst->ftw = xsave->TagWord; dst->fop.u16 = xsave->ErrorOpcode; - dst->fcs.u16 = xsave->ErrorSelector; - dst->fds.u16 = xsave->DataSelector; - dst->fip.u64 = xsave->ErrorOffset; - dst->fdp.u64 = xsave->DataOffset; + MemoryCopy(&dst->fip.u64, &xsave->ErrorOffset, sizeof(U64)); + MemoryCopy(&dst->fdp.u64, &xsave->DataOffset, sizeof(U64)); dst->mxcsr.u32 = xsave->MxCsr; dst->mxcsr_mask.u32 = xsave->MxCsr_Mask; { M128A *float_s = xsave->FloatRegisters; - REGS_Reg80 *float_d = &dst->fpr0; + REGS_Reg80 *float_d = &dst->st0; for(U32 n = 0; n < 8; n += 1, float_s += 1, float_d += 1) { MemoryCopy(float_d, float_s, sizeof(*float_d)); @@ -991,7 +938,7 @@ dmn_w32_thread_write_reg_block(Arch arch, HANDLE thread, void *reg_block) ctx.EFlags = src->eflags.u32; fxsave->ControlWord = src->fcw.u16; fxsave->StatusWord = src->fsw.u16; - fxsave->TagWord = dmn_w32_xsave_tag_word_from_real_tag_word(src->ftw.u16); + fxsave->TagWord = src->ftw.u16; fxsave->ErrorOpcode = src->fop.u16; fxsave->ErrorSelector = src->fcs.u16; fxsave->DataSelector = src->fds.u16; @@ -1001,7 +948,7 @@ dmn_w32_thread_write_reg_block(Arch arch, HANDLE thread, void *reg_block) fxsave->MxCsr_Mask = src->mxcsr_mask.u32; { M128A *float_d = fxsave->FloatRegisters; - REGS_Reg80 *float_s = &src->fpr0; + REGS_Reg80 *float_s = &src->st0; for(U32 n = 0; n < 8; n += 1, float_s += 1, float_d += 1) { MemoryCopy(float_d, float_s, 10); @@ -1098,15 +1045,13 @@ dmn_w32_thread_write_reg_block(Arch arch, HANDLE thread, void *reg_block) ctx->EFlags = src->rflags.u64; fxsave->ControlWord = src->fcw.u16; fxsave->StatusWord = src->fsw.u16; - fxsave->TagWord = dmn_w32_xsave_tag_word_from_real_tag_word(src->ftw.u16); + fxsave->TagWord = src->ftw; fxsave->ErrorOpcode = src->fop.u16; - fxsave->ErrorSelector = src->fcs.u16; - fxsave->DataSelector = src->fds.u16; - fxsave->ErrorOffset = src->fip.u64; - fxsave->DataOffset = src->fdp.u64; + MemoryCopy(&fxsave->ErrorOffset, &src->fip.u64, sizeof(U64)); + MemoryCopy(&fxsave->DataOffset, &src->fdp.u64, sizeof(U64)); { M128A *float_d = fxsave->FloatRegisters; - REGS_Reg80 *float_s = &src->fpr0; + REGS_Reg80 *float_s = &src->st0; for(U32 n = 0; n < 8; n += 1, float_s += 1, float_d += 1) { MemoryCopy(float_d, float_s, 10); diff --git a/src/demon/win32/demon_core_win32.h b/src/demon/win32/demon_core_win32.h index f5f9265e..c19b3cd4 100644 --- a/src/demon/win32/demon_core_win32.h +++ b/src/demon/win32/demon_core_win32.h @@ -350,8 +350,6 @@ internal String16 dmn_w32_read_memory_str16(Arena *arena, HANDLE process_handle, internal DMN_W32_ImageInfo dmn_w32_image_info_from_process_base_vaddr(HANDLE process, U64 base_vaddr); //- rjf: threads -internal U16 dmn_w32_real_tag_word_from_xsave(XSAVE_FORMAT *fxsave); -internal U16 dmn_w32_xsave_tag_word_from_real_tag_word(U16 ftw); internal B32 dmn_w32_thread_read_reg_block(Arch arch, HANDLE thread, void *reg_block); internal B32 dmn_w32_thread_write_reg_block(Arch arch, HANDLE thread, void *reg_block); diff --git a/src/dwarf/dwarf.h b/src/dwarf/dwarf.h index 89e9b099..4706619d 100644 --- a/src/dwarf/dwarf.h +++ b/src/dwarf/dwarf.h @@ -1618,14 +1618,14 @@ X(Xmm4, 25, ymm4, 0, 16) \ X(Xmm5, 26, ymm5, 0, 16) \ X(Xmm6, 27, ymm6, 0, 16) \ X(Xmm7, 28, ymm7, 0, 16) \ -X(Mm0, 29, fpr0, 0, 8) \ -X(Mm1, 30, fpr1, 0, 8) \ -X(Mm2, 31, fpr2, 0, 8) \ -X(Mm3, 32, fpr3, 0, 8) \ -X(Mm4, 33, fpr4, 0, 8) \ -X(Mm5, 34, fpr5, 0, 8) \ -X(Mm6, 35, fpr6, 0, 8) \ -X(Mm7, 36, fpr7, 0, 8) \ +X(Mm0, 29, st0, 0, 8) \ +X(Mm1, 30, st1, 0, 8) \ +X(Mm2, 31, st2, 0, 8) \ +X(Mm3, 32, st3, 0, 8) \ +X(Mm4, 33, st4, 0, 8) \ +X(Mm5, 34, st5, 0, 8) \ +X(Mm6, 35, st6, 0, 8) \ +X(Mm7, 36, st7, 0, 8) \ X(Fcw, 37, fcw, 0, 2) \ X(Fsw, 38, fsw, 0, 2) \ X(Mxcsr, 39, mxcsr, 0, 4) \ @@ -1635,8 +1635,8 @@ X(Ss, 42, ss, 0, 2) \ X(Ds, 43, ds, 0, 2) \ X(Fs, 44, fs, 0, 2) \ X(Gs, 45, gs, 0, 2) \ -X(Tr, 48, tr, 0, 0) \ -X(Ldtr, 49, ldtr, 0, 0) +X(Tr, 48, tr, 0, 0) \ +X(Ldtr, 49, ldtr, 0, 0) #define DW_Regs_X64_XList(X) \ X(Rax, 0, rax, 0, 8) \ @@ -1696,14 +1696,14 @@ X(St4, 37, st4, 0, 10) \ X(St5, 38, st5, 0, 10) \ X(St6, 39, st6, 0, 10) \ X(St7, 40, st7, 0, 10) \ -X(Mm0, 41, fpr0, 0, 8) \ -X(Mm1, 42, fpr1, 0, 8) \ -X(Mm2, 43, fpr2, 0, 8) \ -X(Mm3, 44, fpr3, 0, 8) \ -X(Mm4, 45, fpr4, 0, 8) \ -X(Mm5, 46, fpr5, 0, 8) \ -X(Mm6, 47, fpr6, 0, 8) \ -X(Mm7, 48, fpr7, 0, 8) \ +X(Mm0, 41, st0, 0, 8) \ +X(Mm1, 42, st1, 0, 8) \ +X(Mm2, 43, st2, 0, 8) \ +X(Mm3, 44, st3, 0, 8) \ +X(Mm4, 45, st4, 0, 8) \ +X(Mm5, 46, st5, 0, 8) \ +X(Mm6, 47, st6, 0, 8) \ +X(Mm7, 48, st7, 0, 8) \ X(Rflags, 49, rflags, 0, 4) \ X(Es, 50, es, 0, 2) \ X(Cs, 51, cs, 0, 2) \ diff --git a/src/lib_rdi/rdi.h b/src/lib_rdi/rdi.h index fd680a04..8bb3fcfe 100644 --- a/src/lib_rdi/rdi.h +++ b/src/lib_rdi/rdi.h @@ -166,48 +166,40 @@ RDI_RegCodeX86_dr4 = 17, RDI_RegCodeX86_dr5 = 18, RDI_RegCodeX86_dr6 = 19, RDI_RegCodeX86_dr7 = 20, -RDI_RegCodeX86_fpr0 = 21, -RDI_RegCodeX86_fpr1 = 22, -RDI_RegCodeX86_fpr2 = 23, -RDI_RegCodeX86_fpr3 = 24, -RDI_RegCodeX86_fpr4 = 25, -RDI_RegCodeX86_fpr5 = 26, -RDI_RegCodeX86_fpr6 = 27, -RDI_RegCodeX86_fpr7 = 28, -RDI_RegCodeX86_st0 = 29, -RDI_RegCodeX86_st1 = 30, -RDI_RegCodeX86_st2 = 31, -RDI_RegCodeX86_st3 = 32, -RDI_RegCodeX86_st4 = 33, -RDI_RegCodeX86_st5 = 34, -RDI_RegCodeX86_st6 = 35, -RDI_RegCodeX86_st7 = 36, -RDI_RegCodeX86_fcw = 37, -RDI_RegCodeX86_fsw = 38, -RDI_RegCodeX86_ftw = 39, -RDI_RegCodeX86_fop = 40, -RDI_RegCodeX86_fcs = 41, -RDI_RegCodeX86_fds = 42, -RDI_RegCodeX86_fip = 43, -RDI_RegCodeX86_fdp = 44, -RDI_RegCodeX86_mxcsr = 45, -RDI_RegCodeX86_mxcsr_mask = 46, -RDI_RegCodeX86_ss = 47, -RDI_RegCodeX86_cs = 48, -RDI_RegCodeX86_ds = 49, -RDI_RegCodeX86_es = 50, -RDI_RegCodeX86_fs = 51, -RDI_RegCodeX86_gs = 52, -RDI_RegCodeX86_ymm0 = 53, -RDI_RegCodeX86_ymm1 = 54, -RDI_RegCodeX86_ymm2 = 55, -RDI_RegCodeX86_ymm3 = 56, -RDI_RegCodeX86_ymm4 = 57, -RDI_RegCodeX86_ymm5 = 58, -RDI_RegCodeX86_ymm6 = 59, -RDI_RegCodeX86_ymm7 = 60, -RDI_RegCodeX86_tr = 61, -RDI_RegCodeX86_ldtr = 62, +RDI_RegCodeX86_st0 = 21, +RDI_RegCodeX86_st1 = 22, +RDI_RegCodeX86_st2 = 23, +RDI_RegCodeX86_st3 = 24, +RDI_RegCodeX86_st4 = 25, +RDI_RegCodeX86_st5 = 26, +RDI_RegCodeX86_st6 = 27, +RDI_RegCodeX86_st7 = 28, +RDI_RegCodeX86_fcw = 29, +RDI_RegCodeX86_fsw = 30, +RDI_RegCodeX86_ftw = 31, +RDI_RegCodeX86_fop = 32, +RDI_RegCodeX86_fcs = 33, +RDI_RegCodeX86_fds = 34, +RDI_RegCodeX86_fip = 35, +RDI_RegCodeX86_fdp = 36, +RDI_RegCodeX86_mxcsr = 37, +RDI_RegCodeX86_mxcsr_mask = 38, +RDI_RegCodeX86_ss = 39, +RDI_RegCodeX86_cs = 40, +RDI_RegCodeX86_ds = 41, +RDI_RegCodeX86_es = 42, +RDI_RegCodeX86_fs = 43, +RDI_RegCodeX86_gs = 44, +RDI_RegCodeX86_ymm0 = 45, +RDI_RegCodeX86_ymm1 = 46, +RDI_RegCodeX86_ymm2 = 47, +RDI_RegCodeX86_ymm3 = 48, +RDI_RegCodeX86_ymm4 = 49, +RDI_RegCodeX86_ymm5 = 50, +RDI_RegCodeX86_ymm6 = 51, +RDI_RegCodeX86_ymm7 = 52, +RDI_RegCodeX86_tr = 53, +RDI_RegCodeX86_ldtr = 54, } RDI_RegCodeX86Enum; typedef RDI_U8 RDI_RegCodeX64; @@ -254,70 +246,62 @@ RDI_RegCodeX64_st4 = 37, RDI_RegCodeX64_st5 = 38, RDI_RegCodeX64_st6 = 39, RDI_RegCodeX64_st7 = 40, -RDI_RegCodeX64_fpr0 = 41, -RDI_RegCodeX64_fpr1 = 42, -RDI_RegCodeX64_fpr2 = 43, -RDI_RegCodeX64_fpr3 = 44, -RDI_RegCodeX64_fpr4 = 45, -RDI_RegCodeX64_fpr5 = 46, -RDI_RegCodeX64_fpr6 = 47, -RDI_RegCodeX64_fpr7 = 48, -RDI_RegCodeX64_zmm0 = 49, -RDI_RegCodeX64_zmm1 = 50, -RDI_RegCodeX64_zmm2 = 51, -RDI_RegCodeX64_zmm3 = 52, -RDI_RegCodeX64_zmm4 = 53, -RDI_RegCodeX64_zmm5 = 54, -RDI_RegCodeX64_zmm6 = 55, -RDI_RegCodeX64_zmm7 = 56, -RDI_RegCodeX64_zmm8 = 57, -RDI_RegCodeX64_zmm9 = 58, -RDI_RegCodeX64_zmm10 = 59, -RDI_RegCodeX64_zmm11 = 60, -RDI_RegCodeX64_zmm12 = 61, -RDI_RegCodeX64_zmm13 = 62, -RDI_RegCodeX64_zmm14 = 63, -RDI_RegCodeX64_zmm15 = 64, -RDI_RegCodeX64_zmm16 = 65, -RDI_RegCodeX64_zmm17 = 66, -RDI_RegCodeX64_zmm18 = 67, -RDI_RegCodeX64_zmm19 = 68, -RDI_RegCodeX64_zmm20 = 69, -RDI_RegCodeX64_zmm21 = 70, -RDI_RegCodeX64_zmm22 = 71, -RDI_RegCodeX64_zmm23 = 72, -RDI_RegCodeX64_zmm24 = 73, -RDI_RegCodeX64_zmm25 = 74, -RDI_RegCodeX64_zmm26 = 75, -RDI_RegCodeX64_zmm27 = 76, -RDI_RegCodeX64_zmm28 = 77, -RDI_RegCodeX64_zmm29 = 78, -RDI_RegCodeX64_zmm30 = 79, -RDI_RegCodeX64_zmm31 = 80, -RDI_RegCodeX64_k0 = 81, -RDI_RegCodeX64_k1 = 82, -RDI_RegCodeX64_k2 = 83, -RDI_RegCodeX64_k3 = 84, -RDI_RegCodeX64_k4 = 85, -RDI_RegCodeX64_k5 = 86, -RDI_RegCodeX64_k6 = 87, -RDI_RegCodeX64_k7 = 88, -RDI_RegCodeX64_mxcsr = 89, -RDI_RegCodeX64_fsbase = 90, -RDI_RegCodeX64_gsbase = 91, -RDI_RegCodeX64_fcw = 92, -RDI_RegCodeX64_fsw = 93, -RDI_RegCodeX64_ftw = 94, -RDI_RegCodeX64_fop = 95, -RDI_RegCodeX64_fcs = 96, -RDI_RegCodeX64_fds = 97, -RDI_RegCodeX64_fip = 98, -RDI_RegCodeX64_fdp = 99, -RDI_RegCodeX64_mxcsr_mask = 100, -RDI_RegCodeX64_cetmsr = 101, -RDI_RegCodeX64_cetssp = 102, -RDI_RegCodeX64_tr = 103, -RDI_RegCodeX64_ldtr = 104, +RDI_RegCodeX64_zmm0 = 41, +RDI_RegCodeX64_zmm1 = 42, +RDI_RegCodeX64_zmm2 = 43, +RDI_RegCodeX64_zmm3 = 44, +RDI_RegCodeX64_zmm4 = 45, +RDI_RegCodeX64_zmm5 = 46, +RDI_RegCodeX64_zmm6 = 47, +RDI_RegCodeX64_zmm7 = 48, +RDI_RegCodeX64_zmm8 = 49, +RDI_RegCodeX64_zmm9 = 50, +RDI_RegCodeX64_zmm10 = 51, +RDI_RegCodeX64_zmm11 = 52, +RDI_RegCodeX64_zmm12 = 53, +RDI_RegCodeX64_zmm13 = 54, +RDI_RegCodeX64_zmm14 = 55, +RDI_RegCodeX64_zmm15 = 56, +RDI_RegCodeX64_zmm16 = 57, +RDI_RegCodeX64_zmm17 = 58, +RDI_RegCodeX64_zmm18 = 59, +RDI_RegCodeX64_zmm19 = 60, +RDI_RegCodeX64_zmm20 = 61, +RDI_RegCodeX64_zmm21 = 62, +RDI_RegCodeX64_zmm22 = 63, +RDI_RegCodeX64_zmm23 = 64, +RDI_RegCodeX64_zmm24 = 65, +RDI_RegCodeX64_zmm25 = 66, +RDI_RegCodeX64_zmm26 = 67, +RDI_RegCodeX64_zmm27 = 68, +RDI_RegCodeX64_zmm28 = 69, +RDI_RegCodeX64_zmm29 = 70, +RDI_RegCodeX64_zmm30 = 71, +RDI_RegCodeX64_zmm31 = 72, +RDI_RegCodeX64_k0 = 73, +RDI_RegCodeX64_k1 = 74, +RDI_RegCodeX64_k2 = 75, +RDI_RegCodeX64_k3 = 76, +RDI_RegCodeX64_k4 = 77, +RDI_RegCodeX64_k5 = 78, +RDI_RegCodeX64_k6 = 79, +RDI_RegCodeX64_k7 = 80, +RDI_RegCodeX64_mxcsr = 81, +RDI_RegCodeX64_fsbase = 82, +RDI_RegCodeX64_gsbase = 83, +RDI_RegCodeX64_fcw = 84, +RDI_RegCodeX64_fsw = 85, +RDI_RegCodeX64_ftw = 86, +RDI_RegCodeX64_fop = 87, +RDI_RegCodeX64_fcs = 88, +RDI_RegCodeX64_fds = 89, +RDI_RegCodeX64_fip = 90, +RDI_RegCodeX64_fdp = 91, +RDI_RegCodeX64_mxcsr_mask = 92, +RDI_RegCodeX64_cetmsr = 93, +RDI_RegCodeX64_cetssp = 94, +RDI_RegCodeX64_tr = 95, +RDI_RegCodeX64_ldtr = 96, } RDI_RegCodeX64Enum; typedef RDI_U32 RDI_BinarySectionFlags; @@ -664,48 +648,40 @@ X(dr4, 17)\ X(dr5, 18)\ X(dr6, 19)\ X(dr7, 20)\ -X(fpr0, 21)\ -X(fpr1, 22)\ -X(fpr2, 23)\ -X(fpr3, 24)\ -X(fpr4, 25)\ -X(fpr5, 26)\ -X(fpr6, 27)\ -X(fpr7, 28)\ -X(st0, 29)\ -X(st1, 30)\ -X(st2, 31)\ -X(st3, 32)\ -X(st4, 33)\ -X(st5, 34)\ -X(st6, 35)\ -X(st7, 36)\ -X(fcw, 37)\ -X(fsw, 38)\ -X(ftw, 39)\ -X(fop, 40)\ -X(fcs, 41)\ -X(fds, 42)\ -X(fip, 43)\ -X(fdp, 44)\ -X(mxcsr, 45)\ -X(mxcsr_mask, 46)\ -X(ss, 47)\ -X(cs, 48)\ -X(ds, 49)\ -X(es, 50)\ -X(fs, 51)\ -X(gs, 52)\ -X(ymm0, 53)\ -X(ymm1, 54)\ -X(ymm2, 55)\ -X(ymm3, 56)\ -X(ymm4, 57)\ -X(ymm5, 58)\ -X(ymm6, 59)\ -X(ymm7, 60)\ -X(tr, 61)\ -X(ldtr, 62)\ +X(st0, 21)\ +X(st1, 22)\ +X(st2, 23)\ +X(st3, 24)\ +X(st4, 25)\ +X(st5, 26)\ +X(st6, 27)\ +X(st7, 28)\ +X(fcw, 29)\ +X(fsw, 30)\ +X(ftw, 31)\ +X(fop, 32)\ +X(fcs, 33)\ +X(fds, 34)\ +X(fip, 35)\ +X(fdp, 36)\ +X(mxcsr, 37)\ +X(mxcsr_mask, 38)\ +X(ss, 39)\ +X(cs, 40)\ +X(ds, 41)\ +X(es, 42)\ +X(fs, 43)\ +X(gs, 44)\ +X(ymm0, 45)\ +X(ymm1, 46)\ +X(ymm2, 47)\ +X(ymm3, 48)\ +X(ymm4, 49)\ +X(ymm5, 50)\ +X(ymm6, 51)\ +X(ymm7, 52)\ +X(tr, 53)\ +X(ldtr, 54)\ #define RDI_RegCodeX64_XList \ X(nil, 0)\ @@ -749,70 +725,62 @@ X(st4, 37)\ X(st5, 38)\ X(st6, 39)\ X(st7, 40)\ -X(fpr0, 41)\ -X(fpr1, 42)\ -X(fpr2, 43)\ -X(fpr3, 44)\ -X(fpr4, 45)\ -X(fpr5, 46)\ -X(fpr6, 47)\ -X(fpr7, 48)\ -X(zmm0, 49)\ -X(zmm1, 50)\ -X(zmm2, 51)\ -X(zmm3, 52)\ -X(zmm4, 53)\ -X(zmm5, 54)\ -X(zmm6, 55)\ -X(zmm7, 56)\ -X(zmm8, 57)\ -X(zmm9, 58)\ -X(zmm10, 59)\ -X(zmm11, 60)\ -X(zmm12, 61)\ -X(zmm13, 62)\ -X(zmm14, 63)\ -X(zmm15, 64)\ -X(zmm16, 65)\ -X(zmm17, 66)\ -X(zmm18, 67)\ -X(zmm19, 68)\ -X(zmm20, 69)\ -X(zmm21, 70)\ -X(zmm22, 71)\ -X(zmm23, 72)\ -X(zmm24, 73)\ -X(zmm25, 74)\ -X(zmm26, 75)\ -X(zmm27, 76)\ -X(zmm28, 77)\ -X(zmm29, 78)\ -X(zmm30, 79)\ -X(zmm31, 80)\ -X(k0, 81)\ -X(k1, 82)\ -X(k2, 83)\ -X(k3, 84)\ -X(k4, 85)\ -X(k5, 86)\ -X(k6, 87)\ -X(k7, 88)\ -X(mxcsr, 89)\ -X(fsbase, 90)\ -X(gsbase, 91)\ -X(fcw, 92)\ -X(fsw, 93)\ -X(ftw, 94)\ -X(fop, 95)\ -X(fcs, 96)\ -X(fds, 97)\ -X(fip, 98)\ -X(fdp, 99)\ -X(mxcsr_mask, 100)\ -X(cetmsr, 101)\ -X(cetssp, 102)\ -X(tr, 103)\ -X(ldtr, 104)\ +X(zmm0, 41)\ +X(zmm1, 42)\ +X(zmm2, 43)\ +X(zmm3, 44)\ +X(zmm4, 45)\ +X(zmm5, 46)\ +X(zmm6, 47)\ +X(zmm7, 48)\ +X(zmm8, 49)\ +X(zmm9, 50)\ +X(zmm10, 51)\ +X(zmm11, 52)\ +X(zmm12, 53)\ +X(zmm13, 54)\ +X(zmm14, 55)\ +X(zmm15, 56)\ +X(zmm16, 57)\ +X(zmm17, 58)\ +X(zmm18, 59)\ +X(zmm19, 60)\ +X(zmm20, 61)\ +X(zmm21, 62)\ +X(zmm22, 63)\ +X(zmm23, 64)\ +X(zmm24, 65)\ +X(zmm25, 66)\ +X(zmm26, 67)\ +X(zmm27, 68)\ +X(zmm28, 69)\ +X(zmm29, 70)\ +X(zmm30, 71)\ +X(zmm31, 72)\ +X(k0, 73)\ +X(k1, 74)\ +X(k2, 75)\ +X(k3, 76)\ +X(k4, 77)\ +X(k5, 78)\ +X(k6, 79)\ +X(k7, 80)\ +X(mxcsr, 81)\ +X(fsbase, 82)\ +X(gsbase, 83)\ +X(fcw, 84)\ +X(fsw, 85)\ +X(ftw, 86)\ +X(fop, 87)\ +X(fcs, 88)\ +X(fds, 89)\ +X(fip, 90)\ +X(fdp, 91)\ +X(mxcsr_mask, 92)\ +X(cetmsr, 93)\ +X(cetssp, 94)\ +X(tr, 95)\ +X(ldtr, 96)\ #define RDI_TopLevelInfo_XList \ X(RDI_Arch, arch)\ diff --git a/src/rdi/rdi.mdesk b/src/rdi/rdi.mdesk index 3e73f1ac..214ca3f5 100644 --- a/src/rdi/rdi.mdesk +++ b/src/rdi/rdi.mdesk @@ -306,48 +306,40 @@ RDI_RegCodeX86Table: {dr5 18} {dr6 19} {dr7 20} - {fpr0 21} - {fpr1 22} - {fpr2 23} - {fpr3 24} - {fpr4 25} - {fpr5 26} - {fpr6 27} - {fpr7 28} - {st0 29} - {st1 30} - {st2 31} - {st3 32} - {st4 33} - {st5 34} - {st6 35} - {st7 36} - {fcw 37} - {fsw 38} - {ftw 39} - {fop 40} - {fcs 41} - {fds 42} - {fip 43} - {fdp 44} - {mxcsr 45} - {mxcsr_mask 46} - {ss 47} - {cs 48} - {ds 49} - {es 50} - {fs 51} - {gs 52} - {ymm0 53} - {ymm1 54} - {ymm2 55} - {ymm3 56} - {ymm4 57} - {ymm5 58} - {ymm6 59} - {ymm7 60} - {tr 61} - {ldtr 62} + {st0 21} + {st1 22} + {st2 23} + {st3 24} + {st4 25} + {st5 26} + {st6 27} + {st7 28} + {fcw 29} + {fsw 30} + {ftw 31} + {fop 32} + {fcs 33} + {fds 34} + {fip 35} + {fdp 36} + {mxcsr 37} + {mxcsr_mask 38} + {ss 39} + {cs 40} + {ds 41} + {es 42} + {fs 43} + {gs 44} + {ymm0 45} + {ymm1 46} + {ymm2 47} + {ymm3 48} + {ymm4 49} + {ymm5 50} + {ymm6 51} + {ymm7 52} + {tr 53} + {ldtr 54} } @table(name value) @@ -394,70 +386,62 @@ RDI_RegCodeX64Table: {st5 38} {st6 39} {st7 40} - {fpr0 41} - {fpr1 42} - {fpr2 43} - {fpr3 44} - {fpr4 45} - {fpr5 46} - {fpr6 47} - {fpr7 48} - {zmm0 49} - {zmm1 50} - {zmm2 51} - {zmm3 52} - {zmm4 53} - {zmm5 54} - {zmm6 55} - {zmm7 56} - {zmm8 57} - {zmm9 58} - {zmm10 59} - {zmm11 60} - {zmm12 61} - {zmm13 62} - {zmm14 63} - {zmm15 64} - {zmm16 65} - {zmm17 66} - {zmm18 67} - {zmm19 68} - {zmm20 69} - {zmm21 70} - {zmm22 71} - {zmm23 72} - {zmm24 73} - {zmm25 74} - {zmm26 75} - {zmm27 76} - {zmm28 77} - {zmm29 78} - {zmm30 79} - {zmm31 80} - {k0 81} - {k1 82} - {k2 83} - {k3 84} - {k4 85} - {k5 86} - {k6 87} - {k7 88} - {mxcsr 89} - {fsbase 90} - {gsbase 91} - {fcw 92} - {fsw 93} - {ftw 94} - {fop 95} - {fcs 96} - {fds 97} - {fip 98} - {fdp 99} - {mxcsr_mask 100} - {cetmsr 101} - {cetssp 102} - {tr 103} - {ldtr 104} + {zmm0 41} + {zmm1 42} + {zmm2 43} + {zmm3 44} + {zmm4 45} + {zmm5 46} + {zmm6 47} + {zmm7 48} + {zmm8 49} + {zmm9 50} + {zmm10 51} + {zmm11 52} + {zmm12 53} + {zmm13 54} + {zmm14 55} + {zmm15 56} + {zmm16 57} + {zmm17 58} + {zmm18 59} + {zmm19 60} + {zmm20 61} + {zmm21 62} + {zmm22 63} + {zmm23 64} + {zmm24 65} + {zmm25 66} + {zmm26 67} + {zmm27 68} + {zmm28 69} + {zmm29 70} + {zmm30 71} + {zmm31 72} + {k0 73} + {k1 74} + {k2 75} + {k3 76} + {k4 77} + {k5 78} + {k6 79} + {k7 80} + {mxcsr 81} + {fsbase 82} + {gsbase 83} + {fcw 84} + {fsw 85} + {ftw 86} + {fop 87} + {fcs 88} + {fds 89} + {fip 90} + {fdp 91} + {mxcsr_mask 92} + {cetmsr 93} + {cetssp 94} + {tr 95} + {ldtr 96} } @enum(RDI_U32) RDI_Arch: diff --git a/src/regs/generated/regs.meta.c b/src/regs/generated/regs.meta.c index cd5fca12..66f1a886 100644 --- a/src/regs/generated/regs.meta.c +++ b/src/regs/generated/regs.meta.c @@ -103,7 +103,7 @@ case Arch_x86:{result = regs_g_alias_code_x86_usage_kind_table;}break; return result; } C_LINKAGE_BEGIN -REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[105] = +REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[95] = { REGS_UsageKind_Normal, REGS_UsageKind_Normal, @@ -156,16 +156,6 @@ REGS_UsageKind_Normal, REGS_UsageKind_Normal, REGS_UsageKind_Normal, REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, REGS_UsageKind_Vector, REGS_UsageKind_Vector, REGS_UsageKind_Vector, @@ -312,7 +302,7 @@ REGS_UsageKind_Vector, REGS_UsageKind_Vector, }; -String8 regs_g_reg_code_x64_string_table[105] = +String8 regs_g_reg_code_x64_string_table[95] = { str8_lit_comp(""), str8_lit_comp("rax"), @@ -343,14 +333,6 @@ str8_lit_comp("dr4"), str8_lit_comp("dr5"), str8_lit_comp("dr6"), str8_lit_comp("dr7"), -str8_lit_comp("fpr0"), -str8_lit_comp("fpr1"), -str8_lit_comp("fpr2"), -str8_lit_comp("fpr3"), -str8_lit_comp("fpr4"), -str8_lit_comp("fpr5"), -str8_lit_comp("fpr6"), -str8_lit_comp("fpr7"), str8_lit_comp("st0"), str8_lit_comp("st1"), str8_lit_comp("st2"), @@ -363,8 +345,6 @@ str8_lit_comp("fcw"), str8_lit_comp("fsw"), str8_lit_comp("ftw"), str8_lit_comp("fop"), -str8_lit_comp("fcs"), -str8_lit_comp("fds"), str8_lit_comp("fip"), str8_lit_comp("fdp"), str8_lit_comp("mxcsr"), @@ -521,7 +501,7 @@ str8_lit_comp("mm6"), str8_lit_comp("mm7"), }; -REGS_Rng regs_g_reg_code_x64_rng_table[105] = +REGS_Rng regs_g_reg_code_x64_rng_table[95] = { {0}, {(U16)OffsetOf(REGS_RegBlockX64, rax), 8}, @@ -552,14 +532,6 @@ REGS_Rng regs_g_reg_code_x64_rng_table[105] = {(U16)OffsetOf(REGS_RegBlockX64, dr5), 8}, {(U16)OffsetOf(REGS_RegBlockX64, dr6), 8}, {(U16)OffsetOf(REGS_RegBlockX64, dr7), 8}, -{(U16)OffsetOf(REGS_RegBlockX64, fpr0), 10}, -{(U16)OffsetOf(REGS_RegBlockX64, fpr1), 10}, -{(U16)OffsetOf(REGS_RegBlockX64, fpr2), 10}, -{(U16)OffsetOf(REGS_RegBlockX64, fpr3), 10}, -{(U16)OffsetOf(REGS_RegBlockX64, fpr4), 10}, -{(U16)OffsetOf(REGS_RegBlockX64, fpr5), 10}, -{(U16)OffsetOf(REGS_RegBlockX64, fpr6), 10}, -{(U16)OffsetOf(REGS_RegBlockX64, fpr7), 10}, {(U16)OffsetOf(REGS_RegBlockX64, st0), 10}, {(U16)OffsetOf(REGS_RegBlockX64, st1), 10}, {(U16)OffsetOf(REGS_RegBlockX64, st2), 10}, @@ -570,10 +542,8 @@ REGS_Rng regs_g_reg_code_x64_rng_table[105] = {(U16)OffsetOf(REGS_RegBlockX64, st7), 10}, {(U16)OffsetOf(REGS_RegBlockX64, fcw), 2}, {(U16)OffsetOf(REGS_RegBlockX64, fsw), 2}, -{(U16)OffsetOf(REGS_RegBlockX64, ftw), 2}, +{(U16)OffsetOf(REGS_RegBlockX64, ftw), 1}, {(U16)OffsetOf(REGS_RegBlockX64, fop), 2}, -{(U16)OffsetOf(REGS_RegBlockX64, fcs), 2}, -{(U16)OffsetOf(REGS_RegBlockX64, fds), 2}, {(U16)OffsetOf(REGS_RegBlockX64, fip), 8}, {(U16)OffsetOf(REGS_RegBlockX64, fdp), 8}, {(U16)OffsetOf(REGS_RegBlockX64, mxcsr), 4}, @@ -720,17 +690,17 @@ REGS_Slice regs_g_alias_code_x64_slice_table[96] = {REGS_RegCodeX64_zmm13, 0, 32}, {REGS_RegCodeX64_zmm14, 0, 32}, {REGS_RegCodeX64_zmm15, 0, 32}, -{REGS_RegCodeX64_fpr0, 0, 8}, -{REGS_RegCodeX64_fpr1, 0, 8}, -{REGS_RegCodeX64_fpr2, 0, 8}, -{REGS_RegCodeX64_fpr3, 0, 8}, -{REGS_RegCodeX64_fpr4, 0, 8}, -{REGS_RegCodeX64_fpr5, 0, 8}, -{REGS_RegCodeX64_fpr6, 0, 8}, -{REGS_RegCodeX64_fpr7, 0, 8}, +{REGS_RegCodeX64_st0, 0, 8}, +{REGS_RegCodeX64_st1, 0, 8}, +{REGS_RegCodeX64_st2, 0, 8}, +{REGS_RegCodeX64_st3, 0, 8}, +{REGS_RegCodeX64_st4, 0, 8}, +{REGS_RegCodeX64_st5, 0, 8}, +{REGS_RegCodeX64_st6, 0, 8}, +{REGS_RegCodeX64_st7, 0, 8}, }; -REGS_UsageKind regs_g_reg_code_x86_usage_kind_table[63] = +REGS_UsageKind regs_g_reg_code_x86_usage_kind_table[55] = { REGS_UsageKind_Normal, REGS_UsageKind_Normal, @@ -779,14 +749,6 @@ REGS_UsageKind_Normal, REGS_UsageKind_Normal, REGS_UsageKind_Normal, REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, -REGS_UsageKind_Normal, REGS_UsageKind_Vector, REGS_UsageKind_Vector, REGS_UsageKind_Vector, @@ -837,7 +799,7 @@ REGS_UsageKind_Vector, REGS_UsageKind_Vector, }; -String8 regs_g_reg_code_x86_string_table[63] = +String8 regs_g_reg_code_x86_string_table[55] = { str8_lit_comp(""), str8_lit_comp("eax"), @@ -860,14 +822,6 @@ str8_lit_comp("dr4"), str8_lit_comp("dr5"), str8_lit_comp("dr6"), str8_lit_comp("dr7"), -str8_lit_comp("fpr0"), -str8_lit_comp("fpr1"), -str8_lit_comp("fpr2"), -str8_lit_comp("fpr3"), -str8_lit_comp("fpr4"), -str8_lit_comp("fpr5"), -str8_lit_comp("fpr6"), -str8_lit_comp("fpr7"), str8_lit_comp("st0"), str8_lit_comp("st1"), str8_lit_comp("st2"), @@ -944,7 +898,7 @@ str8_lit_comp("mm6"), str8_lit_comp("mm7"), }; -REGS_Rng regs_g_reg_code_x86_rng_table[63] = +REGS_Rng regs_g_reg_code_x86_rng_table[55] = { {0}, {(U16)OffsetOf(REGS_RegBlockX86, eax), 4}, @@ -967,14 +921,6 @@ REGS_Rng regs_g_reg_code_x86_rng_table[63] = {(U16)OffsetOf(REGS_RegBlockX86, dr5), 4}, {(U16)OffsetOf(REGS_RegBlockX86, dr6), 4}, {(U16)OffsetOf(REGS_RegBlockX86, dr7), 4}, -{(U16)OffsetOf(REGS_RegBlockX86, fpr0), 10}, -{(U16)OffsetOf(REGS_RegBlockX86, fpr1), 10}, -{(U16)OffsetOf(REGS_RegBlockX86, fpr2), 10}, -{(U16)OffsetOf(REGS_RegBlockX86, fpr3), 10}, -{(U16)OffsetOf(REGS_RegBlockX86, fpr4), 10}, -{(U16)OffsetOf(REGS_RegBlockX86, fpr5), 10}, -{(U16)OffsetOf(REGS_RegBlockX86, fpr6), 10}, -{(U16)OffsetOf(REGS_RegBlockX86, fpr7), 10}, {(U16)OffsetOf(REGS_RegBlockX86, st0), 10}, {(U16)OffsetOf(REGS_RegBlockX86, st1), 10}, {(U16)OffsetOf(REGS_RegBlockX86, st2), 10}, @@ -1041,14 +987,14 @@ REGS_Slice regs_g_alias_code_x86_slice_table[36] = {REGS_RegCodeX86_ymm5, 0, 16}, {REGS_RegCodeX86_ymm6, 0, 16}, {REGS_RegCodeX86_ymm7, 0, 16}, -{REGS_RegCodeX86_fpr0, 0, 8}, -{REGS_RegCodeX86_fpr1, 0, 8}, -{REGS_RegCodeX86_fpr2, 0, 8}, -{REGS_RegCodeX86_fpr3, 0, 8}, -{REGS_RegCodeX86_fpr4, 0, 8}, -{REGS_RegCodeX86_fpr5, 0, 8}, -{REGS_RegCodeX86_fpr6, 0, 8}, -{REGS_RegCodeX86_fpr7, 0, 8}, +{REGS_RegCodeX86_st0, 0, 8}, +{REGS_RegCodeX86_st1, 0, 8}, +{REGS_RegCodeX86_st2, 0, 8}, +{REGS_RegCodeX86_st3, 0, 8}, +{REGS_RegCodeX86_st4, 0, 8}, +{REGS_RegCodeX86_st5, 0, 8}, +{REGS_RegCodeX86_st6, 0, 8}, +{REGS_RegCodeX86_st7, 0, 8}, }; C_LINKAGE_END diff --git a/src/regs/generated/regs.meta.h b/src/regs/generated/regs.meta.h index d5819953..2490022d 100644 --- a/src/regs/generated/regs.meta.h +++ b/src/regs/generated/regs.meta.h @@ -37,14 +37,6 @@ REGS_RegCodeX64_dr4, REGS_RegCodeX64_dr5, REGS_RegCodeX64_dr6, REGS_RegCodeX64_dr7, -REGS_RegCodeX64_fpr0, -REGS_RegCodeX64_fpr1, -REGS_RegCodeX64_fpr2, -REGS_RegCodeX64_fpr3, -REGS_RegCodeX64_fpr4, -REGS_RegCodeX64_fpr5, -REGS_RegCodeX64_fpr6, -REGS_RegCodeX64_fpr7, REGS_RegCodeX64_st0, REGS_RegCodeX64_st1, REGS_RegCodeX64_st2, @@ -57,8 +49,6 @@ REGS_RegCodeX64_fcw, REGS_RegCodeX64_fsw, REGS_RegCodeX64_ftw, REGS_RegCodeX64_fop, -REGS_RegCodeX64_fcs, -REGS_RegCodeX64_fds, REGS_RegCodeX64_fip, REGS_RegCodeX64_fdp, REGS_RegCodeX64_mxcsr, @@ -240,14 +230,6 @@ REGS_RegCodeX86_dr4, REGS_RegCodeX86_dr5, REGS_RegCodeX86_dr6, REGS_RegCodeX86_dr7, -REGS_RegCodeX86_fpr0, -REGS_RegCodeX86_fpr1, -REGS_RegCodeX86_fpr2, -REGS_RegCodeX86_fpr3, -REGS_RegCodeX86_fpr4, -REGS_RegCodeX86_fpr5, -REGS_RegCodeX86_fpr6, -REGS_RegCodeX86_fpr7, REGS_RegCodeX86_st0, REGS_RegCodeX86_st1, REGS_RegCodeX86_st2, @@ -357,14 +339,6 @@ REGS_Reg64 dr4; REGS_Reg64 dr5; REGS_Reg64 dr6; REGS_Reg64 dr7; -REGS_Reg80 fpr0; -REGS_Reg80 fpr1; -REGS_Reg80 fpr2; -REGS_Reg80 fpr3; -REGS_Reg80 fpr4; -REGS_Reg80 fpr5; -REGS_Reg80 fpr6; -REGS_Reg80 fpr7; REGS_Reg80 st0; REGS_Reg80 st1; REGS_Reg80 st2; @@ -375,10 +349,8 @@ REGS_Reg80 st6; REGS_Reg80 st7; REGS_Reg16 fcw; REGS_Reg16 fsw; -REGS_Reg16 ftw; +REGS_Reg8 ftw; REGS_Reg16 fop; -REGS_Reg16 fcs; -REGS_Reg16 fds; REGS_Reg64 fip; REGS_Reg64 fdp; REGS_Reg32 mxcsr; @@ -458,14 +430,6 @@ REGS_Reg32 dr4; REGS_Reg32 dr5; REGS_Reg32 dr6; REGS_Reg32 dr7; -REGS_Reg80 fpr0; -REGS_Reg80 fpr1; -REGS_Reg80 fpr2; -REGS_Reg80 fpr3; -REGS_Reg80 fpr4; -REGS_Reg80 fpr5; -REGS_Reg80 fpr6; -REGS_Reg80 fpr7; REGS_Reg80 st0; REGS_Reg80 st1; REGS_Reg80 st2; @@ -503,17 +467,17 @@ REGS_Reg256 ymm7; }; C_LINKAGE_BEGIN -extern REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[105]; +extern REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[95]; extern REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[96]; -extern String8 regs_g_reg_code_x64_string_table[105]; +extern String8 regs_g_reg_code_x64_string_table[95]; extern String8 regs_g_alias_code_x64_string_table[96]; -extern REGS_Rng regs_g_reg_code_x64_rng_table[105]; +extern REGS_Rng regs_g_reg_code_x64_rng_table[95]; extern REGS_Slice regs_g_alias_code_x64_slice_table[96]; -extern REGS_UsageKind regs_g_reg_code_x86_usage_kind_table[63]; +extern REGS_UsageKind regs_g_reg_code_x86_usage_kind_table[55]; extern REGS_UsageKind regs_g_alias_code_x86_usage_kind_table[36]; -extern String8 regs_g_reg_code_x86_string_table[63]; +extern String8 regs_g_reg_code_x86_string_table[55]; extern String8 regs_g_alias_code_x86_string_table[36]; -extern REGS_Rng regs_g_reg_code_x86_rng_table[63]; +extern REGS_Rng regs_g_reg_code_x86_rng_table[55]; extern REGS_Slice regs_g_alias_code_x86_slice_table[36]; C_LINKAGE_END diff --git a/src/regs/rdi/generated/regs_rdi.meta.c b/src/regs/rdi/generated/regs_rdi.meta.c index 62069a6f..cfdb9754 100644 --- a/src/regs/rdi/generated/regs_rdi.meta.c +++ b/src/regs/rdi/generated/regs_rdi.meta.c @@ -42,14 +42,6 @@ case REGS_RegCodeX64_dr4:{result = RDI_RegCodeX64_dr4;}break; case REGS_RegCodeX64_dr5:{result = RDI_RegCodeX64_dr5;}break; case REGS_RegCodeX64_dr6:{result = RDI_RegCodeX64_dr6;}break; case REGS_RegCodeX64_dr7:{result = RDI_RegCodeX64_dr7;}break; -case REGS_RegCodeX64_fpr0:{result = RDI_RegCodeX64_fpr0;}break; -case REGS_RegCodeX64_fpr1:{result = RDI_RegCodeX64_fpr1;}break; -case REGS_RegCodeX64_fpr2:{result = RDI_RegCodeX64_fpr2;}break; -case REGS_RegCodeX64_fpr3:{result = RDI_RegCodeX64_fpr3;}break; -case REGS_RegCodeX64_fpr4:{result = RDI_RegCodeX64_fpr4;}break; -case REGS_RegCodeX64_fpr5:{result = RDI_RegCodeX64_fpr5;}break; -case REGS_RegCodeX64_fpr6:{result = RDI_RegCodeX64_fpr6;}break; -case REGS_RegCodeX64_fpr7:{result = RDI_RegCodeX64_fpr7;}break; case REGS_RegCodeX64_st0:{result = RDI_RegCodeX64_st0;}break; case REGS_RegCodeX64_st1:{result = RDI_RegCodeX64_st1;}break; case REGS_RegCodeX64_st2:{result = RDI_RegCodeX64_st2;}break; @@ -62,8 +54,6 @@ case REGS_RegCodeX64_fcw:{result = RDI_RegCodeX64_fcw;}break; case REGS_RegCodeX64_fsw:{result = RDI_RegCodeX64_fsw;}break; case REGS_RegCodeX64_ftw:{result = RDI_RegCodeX64_ftw;}break; case REGS_RegCodeX64_fop:{result = RDI_RegCodeX64_fop;}break; -case REGS_RegCodeX64_fcs:{result = RDI_RegCodeX64_fcs;}break; -case REGS_RegCodeX64_fds:{result = RDI_RegCodeX64_fds;}break; case REGS_RegCodeX64_fip:{result = RDI_RegCodeX64_fip;}break; case REGS_RegCodeX64_fdp:{result = RDI_RegCodeX64_fdp;}break; case REGS_RegCodeX64_mxcsr:{result = RDI_RegCodeX64_mxcsr;}break; @@ -145,14 +135,6 @@ case REGS_RegCodeX86_dr4:{result = RDI_RegCodeX86_dr4;}break; case REGS_RegCodeX86_dr5:{result = RDI_RegCodeX86_dr5;}break; case REGS_RegCodeX86_dr6:{result = RDI_RegCodeX86_dr6;}break; case REGS_RegCodeX86_dr7:{result = RDI_RegCodeX86_dr7;}break; -case REGS_RegCodeX86_fpr0:{result = RDI_RegCodeX86_fpr0;}break; -case REGS_RegCodeX86_fpr1:{result = RDI_RegCodeX86_fpr1;}break; -case REGS_RegCodeX86_fpr2:{result = RDI_RegCodeX86_fpr2;}break; -case REGS_RegCodeX86_fpr3:{result = RDI_RegCodeX86_fpr3;}break; -case REGS_RegCodeX86_fpr4:{result = RDI_RegCodeX86_fpr4;}break; -case REGS_RegCodeX86_fpr5:{result = RDI_RegCodeX86_fpr5;}break; -case REGS_RegCodeX86_fpr6:{result = RDI_RegCodeX86_fpr6;}break; -case REGS_RegCodeX86_fpr7:{result = RDI_RegCodeX86_fpr7;}break; case REGS_RegCodeX86_st0:{result = RDI_RegCodeX86_st0;}break; case REGS_RegCodeX86_st1:{result = RDI_RegCodeX86_st1;}break; case REGS_RegCodeX86_st2:{result = RDI_RegCodeX86_st2;}break; @@ -231,14 +213,6 @@ case RDI_RegCodeX64_dr4:{result = REGS_RegCodeX64_dr4;}break; case RDI_RegCodeX64_dr5:{result = REGS_RegCodeX64_dr5;}break; case RDI_RegCodeX64_dr6:{result = REGS_RegCodeX64_dr6;}break; case RDI_RegCodeX64_dr7:{result = REGS_RegCodeX64_dr7;}break; -case RDI_RegCodeX64_fpr0:{result = REGS_RegCodeX64_fpr0;}break; -case RDI_RegCodeX64_fpr1:{result = REGS_RegCodeX64_fpr1;}break; -case RDI_RegCodeX64_fpr2:{result = REGS_RegCodeX64_fpr2;}break; -case RDI_RegCodeX64_fpr3:{result = REGS_RegCodeX64_fpr3;}break; -case RDI_RegCodeX64_fpr4:{result = REGS_RegCodeX64_fpr4;}break; -case RDI_RegCodeX64_fpr5:{result = REGS_RegCodeX64_fpr5;}break; -case RDI_RegCodeX64_fpr6:{result = REGS_RegCodeX64_fpr6;}break; -case RDI_RegCodeX64_fpr7:{result = REGS_RegCodeX64_fpr7;}break; case RDI_RegCodeX64_st0:{result = REGS_RegCodeX64_st0;}break; case RDI_RegCodeX64_st1:{result = REGS_RegCodeX64_st1;}break; case RDI_RegCodeX64_st2:{result = REGS_RegCodeX64_st2;}break; @@ -251,8 +225,6 @@ case RDI_RegCodeX64_fcw:{result = REGS_RegCodeX64_fcw;}break; case RDI_RegCodeX64_fsw:{result = REGS_RegCodeX64_fsw;}break; case RDI_RegCodeX64_ftw:{result = REGS_RegCodeX64_ftw;}break; case RDI_RegCodeX64_fop:{result = REGS_RegCodeX64_fop;}break; -case RDI_RegCodeX64_fcs:{result = REGS_RegCodeX64_fcs;}break; -case RDI_RegCodeX64_fds:{result = REGS_RegCodeX64_fds;}break; case RDI_RegCodeX64_fip:{result = REGS_RegCodeX64_fip;}break; case RDI_RegCodeX64_fdp:{result = REGS_RegCodeX64_fdp;}break; case RDI_RegCodeX64_mxcsr:{result = REGS_RegCodeX64_mxcsr;}break; @@ -334,14 +306,6 @@ case RDI_RegCodeX86_dr4:{result = REGS_RegCodeX86_dr4;}break; case RDI_RegCodeX86_dr5:{result = REGS_RegCodeX86_dr5;}break; case RDI_RegCodeX86_dr6:{result = REGS_RegCodeX86_dr6;}break; case RDI_RegCodeX86_dr7:{result = REGS_RegCodeX86_dr7;}break; -case RDI_RegCodeX86_fpr0:{result = REGS_RegCodeX86_fpr0;}break; -case RDI_RegCodeX86_fpr1:{result = REGS_RegCodeX86_fpr1;}break; -case RDI_RegCodeX86_fpr2:{result = REGS_RegCodeX86_fpr2;}break; -case RDI_RegCodeX86_fpr3:{result = REGS_RegCodeX86_fpr3;}break; -case RDI_RegCodeX86_fpr4:{result = REGS_RegCodeX86_fpr4;}break; -case RDI_RegCodeX86_fpr5:{result = REGS_RegCodeX86_fpr5;}break; -case RDI_RegCodeX86_fpr6:{result = REGS_RegCodeX86_fpr6;}break; -case RDI_RegCodeX86_fpr7:{result = REGS_RegCodeX86_fpr7;}break; case RDI_RegCodeX86_st0:{result = REGS_RegCodeX86_st0;}break; case RDI_RegCodeX86_st1:{result = REGS_RegCodeX86_st1;}break; case RDI_RegCodeX86_st2:{result = REGS_RegCodeX86_st2;}break; diff --git a/src/regs/regs.h b/src/regs/regs.h index 27c1efcd..76214f41 100644 --- a/src/regs/regs.h +++ b/src/regs/regs.h @@ -20,6 +20,8 @@ REGS_UsageKind; typedef U8 REGS_RegCode; typedef U8 REGS_AliasCode; +typedef U8 REGS_Reg8; + typedef union REGS_Reg16 REGS_Reg16; union REGS_Reg16 { @@ -39,6 +41,7 @@ typedef union REGS_Reg64 REGS_Reg64; union REGS_Reg64 { U8 v[8]; + U32 u32[2]; U64 u64; F64 f64; }; diff --git a/src/regs/regs.mdesk b/src/regs/regs.mdesk index 1f0cb270..cd05c10a 100644 --- a/src/regs/regs.mdesk +++ b/src/regs/regs.mdesk @@ -35,14 +35,6 @@ REGS_RegTableX64: {dr5 64 Normal} {dr6 64 Normal} {dr7 64 Normal} - {fpr0 80 Normal} - {fpr1 80 Normal} - {fpr2 80 Normal} - {fpr3 80 Normal} - {fpr4 80 Normal} - {fpr5 80 Normal} - {fpr6 80 Normal} - {fpr7 80 Normal} {st0 80 Normal} {st1 80 Normal} {st2 80 Normal} @@ -53,10 +45,8 @@ REGS_RegTableX64: {st7 80 Normal} {fcw 16 Normal} {fsw 16 Normal} - {ftw 16 Normal} + {ftw 8 Normal} {fop 16 Normal} - {fcs 16 Normal} - {fds 16 Normal} {fip 64 Normal} {fdp 64 Normal} {mxcsr 32 Normal} @@ -206,14 +196,14 @@ REGS_AliasTableX64: {ymm13 zmm13 0 256 Vector} {ymm14 zmm14 0 256 Vector} {ymm15 zmm15 0 256 Vector} - {mm0 fpr0 0 64 Vector} - {mm1 fpr1 0 64 Vector} - {mm2 fpr2 0 64 Vector} - {mm3 fpr3 0 64 Vector} - {mm4 fpr4 0 64 Vector} - {mm5 fpr5 0 64 Vector} - {mm6 fpr6 0 64 Vector} - {mm7 fpr7 0 64 Vector} + {mm0 st0 0 64 Vector} + {mm1 st1 0 64 Vector} + {mm2 st2 0 64 Vector} + {mm3 st3 0 64 Vector} + {mm4 st4 0 64 Vector} + {mm5 st5 0 64 Vector} + {mm6 st6 0 64 Vector} + {mm7 st7 0 64 Vector} } //////////////////////////////// @@ -246,14 +236,6 @@ REGS_RegTableX86: // TODO(allen): I am suspicious of this stuff here. // Are fpr0-7 and st0-7 actually different things? Visual studio doesn't show // frp0-7. Not sure if the mm0-7 aliases are setup the right way either. - {fpr0 80 Normal} - {fpr1 80 Normal} - {fpr2 80 Normal} - {fpr3 80 Normal} - {fpr4 80 Normal} - {fpr5 80 Normal} - {fpr6 80 Normal} - {fpr7 80 Normal} {st0 80 Normal} {st1 80 Normal} {st2 80 Normal} @@ -322,14 +304,14 @@ REGS_AliasTableX86: {xmm5 ymm5 0 128 Vector} {xmm6 ymm6 0 128 Vector} {xmm7 ymm7 0 128 Vector} - {mm0 fpr0 0 64 Vector} - {mm1 fpr1 0 64 Vector} - {mm2 fpr2 0 64 Vector} - {mm3 fpr3 0 64 Vector} - {mm4 fpr4 0 64 Vector} - {mm5 fpr5 0 64 Vector} - {mm6 fpr6 0 64 Vector} - {mm7 fpr7 0 64 Vector} + {mm0 st0 0 64 Vector} + {mm1 st1 0 64 Vector} + {mm2 st2 0 64 Vector} + {mm3 st3 0 64 Vector} + {mm4 st4 0 64 Vector} + {mm5 st5 0 64 Vector} + {mm6 st6 0 64 Vector} + {mm7 st7 0 64 Vector} } //////////////////////////////// diff --git a/src/x64/x64.h b/src/x64/x64.h index 93dfe433..8a41a154 100644 --- a/src/x64/x64.h +++ b/src/x64/x64.h @@ -36,22 +36,13 @@ enum typedef struct AlignType(16) X64_FXSave { - U16 fcw; - U16 fsw; - U16 ftw; - U16 fop; - union { - struct { - U64 fip; - U64 fdp; - } b64; - struct { - U32 fip; - U16 fcs, _pad0; - U32 fdp; - U16 fds, _pad1; - } b32; - }; + U16 fcw; + U16 fsw; + U8 ftw; + U8 reserved1; + U16 fop; + U64 fip; + U64 fdp; U32 mxcsr; U32 mxcsr_mask; U128 st_space[8];