ed/raddebugger
1
0
Fork 0
mirror of https://github.com/Ed94/raddebugger.git synced 2026-08-14 17:28:07 +00:00
Code Issues Packages Projects Releases Wiki Activity

remove privileged registers

Browse Source
This commit is contained in:
Nikita Smith
2025-12-05 17:03:05 -08:00
parent 8005c31276
commit 9659ab4ad2
7 changed files with 10 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/dwarf/dwarf.h
+4 -3
View File
@@ -1664,9 +1664,10 @@ X(Ds, 53, ds, 0, 2) \
X(Fs, 54, fs, 0, 2) \ X(Fs, 54, fs, 0, 2) \
X(Gs, 55, gs, 0, 2) \ X(Gs, 55, gs, 0, 2) \
X(FsBase, 58, fsbase, 0, 0) \ X(FsBase, 58, fsbase, 0, 0) \
X(GsBase, 59, gsbase, 0, 0) \ X(GsBase, 59, gsbase, 0, 0)
X(Tr, 62, tr, 0, 0) \ // privileged registers:
X(Ldtr, 63, ldtr, 0, 0) // X(Tr, 62, nil, 0, 0) \
// X(Ldtr, 63, nil, 0, 0)
typedef U32 DW_Reg; typedef U32 DW_Reg;
src/lib_rdi/rdi.h
-4
View File
@@ -239,8 +239,6 @@ RDI_RegCodeX64_fdp = 91,
RDI_RegCodeX64_mxcsr_mask = 92, RDI_RegCodeX64_mxcsr_mask = 92,
RDI_RegCodeX64_cetmsr = 93, RDI_RegCodeX64_cetmsr = 93,
RDI_RegCodeX64_cetssp = 94, RDI_RegCodeX64_cetssp = 94,
RDI_RegCodeX64_tr = 95,
RDI_RegCodeX64_ldtr = 96,
} RDI_RegCodeX64Enum; } RDI_RegCodeX64Enum;
typedef RDI_U32 RDI_BinarySectionFlags; typedef RDI_U32 RDI_BinarySectionFlags;
@@ -660,8 +658,6 @@ X(fdp, 91)\
X(mxcsr_mask, 92)\ X(mxcsr_mask, 92)\
X(cetmsr, 93)\ X(cetmsr, 93)\
X(cetssp, 94)\ X(cetssp, 94)\
X(tr, 95)\
X(ldtr, 96)\
#define RDI_TopLevelInfo_XList \ #define RDI_TopLevelInfo_XList \
X(RDI_Arch, arch)\ X(RDI_Arch, arch)\
src/rdi/rdi.mdesk
-2
View File
@@ -379,8 +379,6 @@ RDI_RegCodeX64Table:
{mxcsr_mask 92} {mxcsr_mask 92}
{cetmsr 93} {cetmsr 93}
{cetssp 94} {cetssp 94}
{tr 95}
{ldtr 96}
} }
@enum(RDI_U32) RDI_Arch: @enum(RDI_U32) RDI_Arch:
src/regs/generated/regs.meta.c
+3 -9
View File
@@ -94,7 +94,7 @@ case Arch_x64:{result = regs_g_alias_code_x64_usage_kind_table;}break;
return result; return result;
} }
C_LINKAGE_BEGIN C_LINKAGE_BEGIN
REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[95] = REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[93] =
{ {
REGS_UsageKind_Normal, REGS_UsageKind_Normal,
REGS_UsageKind_Normal, REGS_UsageKind_Normal,
@@ -189,8 +189,6 @@ REGS_UsageKind_Normal,
REGS_UsageKind_Normal, REGS_UsageKind_Normal,
REGS_UsageKind_Normal, REGS_UsageKind_Normal,
REGS_UsageKind_Normal, REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
}; };
REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[95] = REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[95] =
@@ -292,7 +290,7 @@ REGS_UsageKind_Vector,
REGS_UsageKind_Vector, REGS_UsageKind_Vector,
}; };
String8 regs_g_reg_code_x64_string_table[95] = String8 regs_g_reg_code_x64_string_table[93] =
{ {
str8_lit_comp(""), str8_lit_comp(""),
str8_lit_comp("rax"), str8_lit_comp("rax"),
@@ -387,8 +385,6 @@ str8_lit_comp("k6"),
str8_lit_comp("k7"), str8_lit_comp("k7"),
str8_lit_comp("cetmsr"), str8_lit_comp("cetmsr"),
str8_lit_comp("cetssp"), str8_lit_comp("cetssp"),
str8_lit_comp("tr"),
str8_lit_comp("ldtr"),
}; };
String8 regs_g_alias_code_x64_string_table[95] = String8 regs_g_alias_code_x64_string_table[95] =
@@ -490,7 +486,7 @@ str8_lit_comp("mm6"),
str8_lit_comp("mm7"), str8_lit_comp("mm7"),
}; };
REGS_Rng regs_g_reg_code_x64_rng_table[95] = REGS_Rng regs_g_reg_code_x64_rng_table[93] =
{ {
{0}, {0},
{(U16)OffsetOf(REGS_RegBlockX64, rax), 8}, {(U16)OffsetOf(REGS_RegBlockX64, rax), 8},
@@ -585,8 +581,6 @@ REGS_Rng regs_g_reg_code_x64_rng_table[95] =
{(U16)OffsetOf(REGS_RegBlockX64, k7), 8}, {(U16)OffsetOf(REGS_RegBlockX64, k7), 8},
{(U16)OffsetOf(REGS_RegBlockX64, cetmsr), 8}, {(U16)OffsetOf(REGS_RegBlockX64, cetmsr), 8},
{(U16)OffsetOf(REGS_RegBlockX64, cetssp), 8}, {(U16)OffsetOf(REGS_RegBlockX64, cetssp), 8},
{(U16)OffsetOf(REGS_RegBlockX64, tr), 2},
{(U16)OffsetOf(REGS_RegBlockX64, ldtr), 2},
}; };
REGS_Slice regs_g_alias_code_x64_slice_table[95] = REGS_Slice regs_g_alias_code_x64_slice_table[95] =
src/regs/generated/regs.meta.h
+3 -7
View File
@@ -101,8 +101,6 @@ REGS_RegCodeX64_k6,
REGS_RegCodeX64_k7, REGS_RegCodeX64_k7,
REGS_RegCodeX64_cetmsr, REGS_RegCodeX64_cetmsr,
REGS_RegCodeX64_cetssp, REGS_RegCodeX64_cetssp,
REGS_RegCodeX64_tr,
REGS_RegCodeX64_ldtr,
REGS_RegCodeX64_COUNT, REGS_RegCodeX64_COUNT,
} REGS_RegCodeX64; } REGS_RegCodeX64;
@@ -301,16 +299,14 @@ REGS_Reg64 k6;
REGS_Reg64 k7; REGS_Reg64 k7;
REGS_Reg64 cetmsr; REGS_Reg64 cetmsr;
REGS_Reg64 cetssp; REGS_Reg64 cetssp;
REGS_Reg16 tr;
REGS_Reg16 ldtr;
}; };
C_LINKAGE_BEGIN C_LINKAGE_BEGIN
extern REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[95]; extern REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[93];
extern REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[95]; extern REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[95];
extern String8 regs_g_reg_code_x64_string_table[95]; extern String8 regs_g_reg_code_x64_string_table[93];
extern String8 regs_g_alias_code_x64_string_table[95]; extern String8 regs_g_alias_code_x64_string_table[95];
extern REGS_Rng regs_g_reg_code_x64_rng_table[95]; extern REGS_Rng regs_g_reg_code_x64_rng_table[93];
extern REGS_Slice regs_g_alias_code_x64_slice_table[95]; extern REGS_Slice regs_g_alias_code_x64_slice_table[95];
C_LINKAGE_END C_LINKAGE_END
src/regs/rdi/generated/regs_rdi.meta.c
-4
View File
@@ -106,8 +106,6 @@ case REGS_RegCodeX64_k6:{result = RDI_RegCodeX64_k6;}break;
case REGS_RegCodeX64_k7:{result = RDI_RegCodeX64_k7;}break; case REGS_RegCodeX64_k7:{result = RDI_RegCodeX64_k7;}break;
case REGS_RegCodeX64_cetmsr:{result = RDI_RegCodeX64_cetmsr;}break; case REGS_RegCodeX64_cetmsr:{result = RDI_RegCodeX64_cetmsr;}break;
case REGS_RegCodeX64_cetssp:{result = RDI_RegCodeX64_cetssp;}break; case REGS_RegCodeX64_cetssp:{result = RDI_RegCodeX64_cetssp;}break;
case REGS_RegCodeX64_tr:{result = RDI_RegCodeX64_tr;}break;
case REGS_RegCodeX64_ldtr:{result = RDI_RegCodeX64_ldtr;}break;
} }
}break; }break;
case Arch_x86: case Arch_x86:
@@ -220,8 +218,6 @@ case RDI_RegCodeX64_k6:{result = REGS_RegCodeX64_k6;}break;
case RDI_RegCodeX64_k7:{result = REGS_RegCodeX64_k7;}break; case RDI_RegCodeX64_k7:{result = REGS_RegCodeX64_k7;}break;
case RDI_RegCodeX64_cetmsr:{result = REGS_RegCodeX64_cetmsr;}break; case RDI_RegCodeX64_cetmsr:{result = REGS_RegCodeX64_cetmsr;}break;
case RDI_RegCodeX64_cetssp:{result = REGS_RegCodeX64_cetssp;}break; case RDI_RegCodeX64_cetssp:{result = REGS_RegCodeX64_cetssp;}break;
case RDI_RegCodeX64_tr:{result = REGS_RegCodeX64_tr;}break;
case RDI_RegCodeX64_ldtr:{result = REGS_RegCodeX64_ldtr;}break;
} }
}break; }break;
case Arch_x86: case Arch_x86:
src/regs/regs.mdesk
-2
View File
@@ -99,8 +99,6 @@ REGS_RegTableX64:
{k7 64 Normal} {k7 64 Normal}
{cetmsr 64 Normal} {cetmsr 64 Normal}
{cetssp 64 Normal} {cetssp 64 Normal}
{tr 16 Normal}
{ldtr 16 Normal}
} }
@table(name base off size usage) @table(name base off size usage)