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remove x86 register code

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This commit is contained in:
Nikita Smith
2025-12-05 16:39:02 -08:00
parent ce77442d37
commit 8005c31276
23 changed files with 31 additions and 1625 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/codeview/codeview.c
-41
View File
@@ -47,7 +47,6 @@ cv_size_from_reg(CV_Arch arch, CV_Reg reg)
{
switch(arch)
{
case CV_Arch_8086: return cv_size_from_reg_x86(reg);
case CV_Arch_X64 : return cv_size_from_reg_x64(reg);
default: NotImplemented;
}
@@ -59,25 +58,12 @@ cv_is_reg_sp(CV_Arch arch, CV_Reg reg)
{
switch(arch)
{
case CV_Arch_8086: return reg == CV_Regx86_ESP;
case CV_Arch_X64: return reg == CV_Regx64_RSP;
default: NotImplemented;
}
return 0;
}
internal U64
cv_size_from_reg_x86(CV_Reg reg)
{
switch(reg)
{
#define X(NAME, CODE, RDI_NAME, BYTE_POS, BYTE_SIZE) case CV_Regx86_##NAME: return BYTE_SIZE;
CV_Reg_X86_XList(X)
#undef X
}
return 0;
}
internal U64
cv_size_from_reg_x64(CV_Reg reg)
{
@@ -111,18 +97,6 @@ cv_decode_fp_reg(CV_Arch arch, CV_EncodedFramePtrReg encoded_reg)
CV_Reg fp_reg = 0;
switch (arch)
{
case CV_Arch_8086:
{
switch (encoded_reg)
{
case CV_EncodedFramePtrReg_None : break;
case CV_EncodedFramePtrReg_StackPtr: AssertAlways(!"TODO: not tested, this is a guess");
fp_reg = CV_Regx86_ESP; break;
case CV_EncodedFramePtrReg_FramePtr: fp_reg = CV_Regx86_EBP; break;
case CV_EncodedFramePtrReg_BasePtr : fp_reg = CV_Regx86_EBX; break;
default: InvalidPath;
}
} break;
case CV_Arch_X64:
{
switch (encoded_reg)
@@ -144,14 +118,6 @@ cv_map_encoded_base_pointer(CV_Arch arch, U32 encoded_frame_reg)
{
U32 r = 0;
switch (arch) {
case CV_Arch_8086: {
switch (encoded_frame_reg) {
case 0: r = 0; break;
case 1: r = CV_AllReg_VFRAME; break;
case 2: r = CV_Regx86_EBP; break;
case 3: r = CV_Regx86_EBX; break;
}
} break;
case CV_Arch_X64: {
switch (encoded_frame_reg) {
case 0: r = 0; break;
@@ -207,13 +173,6 @@ cv_string_from_reg_id(Arena *arena, CV_Arch arch, U32 id)
{
String8 result = str8_zero();
switch (arch) {
case CV_Arch_8086: {
switch (id) {
#define X(_N, _ID, ...) case _ID: result = str8_lit(Stringify(_N)); break;
CV_Reg_X86_XList(X)
#undef X
}
} break;
case CV_Arch_X64: {
switch (id) {
#define X(_N, _ID, ...) case _ID: result = str8_lit(Stringify(_N)); break;
src/codeview/codeview.h
-256
View File
@@ -41,261 +41,6 @@ read_only global CV_TypeId cv_type_id_variadic = 0xFFFFFFFF;
////////////////////////////////
//~ rjf: Registers
// X(NAME, CODE, (RDI_RegCode_X86) NAME, BYTE_POS, BYTE_SIZE)
#define CV_Reg_X86_XList(X) \
X(NONE, 0, nil, 0, 0) \
X(AL, 1, eax, 0, 1) \
X(CL, 2, ecx, 0, 1) \
X(DL, 3, edx, 0, 1) \
X(BL, 4, ebx, 0, 1) \
X(AH, 5, eax, 1, 1) \
X(CH, 6, ecx, 1, 1) \
X(DH, 7, edx, 1, 1) \
X(BH, 8, ebx, 1, 1) \
X(AX, 9, eax, 0, 2) \
X(CX, 10, ecx, 0, 2) \
X(DX, 11, edx, 0, 2) \
X(BX, 12, ebx, 0, 2) \
X(SP, 13, esp, 0, 2) \
X(BP, 14, ebp, 0, 2) \
X(SI, 15, esi, 0, 2) \
X(DI, 16, edi, 0, 2) \
X(EAX, 17, eax, 0, 4) \
X(ECX, 18, ecx, 0, 4) \
X(EDX, 19, edx, 0, 4) \
X(EBX, 20, ebx, 0, 4) \
X(ESP, 21, esp, 0, 4) \
X(EBP, 22, ebp, 0, 4) \
X(ESI, 23, esi, 0, 4) \
X(EDI, 24, edi, 0, 4) \
X(ES, 25, es, 0, 2) \
X(CS, 26, cs, 0, 2) \
X(SS, 27, ss, 0, 2) \
X(DS, 28, ds, 0, 2) \
X(FS, 29, fs, 0, 2) \
X(GS, 30, gs, 0, 2) \
X(IP, 31, eip, 0, 2) \
X(FLAGS, 32, eflags, 0, 2) \
X(EIP, 33, eip, 0, 4) \
X(EFLAGS, 34, eflags, 0, 4) \
X(MM0, 146, st0, 0, 8) \
X(MM1, 147, st1, 0, 8) \
X(MM2, 148, st2, 0, 8) \
X(MM3, 149, st3, 0, 8) \
X(MM4, 150, st4, 0, 8) \
X(MM5, 151, st5, 0, 8) \
X(MM6, 152, st6, 0, 8) \
X(MM7, 153, st7, 0, 8) \
X(XMM0, 154, ymm0, 0, 16) \
X(XMM1, 155, ymm1, 0, 16) \
X(XMM2, 156, ymm2, 0, 16) \
X(XMM3, 157, ymm3, 0, 16) \
X(XMM4, 158, ymm4, 0, 16) \
X(XMM5, 159, ymm5, 0, 16) \
X(XMM6, 160, ymm6, 0, 16) \
X(XMM7, 161, ymm7, 0, 16) \
X(XMM00, 162, ymm0, 0, 4) \
X(XMM01, 163, ymm0, 4, 4) \
X(XMM02, 164, ymm0, 8, 4) \
X(XMM03, 165, ymm0, 12, 4) \
X(XMM10, 166, ymm1, 0, 4) \
X(XMM11, 167, ymm1, 4, 4) \
X(XMM12, 168, ymm1, 8, 4) \
X(XMM13, 169, ymm1, 12, 4) \
X(XMM20, 170, ymm2, 0, 4) \
X(XMM21, 171, ymm2, 4, 4) \
X(XMM22, 172, ymm2, 8, 4) \
X(XMM23, 173, ymm2, 12, 4) \
X(XMM30, 174, ymm3, 0, 4) \
X(XMM31, 175, ymm3, 4, 4) \
X(XMM32, 176, ymm3, 8, 4) \
X(XMM33, 177, ymm3, 12, 4) \
X(XMM40, 178, ymm4, 0, 4) \
X(XMM41, 179, ymm4, 4, 4) \
X(XMM42, 180, ymm4, 8, 4) \
X(XMM43, 181, ymm4, 12, 4) \
X(XMM50, 182, ymm5, 0, 4) \
X(XMM51, 183, ymm5, 4, 4) \
X(XMM52, 184, ymm5, 8, 4) \
X(XMM53, 185, ymm5, 12, 4) \
X(XMM60, 186, ymm6, 0, 4) \
X(XMM61, 187, ymm6, 4, 4) \
X(XMM62, 188, ymm6, 8, 4) \
X(XMM63, 189, ymm6, 12, 4) \
X(XMM70, 190, ymm7, 0, 4) \
X(XMM71, 191, ymm7, 4, 4) \
X(XMM72, 192, ymm7, 8, 4) \
X(XMM73, 193, ymm7, 12, 4) \
X(XMM0L, 194, ymm0, 0, 8) \
X(XMM1L, 195, ymm1, 0, 8) \
X(XMM2L, 196, ymm2, 0, 8) \
X(XMM3L, 197, ymm3, 0, 8) \
X(XMM4L, 198, ymm4, 0, 8) \
X(XMM5L, 199, ymm5, 0, 8) \
X(XMM6L, 200, ymm6, 0, 8) \
X(XMM7L, 201, ymm7, 0, 8) \
X(XMM0H, 202, ymm0, 8, 8) \
X(XMM1H, 203, ymm1, 8, 8) \
X(XMM2H, 204, ymm2, 8, 8) \
X(XMM3H, 205, ymm3, 8, 8) \
X(XMM4H, 206, ymm4, 8, 8) \
X(XMM5H, 207, ymm5, 8, 8) \
X(XMM6H, 208, ymm6, 8, 8) \
X(XMM7H, 209, ymm7, 8, 8) \
X(YMM0, 252, ymm0, 0, 32) \
X(YMM1, 253, ymm1, 0, 32) \
X(YMM2, 254, ymm2, 0, 32) \
X(YMM3, 255, ymm3, 0, 32) \
X(YMM4, 256, ymm4, 0, 32) \
X(YMM5, 257, ymm5, 0, 32) \
X(YMM6, 258, ymm6, 0, 32) \
X(YMM7, 259, ymm7, 0, 32) \
X(YMM0H, 260, ymm0, 16, 16) \
X(YMM1H, 261, ymm1, 16, 16) \
X(YMM2H, 262, ymm2, 16, 16) \
X(YMM3H, 263, ymm3, 16, 16) \
X(YMM4H, 264, ymm4, 16, 16) \
X(YMM5H, 265, ymm5, 16, 16) \
X(YMM6H, 266, ymm6, 16, 16) \
X(YMM7H, 267, ymm7, 16, 16) \
X(YMM0I0, 268, ymm0, 0, 8) \
X(YMM0I1, 269, ymm0, 8, 8) \
X(YMM0I2, 270, ymm0, 16, 8) \
X(YMM0I3, 271, ymm0, 24, 8) \
X(YMM1I0, 272, ymm1, 0, 8) \
X(YMM1I1, 273, ymm1, 8, 8) \
X(YMM1I2, 274, ymm1, 16, 8) \
X(YMM1I3, 275, ymm1, 24, 8) \
X(YMM2I0, 276, ymm2, 0, 8) \
X(YMM2I1, 277, ymm2, 8, 8) \
X(YMM2I2, 278, ymm2, 16, 8) \
X(YMM2I3, 279, ymm2, 24, 8) \
X(YMM3I0, 280, ymm3, 0, 8) \
X(YMM3I1, 281, ymm3, 8, 8) \
X(YMM3I2, 282, ymm3, 16, 8) \
X(YMM3I3, 283, ymm3, 24, 8) \
X(YMM4I0, 284, ymm4, 0, 8) \
X(YMM4I1, 285, ymm4, 8, 8) \
X(YMM4I2, 286, ymm4, 16, 8) \
X(YMM4I3, 287, ymm4, 24, 8) \
X(YMM5I0, 288, ymm5, 0, 8) \
X(YMM5I1, 289, ymm5, 8, 8) \
X(YMM5I2, 290, ymm5, 16, 8) \
X(YMM5I3, 291, ymm5, 24, 8) \
X(YMM6I0, 292, ymm6, 0, 8) \
X(YMM6I1, 293, ymm6, 8, 8) \
X(YMM6I2, 294, ymm6, 16, 8) \
X(YMM6I3, 295, ymm6, 24, 8) \
X(YMM7I0, 296, ymm7, 0, 8) \
X(YMM7I1, 297, ymm7, 8, 8) \
X(YMM7I2, 298, ymm7, 16, 8) \
X(YMM7I3, 299, ymm7, 24, 8) \
X(YMM0F0, 300, ymm0, 0, 4) \
X(YMM0F1, 301, ymm0, 4, 4) \
X(YMM0F2, 302, ymm0, 8, 4) \
X(YMM0F3, 303, ymm0, 12, 4) \
X(YMM0F4, 304, ymm0, 16, 4) \
X(YMM0F5, 305, ymm0, 20, 4) \
X(YMM0F6, 306, ymm0, 24, 4) \
X(YMM0F7, 307, ymm0, 28, 4) \
X(YMM1F0, 308, ymm1, 0, 4) \
X(YMM1F1, 309, ymm1, 4, 4) \
X(YMM1F2, 310, ymm1, 8, 4) \
X(YMM1F3, 311, ymm1, 12, 4) \
X(YMM1F4, 312, ymm1, 16, 4) \
X(YMM1F5, 313, ymm1, 20, 4) \
X(YMM1F6, 314, ymm1, 24, 4) \
X(YMM1F7, 315, ymm1, 28, 4) \
X(YMM2F0, 316, ymm2, 0, 4) \
X(YMM2F1, 317, ymm2, 4, 4) \
X(YMM2F2, 318, ymm2, 8, 4) \
X(YMM2F3, 319, ymm2, 12, 4) \
X(YMM2F4, 320, ymm2, 16, 4) \
X(YMM2F5, 321, ymm2, 20, 4) \
X(YMM2F6, 322, ymm2, 24, 4) \
X(YMM2F7, 323, ymm2, 28, 4) \
X(YMM3F0, 324, ymm3, 0, 4) \
X(YMM3F1, 325, ymm3, 4, 4) \
X(YMM3F2, 326, ymm3, 8, 4) \
X(YMM3F3, 327, ymm3, 12, 4) \
X(YMM3F4, 328, ymm3, 16, 4) \
X(YMM3F5, 329, ymm3, 20, 4) \
X(YMM3F6, 330, ymm3, 24, 4) \
X(YMM3F7, 331, ymm3, 28, 4) \
X(YMM4F0, 332, ymm4, 0, 4) \
X(YMM4F1, 333, ymm4, 4, 4) \
X(YMM4F2, 334, ymm4, 8, 4) \
X(YMM4F3, 335, ymm4, 12, 4) \
X(YMM4F4, 336, ymm4, 16, 4) \
X(YMM4F5, 337, ymm4, 20, 4) \
X(YMM4F6, 338, ymm4, 24, 4) \
X(YMM4F7, 339, ymm4, 28, 4) \
X(YMM5F0, 340, ymm5, 0, 4) \
X(YMM5F1, 341, ymm5, 4, 4) \
X(YMM5F2, 342, ymm5, 8, 4) \
X(YMM5F3, 343, ymm5, 12, 4) \
X(YMM5F4, 344, ymm5, 16, 4) \
X(YMM5F5, 345, ymm5, 20, 4) \
X(YMM5F6, 346, ymm5, 24, 4) \
X(YMM5F7, 347, ymm5, 28, 4) \
X(YMM6F0, 348, ymm6, 0, 4) \
X(YMM6F1, 349, ymm6, 4, 4) \
X(YMM6F2, 350, ymm6, 8, 4) \
X(YMM6F3, 351, ymm6, 12, 4) \
X(YMM6F4, 352, ymm6, 16, 4) \
X(YMM6F5, 353, ymm6, 20, 4) \
X(YMM6F6, 354, ymm6, 24, 4) \
X(YMM6F7, 355, ymm6, 28, 4) \
X(YMM7F0, 356, ymm7, 0, 4) \
X(YMM7F1, 357, ymm7, 4, 4) \
X(YMM7F2, 358, ymm7, 8, 4) \
X(YMM7F3, 359, ymm7, 12, 4) \
X(YMM7F4, 360, ymm7, 16, 4) \
X(YMM7F5, 361, ymm7, 20, 4) \
X(YMM7F6, 362, ymm7, 24, 4) \
X(YMM7F7, 363, ymm7, 28, 4) \
X(YMM0D0, 364, ymm0, 0, 8) \
X(YMM0D1, 365, ymm0, 8, 8) \
X(YMM0D2, 366, ymm0, 16, 8) \
X(YMM0D3, 367, ymm0, 24, 8) \
X(YMM1D0, 368, ymm1, 0, 8) \
X(YMM1D1, 369, ymm1, 8, 8) \
X(YMM1D2, 370, ymm1, 16, 8) \
X(YMM1D3, 371, ymm1, 24, 8) \
X(YMM2D0, 372, ymm2, 0, 8) \
X(YMM2D1, 373, ymm2, 8, 8) \
X(YMM2D2, 374, ymm2, 16, 8) \
X(YMM2D3, 375, ymm2, 24, 8) \
X(YMM3D0, 376, ymm3, 0, 8) \
X(YMM3D1, 377, ymm3, 8, 8) \
X(YMM3D2, 378, ymm3, 16, 8) \
X(YMM3D3, 379, ymm3, 24, 8) \
X(YMM4D0, 380, ymm4, 0, 8) \
X(YMM4D1, 381, ymm4, 8, 8) \
X(YMM4D2, 382, ymm4, 16, 8) \
X(YMM4D3, 383, ymm4, 24, 8) \
X(YMM5D0, 384, ymm5, 0, 8) \
X(YMM5D1, 385, ymm5, 8, 8) \
X(YMM5D2, 386, ymm5, 16, 8) \
X(YMM5D3, 387, ymm5, 24, 8) \
X(YMM6D0, 388, ymm6, 0, 8) \
X(YMM6D1, 389, ymm6, 8, 8) \
X(YMM6D2, 390, ymm6, 16, 8) \
X(YMM6D3, 391, ymm6, 24, 8) \
X(YMM7D0, 392, ymm7, 0, 8) \
X(YMM7D1, 393, ymm7, 8, 8) \
X(YMM7D2, 394, ymm7, 16, 8) \
X(YMM7D3, 395, ymm7, 24, 8)
typedef U16 CV_Regx86;
typedef enum CV_Regx86Enum
{
#define X(CVN,C,RDN,BP,BZ) CV_Regx86_##CVN = C,
CV_Reg_X86_XList(X)
#undef X
}
CV_Regx86Enum;
// X(NAME, CODE, (RDI_RegisterCode_X64) NAME, BYTE_POS, BYTE_SIZE)
#define CV_Reg_X64_XList(X) \
X(NONE, 0, nil, 0, 0) \
@@ -2963,7 +2708,6 @@ struct CV_TypeIndexArray
////////////////////////////////
internal CV_Arch cv_arch_from_coff_machine(COFF_MachineType machine);
internal U64 cv_size_from_reg_x86(CV_Reg reg);
internal U64 cv_size_from_reg_x64(CV_Reg reg);
internal U64 cv_size_from_reg(CV_Arch arch, CV_Reg reg);
internal B32 cv_is_reg_sp(CV_Arch arch, CV_Reg reg);
src/demon/win32/demon_core_win32.c
+6 -177
View File
@@ -597,90 +597,8 @@ dmn_w32_thread_read_reg_block(Arch arch, HANDLE thread, void *reg_block)
{}break;
case Arch_arm64:
case Arch_arm32:
{NotImplemented;}break;
////////////////////////////
//- rjf: x86
//
case Arch_x86:
{
REGS_RegBlockX86 *dst = (REGS_RegBlockX86 *)reg_block;
//- rjf: get thread context
WOW64_CONTEXT ctx = {0};
ctx.ContextFlags = DMN_W32_CTX_X86_ALL;
if(!Wow64GetThreadContext(thread, (WOW64_CONTEXT *)&ctx))
{
break;
}
result = 1;
//- rjf: convert WOW64_CONTEXT -> REGS_RegBlockX86
XSAVE_FORMAT *fxsave = (XSAVE_FORMAT *)ctx.ExtendedRegisters;
dst->eax.u32 = ctx.Eax;
dst->ebx.u32 = ctx.Ebx;
dst->ecx.u32 = ctx.Ecx;
dst->edx.u32 = ctx.Edx;
dst->esi.u32 = ctx.Esi;
dst->edi.u32 = ctx.Edi;
dst->esp.u32 = ctx.Esp;
dst->ebp.u32 = ctx.Ebp;
dst->eip.u32 = ctx.Eip;
dst->cs.u16 = ctx.SegCs;
dst->ds.u16 = ctx.SegDs;
dst->es.u16 = ctx.SegEs;
dst->fs.u16 = ctx.SegFs;
dst->gs.u16 = ctx.SegGs;
dst->ss.u16 = ctx.SegSs;
dst->dr0.u32 = ctx.Dr0;
dst->dr1.u32 = ctx.Dr1;
dst->dr2.u32 = ctx.Dr2;
dst->dr3.u32 = ctx.Dr3;
dst->dr6.u32 = ctx.Dr6;
dst->dr7.u32 = ctx.Dr7;
// NOTE(rjf): this bit is "supposed to always be 1", according to old info.
// may need to be investigated.
dst->eflags.u32 = ctx.EFlags | 0x2;
dst->fcw.u16 = fxsave->ControlWord;
dst->fsw.u16 = fxsave->StatusWord;
dst->ftw.u16 = fxsave->TagWord;
dst->fop.u16 = fxsave->ErrorOpcode;
dst->fip.u32 = fxsave->ErrorOffset;
dst->fcs.u16 = fxsave->ErrorSelector;
dst->fdp.u32 = fxsave->DataOffset;
dst->fds.u16 = fxsave->DataSelector;
dst->mxcsr.u32 = fxsave->MxCsr;
dst->mxcsr_mask.u32 = fxsave->MxCsr_Mask;
{
M128A *float_s = fxsave->FloatRegisters;
REGS_Reg80 *float_d = &dst->st0;
for(U32 n = 0; n < 8; n += 1, float_s += 1, float_d += 1)
{
MemoryCopy(float_d, float_s, sizeof(*float_d));
}
}
{
M128A *xmm_s = fxsave->XmmRegisters;
REGS_Reg256 *xmm_d = &dst->ymm0;
for(U32 n = 0; n < 8; n += 1, xmm_s += 1, xmm_d += 1)
{
MemoryCopy(xmm_d, xmm_s, sizeof(*xmm_s));
}
}
//- rjf: read FS/GS base
WOW64_LDT_ENTRY ldt = {0};
if(Wow64GetThreadSelectorEntry(thread, ctx.SegFs, &ldt))
{
U32 base = (ldt.BaseLow) | (ldt.HighWord.Bytes.BaseMid << 16) | (ldt.HighWord.Bytes.BaseHi << 24);
dst->fsbase.u32 = base;
}
if(Wow64GetThreadSelectorEntry(thread, ctx.SegGs, &ldt))
{
U32 base = (ldt.BaseLow) | (ldt.HighWord.Bytes.BaseMid << 16) | (ldt.HighWord.Bytes.BaseHi << 24);
dst->gsbase.u32 = base;
}
}break;
{NotImplemented;}break;
////////////////////////////
//- rjf: x64
@@ -901,75 +819,8 @@ dmn_w32_thread_write_reg_block(Arch arch, HANDLE thread, void *reg_block)
{}break;
case Arch_arm64:
case Arch_arm32:
{NotImplemented;}break;
////////////////////////////
//- rjf: x86
//
case Arch_x86:
{
REGS_RegBlockX86 *src = (REGS_RegBlockX86 *)reg_block;
//- rjf: convert REGS_RegBlockX86 -> WOW64_CONTEXT
WOW64_CONTEXT ctx = {0};
XSAVE_FORMAT *fxsave = (XSAVE_FORMAT*)ctx.ExtendedRegisters;
ctx.ContextFlags = DMN_W32_CTX_X86_ALL;
ctx.Eax = src->eax.u32;
ctx.Ebx = src->ebx.u32;
ctx.Ecx = src->ecx.u32;
ctx.Edx = src->edx.u32;
ctx.Esi = src->esi.u32;
ctx.Edi = src->edi.u32;
ctx.Esp = src->esp.u32;
ctx.Ebp = src->ebp.u32;
ctx.Eip = src->eip.u32;
ctx.SegCs = src->cs.u16;
ctx.SegDs = src->ds.u16;
ctx.SegEs = src->es.u16;
ctx.SegFs = src->fs.u16;
ctx.SegGs = src->gs.u16;
ctx.SegSs = src->ss.u16;
ctx.Dr0 = src->dr0.u32;
ctx.Dr1 = src->dr1.u32;
ctx.Dr2 = src->dr2.u32;
ctx.Dr3 = src->dr3.u32;
ctx.Dr6 = src->dr6.u32;
ctx.Dr7 = src->dr7.u32;
ctx.EFlags = src->eflags.u32;
fxsave->ControlWord = src->fcw.u16;
fxsave->StatusWord = src->fsw.u16;
fxsave->TagWord = src->ftw.u16;
fxsave->ErrorOpcode = src->fop.u16;
fxsave->ErrorSelector = src->fcs.u16;
fxsave->DataSelector = src->fds.u16;
fxsave->ErrorOffset = src->fip.u32;
fxsave->DataOffset = src->fdp.u32;
fxsave->MxCsr = src->mxcsr.u32 & src->mxcsr_mask.u32;
fxsave->MxCsr_Mask = src->mxcsr_mask.u32;
{
M128A *float_d = fxsave->FloatRegisters;
REGS_Reg80 *float_s = &src->st0;
for(U32 n = 0; n < 8; n += 1, float_s += 1, float_d += 1)
{
MemoryCopy(float_d, float_s, 10);
}
}
{
M128A *xmm_d = fxsave->XmmRegisters;
REGS_Reg256 *xmm_s = &src->ymm0;
for(U32 n = 0; n < 8; n += 1, xmm_d += 1, xmm_s += 1)
{
MemoryCopy(xmm_d, xmm_s, sizeof(*xmm_d));
}
}
//- rjf: set thread context
B32 result = 0;
if(Wow64SetThreadContext(thread, &ctx))
{
result = 1;
}
}break;
{NotImplemented;}break;
////////////////////////////
//- rjf: x64
@@ -1528,16 +1379,8 @@ dmn_ctrl_run(Arena *arena, DMN_CtrlCtx *ctx, DMN_RunCtrls *ctrls)
{}break;
case Arch_arm64:
case Arch_arm32:
{NotImplemented;}break;
//- rjf: x86
case Arch_x86:
{
REGS_RegBlockX86 regs = {0};
dmn_thread_read_reg_block(ctrls->single_step_thread, &regs);
regs.eflags.u32 |= 0x100;
dmn_thread_write_reg_block(ctrls->single_step_thread, &regs);
}break;
{NotImplemented;}break;
//- rjf: x64
case Arch_x64:
@@ -2867,16 +2710,9 @@ dmn_ctrl_run(Arena *arena, DMN_CtrlCtx *ctx, DMN_RunCtrls *ctrls)
{}break;
case Arch_arm64:
case Arch_arm32:
case Arch_x86:
{NotImplemented;}break;
//- rjf: x86/64
case Arch_x86:
{
REGS_RegBlockX86 regs = {0};
dmn_thread_read_reg_block(ctrls->single_step_thread, &regs);
regs.eflags.u32 &= ~0x100;
dmn_thread_write_reg_block(ctrls->single_step_thread, &regs);
}break;
case Arch_x64:
{
if(!GetThreadContext(thread->handle, single_step_thread_ctx))
@@ -3137,17 +2973,13 @@ dmn_stack_base_vaddr_from_thread(DMN_Handle handle)
{}break;
case Arch_arm64:
case Arch_arm32:
case Arch_x86:
{NotImplemented;}break;
case Arch_x64:
{
U64 stack_base_addr = tlb + 0x8;
dmn_w32_process_read(process->handle, r1u64(stack_base_addr, stack_base_addr+8), &result);
}break;
case Arch_x86:
{
U64 stack_base_addr = tlb + 0x4;
dmn_w32_process_read(process->handle, r1u64(stack_base_addr, stack_base_addr+4), &result);
}break;
}
}
}
@@ -3171,15 +3003,12 @@ dmn_tls_root_vaddr_from_thread(DMN_Handle handle)
{}break;
case Arch_arm64:
case Arch_arm32:
case Arch_x86:
{NotImplemented;}break;
case Arch_x64:
{
result += 88;
}break;
case Arch_x86:
{
result += 44;
}break;
}
}
}
src/dwarf/dwarf.c
+1 -33
View File
@@ -1,28 +1,6 @@
// Copyright (c) Epic Games Tools
// Licensed under the MIT license (https://opensource.org/license/mit/)
internal U64
dw_reg_size_from_code_x86(DW_Reg reg_code)
{
switch (reg_code) {
#define X(reg_name_dw, reg_code_dw, reg_name_rdi, reg_pos, reg_size) case DW_RegX86_##reg_name_dw: return reg_size;
DW_Regs_X86_XList(X)
#undef X
}
return 0;
}
internal U64
dw_reg_pos_from_code_x86(DW_Reg reg_code)
{
switch (reg_code) {
#define X(reg_name_dw, reg_code_dw, reg_name_rdi, reg_pos, reg_size) case DW_RegX86_##reg_name_dw: return reg_pos;
DW_Regs_X86_XList(X)
#undef X
}
return max_U64;
}
internal U64
dw_reg_size_from_code_x64(DW_Reg reg_code)
{
@@ -50,7 +28,6 @@ dw_reg_size_from_code(Arch arch, DW_Reg reg_code)
{
switch (arch) {
case Arch_Null: break;
case Arch_x86: return dw_reg_size_from_code_x86(reg_code);
case Arch_x64: return dw_reg_size_from_code_x64(reg_code);
default: NotImplemented; break;
}
@@ -62,7 +39,6 @@ dw_reg_pos_from_code(Arch arch, DW_Reg reg_code)
{
switch (arch) {
case Arch_Null: break;
case Arch_x86: return dw_reg_pos_from_code_x86(reg_code);
case Arch_x64: return dw_reg_pos_from_code_x64(reg_code);
default: NotImplemented; break;
}
@@ -75,7 +51,6 @@ dw_reg_count_from_arch(Arch arch)
switch (arch) {
default: { NotImplemented; } // fall-through
case Arch_Null: return 0;
case Arch_x86: return DW_RegX86_Last;
case Arch_x64: return DW_RegX64_Last;
}
}
@@ -100,7 +75,6 @@ dw_sp_from_arch(Arch arch)
switch (arch) {
default: NotImplemented;
case Arch_Null: return 0;
case Arch_x86: return DW_RegX86_Esp;
case Arch_x64: return DW_RegX64_Rsp;
}
}
@@ -793,13 +767,6 @@ dw_string_from_register(Arena *arena, Arch arch, U64 reg_id)
String8 reg_str = str8_zero();
switch (arch) {
case Arch_Null: break;
case Arch_x86: {
switch (reg_id) {
#define X(_N, _ID, ...) case DW_RegX86_##_N: reg_str = str8_lit(Stringify(_N)); break;
DW_Regs_X86_XList(X)
#undef X
}
} break;
case Arch_x64: {
switch (reg_id) {
#define X(_N, _ID, ...) case DW_RegX64_##_N: reg_str = str8_lit(Stringify(_N)); break;
@@ -809,6 +776,7 @@ dw_string_from_register(Arena *arena, Arch arch, U64 reg_id)
} break;
case Arch_arm32: NotImplemented; break;
case Arch_arm64: NotImplemented; break;
case Arch_x86: NotImplemented; break;
default: InvalidPath; break;
}
if (reg_str.size == 0) {
src/dwarf/dwarf.h
-59
View File
@@ -1590,54 +1590,6 @@ typedef enum DW_ExprOpEnum
//- Regs
#define DW_Regs_X86_XList(X) \
X(Eax, 0, eax, 0, 4) \
X(Ecx, 1, ecx, 0, 4) \
X(Edx, 2, edx, 0, 4) \
X(Ebx, 3, ebx, 0, 4) \
X(Esp, 4, esp, 0, 4) \
X(Ebp, 5, ebp, 0, 4) \
X(Esi, 6, esi, 0, 4) \
X(Edi, 7, edi, 0, 4) \
X(Eip, 8, eip, 0, 4) \
X(Eflags, 9, eflags, 0, 4) \
X(Trapno, 10, nil, 0, 0) \
X(St0, 11, st0, 0, 10) \
X(St1, 12, st1, 0, 10) \
X(St2, 13, st2, 0, 10) \
X(St3, 14, st3, 0, 10) \
X(St4, 15, st4, 0, 10) \
X(St5, 16, st5, 0, 10) \
X(St6, 17, st6, 0, 10) \
X(St7, 18, st7, 0, 10) \
X(Xmm0, 21, ymm0, 0, 16) \
X(Xmm1, 22, ymm1, 0, 16) \
X(Xmm2, 23, ymm2, 0, 16) \
X(Xmm3, 24, ymm3, 0, 16) \
X(Xmm4, 25, ymm4, 0, 16) \
X(Xmm5, 26, ymm5, 0, 16) \
X(Xmm6, 27, ymm6, 0, 16) \
X(Xmm7, 28, ymm7, 0, 16) \
X(Mm0, 29, st0, 0, 8) \
X(Mm1, 30, st1, 0, 8) \
X(Mm2, 31, st2, 0, 8) \
X(Mm3, 32, st3, 0, 8) \
X(Mm4, 33, st4, 0, 8) \
X(Mm5, 34, st5, 0, 8) \
X(Mm6, 35, st6, 0, 8) \
X(Mm7, 36, st7, 0, 8) \
X(Fcw, 37, fcw, 0, 2) \
X(Fsw, 38, fsw, 0, 2) \
X(Mxcsr, 39, mxcsr, 0, 4) \
X(Es, 40, es, 0, 2) \
X(Cs, 41, cs, 0, 2) \
X(Ss, 42, ss, 0, 2) \
X(Ds, 43, ds, 0, 2) \
X(Fs, 44, fs, 0, 2) \
X(Gs, 45, gs, 0, 2) \
X(Tr, 48, tr, 0, 0) \
X(Ldtr, 49, ldtr, 0, 0)
#define DW_Regs_X64_XList(X) \
X(Rax, 0, rax, 0, 8) \
X(Rdx, 1, rdx, 0, 8) \
@@ -1718,15 +1670,6 @@ X(Ldtr, 63, ldtr, 0, 0)
typedef U32 DW_Reg;
typedef DW_Reg DW_RegX86;
typedef enum DW_RegX86Enum
{
#define X(_N,_ID,...) DW_RegX86_##_N = _ID,
DW_Regs_X86_XList(X)
#undef X
DW_RegX86_Last
} DW_RegX86Enum;
typedef DW_Reg DW_RegX64;
typedef enum DW_RegX64Enum
{
@@ -1738,8 +1681,6 @@ typedef enum DW_RegX64Enum
////////////////////////////////
internal U64 dw_reg_size_from_code_x86(DW_Reg reg_code);
internal U64 dw_reg_pos_from_code_x86(DW_Reg reg_code);
internal U64 dw_reg_size_from_code_x64(DW_Reg reg_code);
internal U64 dw_reg_pos_from_code_x64(DW_Reg reg_code);
internal U64 dw_reg_size_from_code(Arch arch, DW_Reg reg_code);
src/lib_rdi/rdi.c
-1
View File
@@ -272,7 +272,6 @@ RDI_U32 result = 0;
switch(arch)
{
default:{}break;
case RDI_Arch_X86:{result = 4;}break;
case RDI_Arch_X64:{result = 8;}break;
}
return result;
src/lib_rdi/rdi.h
+1 -120
View File
@@ -132,8 +132,7 @@ typedef RDI_U32 RDI_Arch;
typedef enum RDI_ArchEnum
{
RDI_Arch_NULL = 0,
RDI_Arch_X86 = 1,
RDI_Arch_X64 = 2,
RDI_Arch_X64 = 1,
} RDI_ArchEnum;
typedef RDI_U8 RDI_RegCode;
@@ -142,66 +141,6 @@ typedef enum RDI_RegCodeEnum
RDI_RegCode_nil,
} RDI_RegCodeEnum;
typedef RDI_U8 RDI_RegCodeX86;
typedef enum RDI_RegCodeX86Enum
{
RDI_RegCodeX86_nil = 0,
RDI_RegCodeX86_eax = 1,
RDI_RegCodeX86_ecx = 2,
RDI_RegCodeX86_edx = 3,
RDI_RegCodeX86_ebx = 4,
RDI_RegCodeX86_esp = 5,
RDI_RegCodeX86_ebp = 6,
RDI_RegCodeX86_esi = 7,
RDI_RegCodeX86_edi = 8,
RDI_RegCodeX86_fsbase = 9,
RDI_RegCodeX86_gsbase = 10,
RDI_RegCodeX86_eflags = 11,
RDI_RegCodeX86_eip = 12,
RDI_RegCodeX86_dr0 = 13,
RDI_RegCodeX86_dr1 = 14,
RDI_RegCodeX86_dr2 = 15,
RDI_RegCodeX86_dr3 = 16,
RDI_RegCodeX86_dr4 = 17,
RDI_RegCodeX86_dr5 = 18,
RDI_RegCodeX86_dr6 = 19,
RDI_RegCodeX86_dr7 = 20,
RDI_RegCodeX86_st0 = 21,
RDI_RegCodeX86_st1 = 22,
RDI_RegCodeX86_st2 = 23,
RDI_RegCodeX86_st3 = 24,
RDI_RegCodeX86_st4 = 25,
RDI_RegCodeX86_st5 = 26,
RDI_RegCodeX86_st6 = 27,
RDI_RegCodeX86_st7 = 28,
RDI_RegCodeX86_fcw = 29,
RDI_RegCodeX86_fsw = 30,
RDI_RegCodeX86_ftw = 31,
RDI_RegCodeX86_fop = 32,
RDI_RegCodeX86_fcs = 33,
RDI_RegCodeX86_fds = 34,
RDI_RegCodeX86_fip = 35,
RDI_RegCodeX86_fdp = 36,
RDI_RegCodeX86_mxcsr = 37,
RDI_RegCodeX86_mxcsr_mask = 38,
RDI_RegCodeX86_ss = 39,
RDI_RegCodeX86_cs = 40,
RDI_RegCodeX86_ds = 41,
RDI_RegCodeX86_es = 42,
RDI_RegCodeX86_fs = 43,
RDI_RegCodeX86_gs = 44,
RDI_RegCodeX86_ymm0 = 45,
RDI_RegCodeX86_ymm1 = 46,
RDI_RegCodeX86_ymm2 = 47,
RDI_RegCodeX86_ymm3 = 48,
RDI_RegCodeX86_ymm4 = 49,
RDI_RegCodeX86_ymm5 = 50,
RDI_RegCodeX86_ymm6 = 51,
RDI_RegCodeX86_ymm7 = 52,
RDI_RegCodeX86_tr = 53,
RDI_RegCodeX86_ldtr = 54,
} RDI_RegCodeX86Enum;
typedef RDI_U8 RDI_RegCodeX64;
typedef enum RDI_RegCodeX64Enum
{
@@ -623,66 +562,8 @@ X(RDI_U64, idx)\
#define RDI_Arch_XList \
X(NULL)\
X(X86)\
X(X64)\
#define RDI_RegCodeX86_XList \
X(nil, 0)\
X(eax, 1)\
X(ecx, 2)\
X(edx, 3)\
X(ebx, 4)\
X(esp, 5)\
X(ebp, 6)\
X(esi, 7)\
X(edi, 8)\
X(fsbase, 9)\
X(gsbase, 10)\
X(eflags, 11)\
X(eip, 12)\
X(dr0, 13)\
X(dr1, 14)\
X(dr2, 15)\
X(dr3, 16)\
X(dr4, 17)\
X(dr5, 18)\
X(dr6, 19)\
X(dr7, 20)\
X(st0, 21)\
X(st1, 22)\
X(st2, 23)\
X(st3, 24)\
X(st4, 25)\
X(st5, 26)\
X(st6, 27)\
X(st7, 28)\
X(fcw, 29)\
X(fsw, 30)\
X(ftw, 31)\
X(fop, 32)\
X(fcs, 33)\
X(fds, 34)\
X(fip, 35)\
X(fdp, 36)\
X(mxcsr, 37)\
X(mxcsr_mask, 38)\
X(ss, 39)\
X(cs, 40)\
X(ds, 41)\
X(es, 42)\
X(fs, 43)\
X(gs, 44)\
X(ymm0, 45)\
X(ymm1, 46)\
X(ymm2, 47)\
X(ymm3, 48)\
X(ymm4, 49)\
X(ymm5, 50)\
X(ymm6, 51)\
X(ymm7, 52)\
X(tr, 53)\
X(ldtr, 54)\
#define RDI_RegCodeX64_XList \
X(nil, 0)\
X(rax, 1)\
src/linker/rdi/rdi_builder.c
-3
View File
@@ -9,7 +9,6 @@ rdib_infer_data_model(OperatingSystem os, RDI_Arch arch)
case OperatingSystem_Null: break;
case OperatingSystem_Windows: {
switch (arch) {
case RDI_Arch_X86:
case RDI_Arch_X64:
data_model = RDIB_DataModel_LLP64; break;
default: NotImplemented;
@@ -17,14 +16,12 @@ rdib_infer_data_model(OperatingSystem os, RDI_Arch arch)
} break;
case OperatingSystem_Linux: {
switch (arch) {
case RDI_Arch_X86: data_model = RDIB_DataModel_ILP32; break;
case RDI_Arch_X64: data_model = RDIB_DataModel_LLP64; break;
default: NotImplemented;
}
} break;
case OperatingSystem_Mac: {
switch (arch) {
case RDI_Arch_X86: NotImplemented; break;
case RDI_Arch_X64: data_model = RDIB_DataModel_LP64; break;
}
} break;
src/linker/rdi/rdi_coff.c
+1 -1
View File
@@ -5,9 +5,9 @@ internal RDI_Arch
rdi_arch_from_coff_machine(COFF_MachineType machine)
{
switch (machine) {
case COFF_MachineType_X86: return RDI_Arch_X86;
case COFF_MachineType_X64: return RDI_Arch_X64;
case COFF_MachineType_X86:
case COFF_MachineType_Unknown:
case COFF_MachineType_Am33:
case COFF_MachineType_Arm:
src/linker/rdi/rdi_cv.c
+2 -8
View File
@@ -5,9 +5,9 @@ internal RDI_Arch
rdi_arch_from_cv_arch(CV_Arch arch)
{
switch (arch) {
case CV_Arch_8086: return RDI_Arch_X86;
case CV_Arch_X64: return RDI_Arch_X64;
case CV_Arch_8086:
case CV_Arch_8080:
case CV_Arch_80286:
case CV_Arch_80386:
@@ -211,13 +211,6 @@ rdi_reg_code_from_cv(CV_Arch arch, CV_Reg reg)
{
RDI_RegCode result = 0;
switch (arch) {
case CV_Arch_8086: {
switch (reg) {
#define X(CVN,C,RDN,BP,BZ) case C: result = RDI_RegCodeX86_##RDN; break;
CV_Reg_X86_XList(X)
#undef X
}
} break;
case CV_Arch_X64: {
switch (reg) {
#define X(CVN,C,RDN,BP,BZ) case C: result = RDI_RegCodeX64_##RDN; break;
@@ -225,6 +218,7 @@ rdi_reg_code_from_cv(CV_Arch arch, CV_Reg reg)
#undef X
}
} break;
case CV_Arch_8086:
default: NotImplemented;
}
return result;
src/rdi/rdi.mdesk
+1 -72
View File
@@ -278,68 +278,7 @@ RDI_VMapEntryMemberTable:
RDI_ArchTable:
{
{NULL 0 0}
{X86 1 4}
{X64 2 8}
}
@table(name value)
RDI_RegCodeX86Table:
{
{nil 0}
{eax 1}
{ecx 2}
{edx 3}
{ebx 4}
{esp 5}
{ebp 6}
{esi 7}
{edi 8}
{fsbase 9}
{gsbase 10}
{eflags 11}
{eip 12}
{dr0 13}
{dr1 14}
{dr2 15}
{dr3 16}
{dr4 17}
{dr5 18}
{dr6 19}
{dr7 20}
{st0 21}
{st1 22}
{st2 23}
{st3 24}
{st4 25}
{st5 26}
{st6 27}
{st7 28}
{fcw 29}
{fsw 30}
{ftw 31}
{fop 32}
{fcs 33}
{fds 34}
{fip 35}
{fdp 36}
{mxcsr 37}
{mxcsr_mask 38}
{ss 39}
{cs 40}
{ds 41}
{es 42}
{fs 43}
{gs 44}
{ymm0 45}
{ymm1 46}
{ymm2 47}
{ymm3 48}
{ymm4 49}
{ymm5 50}
{ymm6 51}
{ymm7 52}
{tr 53}
{ldtr 54}
{X64 1 8}
}
@table(name value)
@@ -456,21 +395,11 @@ RDI_RegCodeX64Table:
@enum(RDI_U8) RDI_RegCode: {nil}
@enum(RDI_U8) RDI_RegCodeX86:
{
@expand(RDI_RegCodeX86Table a) `$(a.name .. =>10) = $(a.value)`
}
@enum(RDI_U8) RDI_RegCodeX64:
{
@expand(RDI_RegCodeX64Table a) `$(a.name .. =>10) = $(a.value)`
}
@xlist RDI_RegCodeX86_XList:
{
@expand(RDI_RegCodeX86Table a) `$(a.name), $(a.value)`
}
@xlist RDI_RegCodeX64_XList:
{
@expand(RDI_RegCodeX64Table a) `$(a.name), $(a.value)`
src/rdi/rdi_local.c
-16
View File
@@ -14,7 +14,6 @@ arch_from_rdi_arch(RDI_Arch arch)
switch((RDI_ArchEnum)arch)
{
case RDI_Arch_NULL:{}break;
case RDI_Arch_X86:{result = Arch_x86;}break;
case RDI_Arch_X64:{result = Arch_x64;}break;
}
return result;
@@ -134,20 +133,6 @@ rdi_string_from_name_map_kind(RDI_NameMapKind kind)
return result;
}
internal String8
rdi_string_from_reg_code_x86(U64 reg_code)
{
String8 result = {0};
switch(reg_code)
{
default:{}break;
#define X(name, value) case RDI_RegCodeX86_##name:{result = str8_lit(#name);}break;
RDI_RegCodeX86_XList
#undef X
}
return result;
}
internal String8
rdi_string_from_reg_code_x64(U64 reg_code)
{
@@ -170,7 +155,6 @@ rdi_string_from_reg_code(Arena *arena, RDI_Arch arch, U64 reg_code)
{
default:
case RDI_Arch_NULL: {result = push_str8f(arena, "??? (%llu)", reg_code);}break;
case RDI_Arch_X86: {result = rdi_string_from_reg_code_x86(reg_code);}break;
case RDI_Arch_X64: {result = rdi_string_from_reg_code_x64(reg_code);}break;
}
return result;
src/rdi_from_coff/rdi_from_coff.c
+1 -1
View File
@@ -5,9 +5,9 @@ internal RDI_Arch
c2r_rdi_arch_from_coff_machine(COFF_MachineType machine)
{
switch (machine) {
case COFF_MachineType_X86: return RDI_Arch_X86;
case COFF_MachineType_X64: return RDI_Arch_X64;
case COFF_MachineType_X86:
case COFF_MachineType_Unknown:
case COFF_MachineType_Am33:
case COFF_MachineType_Arm:
src/rdi_from_dwarf/rdi_from_dwarf.c
+2 -17
View File
@@ -65,20 +65,6 @@ d2r_rdi_language_from_dw_language(DW_Language v)
return result;
}
internal RDI_RegCodeX86
d2r_rdi_reg_code_from_dw_reg_x86(DW_RegX86 v)
{
RDI_RegCodeX86 result = RDI_RegCode_nil;
switch(v)
{
default:{}break;
#define X(reg_dw, val_dw, reg_rdi, ...) case DW_RegX86_##reg_dw: result = RDI_RegCodeX86_##reg_rdi; break;
DW_Regs_X86_XList(X)
#undef X
}
return result;
}
internal RDI_RegCodeX64
d2r_rdi_reg_code_from_dw_reg_x64(DW_RegX64 v)
{
@@ -99,9 +85,8 @@ d2r_rdi_reg_code_from_dw_reg(Arch arch, DW_Reg v)
RDI_RegCode result = RDI_RegCode_nil;
switch(arch)
{
default:
case Arch_Null:
case Arch_x86:{result = d2r_rdi_reg_code_from_dw_reg_x86(v);}break;
default: NotImplemented; break;
case Arch_Null: break;
case Arch_x64:{result = d2r_rdi_reg_code_from_dw_reg_x64(v);}break;
}
return result;
src/rdi_from_dwarf/rdi_from_dwarf.h
-1
View File
@@ -98,7 +98,6 @@ typedef struct D2R_ValueTypeStack
//~ rjf: Enum Conversion Helpers
internal RDI_Language d2r_rdi_language_from_dw_language(DW_Language v);
internal RDI_RegCodeX86 d2r_rdi_reg_code_from_dw_reg_x86(DW_RegX86 v);
internal RDI_RegCodeX64 d2r_rdi_reg_code_from_dw_reg_x64(DW_RegX64 v);
internal RDI_RegCode d2r_rdi_reg_code_from_dw_reg(Arch arch, DW_Reg v);
src/rdi_from_pdb/rdi_from_pdb.c
+1 -34
View File
@@ -69,7 +69,7 @@ p2r_rdi_arch_from_cv_arch(CV_Arch cv_arch)
RDI_Arch result = 0;
switch(cv_arch)
{
case CV_Arch_8086: result = RDI_Arch_X86; break;
case CV_Arch_8086: NotImplemented; break;
case CV_Arch_X64: result = RDI_Arch_X64; break;
//case CV_Arch_8080: break;
//case CV_Arch_80286: break;
@@ -139,15 +139,6 @@ p2r_rdi_reg_code_from_cv_reg_code(RDI_Arch arch, CV_Reg reg_code)
RDI_RegCode result = 0;
switch(arch)
{
case RDI_Arch_X86:
{
switch(reg_code)
{
#define X(CVN,C,RDN,BP,BZ) case C: result = RDI_RegCodeX86_##RDN; break;
CV_Reg_X86_XList(X)
#undef X
}
}break;
case RDI_Arch_X64:
{
switch(reg_code)
@@ -287,25 +278,6 @@ p2r_reg_code_from_arch_encoded_fp_reg(RDI_Arch arch, CV_EncodedFramePtrReg encod
RDI_RegCode result = 0;
switch(arch)
{
case RDI_Arch_X86:
{
switch(encoded_reg)
{
case CV_EncodedFramePtrReg_StackPtr:
{
// TODO(allen): support CV_AllReg_VFRAME
// TODO(allen): error
}break;
case CV_EncodedFramePtrReg_FramePtr:
{
result = RDI_RegCodeX86_ebp;
}break;
case CV_EncodedFramePtrReg_BasePtr:
{
result = RDI_RegCodeX86_ebx;
}break;
}
}break;
case RDI_Arch_X64:
{
switch(encoded_reg)
@@ -3762,7 +3734,6 @@ p2r_convert(Arena *arena, P2R_ConvertParams *params)
switch(arch)
{
default:{}break;
case RDI_Arch_X86:{is_stack_reg = (cv_reg == CV_Regx86_ESP || cv_reg == CV_Regx86_EBP);}break;
case RDI_Arch_X64:{is_stack_reg = (cv_reg == CV_Regx64_RSP || cv_reg == CV_Regx64_RBP);}break;
}
if(is_stack_reg)
@@ -3804,10 +3775,6 @@ p2r_convert(Arena *arena, P2R_ConvertParams *params)
B32 extra_indirection_to_value = 0;
switch(arch)
{
case RDI_Arch_X86:
{
extra_indirection_to_value = (local_kind == RDI_LocalKind_Parameter && (type->byte_size > 4 || !IsPow2OrZero(type->byte_size)));
}break;
case RDI_Arch_X64:
{
extra_indirection_to_value = (local_kind == RDI_LocalKind_Parameter && (type->byte_size > 8 || !IsPow2OrZero(type->byte_size)));
src/rdi_make/rdi_make_local.c
+1 -1
View File
@@ -26,7 +26,7 @@ rdim_make_top_level_info(String8 image_name, Arch arch, U64 exe_hash, RDIM_Binar
{
default:{}break;
case Arch_x64:{arch_rdi = RDI_Arch_X64;}break;
case Arch_x86:{arch_rdi = RDI_Arch_X86;}break;
case Arch_x86:{NotImplemented;}break;
}
// find max VOFF
src/regs/generated/regs.meta.c
+3 -312
View File
@@ -10,7 +10,6 @@ switch(arch)
{
default:{}break;
case Arch_x64:{result = sizeof(REGS_RegBlockX64);}break;
case Arch_x86:{result = sizeof(REGS_RegBlockX86);}break;
}
return result;
}
@@ -21,7 +20,6 @@ switch(arch)
{
default:{}break;
case Arch_x64:{result = REGS_RegCodeX64_COUNT;}break;
case Arch_x86:{result = REGS_RegCodeX86_COUNT;}break;
}
return result;
}
@@ -32,7 +30,6 @@ switch(arch)
{
default:{}break;
case Arch_x64:{result = REGS_AliasCodeX64_COUNT;}break;
case Arch_x86:{result = REGS_AliasCodeX86_COUNT;}break;
}
return result;
}
@@ -43,7 +40,6 @@ switch(arch)
{
default:{}break;
case Arch_x64:{result = regs_g_reg_code_x64_string_table;}break;
case Arch_x86:{result = regs_g_reg_code_x86_string_table;}break;
}
return result;
}
@@ -54,7 +50,6 @@ switch(arch)
{
default:{}break;
case Arch_x64:{result = regs_g_alias_code_x64_string_table;}break;
case Arch_x86:{result = regs_g_alias_code_x86_string_table;}break;
}
return result;
}
@@ -65,7 +60,6 @@ switch(arch)
{
default:{}break;
case Arch_x64:{result = regs_g_reg_code_x64_rng_table;}break;
case Arch_x86:{result = regs_g_reg_code_x86_rng_table;}break;
}
return result;
}
@@ -76,7 +70,6 @@ switch(arch)
{
default:{}break;
case Arch_x64:{result = regs_g_alias_code_x64_slice_table;}break;
case Arch_x86:{result = regs_g_alias_code_x86_slice_table;}break;
}
return result;
}
@@ -87,7 +80,6 @@ switch(arch)
{
default:{}break;
case Arch_x64:{result = regs_g_reg_code_x64_usage_kind_table;}break;
case Arch_x86:{result = regs_g_reg_code_x86_usage_kind_table;}break;
}
return result;
}
@@ -98,7 +90,6 @@ switch(arch)
{
default:{}break;
case Arch_x64:{result = regs_g_alias_code_x64_usage_kind_table;}break;
case Arch_x86:{result = regs_g_alias_code_x86_usage_kind_table;}break;
}
return result;
}
@@ -202,7 +193,7 @@ REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
};
REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[96] =
REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[95] =
{
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
@@ -259,7 +250,6 @@ REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
@@ -401,7 +391,7 @@ str8_lit_comp("tr"),
str8_lit_comp("ldtr"),
};
String8 regs_g_alias_code_x64_string_table[96] =
String8 regs_g_alias_code_x64_string_table[95] =
{
str8_lit_comp(""),
str8_lit_comp("eax"),
@@ -420,7 +410,6 @@ str8_lit_comp("r12d"),
str8_lit_comp("r13d"),
str8_lit_comp("r14d"),
str8_lit_comp("r15d"),
str8_lit_comp("eip"),
str8_lit_comp("eflags"),
str8_lit_comp("ax"),
str8_lit_comp("cx"),
@@ -600,7 +589,7 @@ REGS_Rng regs_g_reg_code_x64_rng_table[95] =
{(U16)OffsetOf(REGS_RegBlockX64, ldtr), 2},
};
REGS_Slice regs_g_alias_code_x64_slice_table[96] =
REGS_Slice regs_g_alias_code_x64_slice_table[95] =
{
{0},
{REGS_RegCodeX64_rax, 0, 4},
@@ -619,7 +608,6 @@ REGS_Slice regs_g_alias_code_x64_slice_table[96] =
{REGS_RegCodeX64_r13, 0, 4},
{REGS_RegCodeX64_r14, 0, 4},
{REGS_RegCodeX64_r15, 0, 4},
{REGS_RegCodeX64_rip, 0, 4},
{REGS_RegCodeX64_rflags, 0, 4},
{REGS_RegCodeX64_rax, 0, 2},
{REGS_RegCodeX64_rcx, 0, 2},
@@ -700,302 +688,5 @@ REGS_Slice regs_g_alias_code_x64_slice_table[96] =
{REGS_RegCodeX64_st7, 0, 8},
};
REGS_UsageKind regs_g_reg_code_x86_usage_kind_table[55] =
{
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
};
REGS_UsageKind regs_g_alias_code_x86_usage_kind_table[36] =
{
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
};
String8 regs_g_reg_code_x86_string_table[55] =
{
str8_lit_comp(""),
str8_lit_comp("eax"),
str8_lit_comp("ecx"),
str8_lit_comp("edx"),
str8_lit_comp("ebx"),
str8_lit_comp("esp"),
str8_lit_comp("ebp"),
str8_lit_comp("esi"),
str8_lit_comp("edi"),
str8_lit_comp("fsbase"),
str8_lit_comp("gsbase"),
str8_lit_comp("eflags"),
str8_lit_comp("eip"),
str8_lit_comp("dr0"),
str8_lit_comp("dr1"),
str8_lit_comp("dr2"),
str8_lit_comp("dr3"),
str8_lit_comp("dr4"),
str8_lit_comp("dr5"),
str8_lit_comp("dr6"),
str8_lit_comp("dr7"),
str8_lit_comp("st0"),
str8_lit_comp("st1"),
str8_lit_comp("st2"),
str8_lit_comp("st3"),
str8_lit_comp("st4"),
str8_lit_comp("st5"),
str8_lit_comp("st6"),
str8_lit_comp("st7"),
str8_lit_comp("fcw"),
str8_lit_comp("fsw"),
str8_lit_comp("ftw"),
str8_lit_comp("fop"),
str8_lit_comp("fcs"),
str8_lit_comp("fds"),
str8_lit_comp("fip"),
str8_lit_comp("fdp"),
str8_lit_comp("mxcsr"),
str8_lit_comp("mxcsr_mask"),
str8_lit_comp("ss"),
str8_lit_comp("cs"),
str8_lit_comp("ds"),
str8_lit_comp("es"),
str8_lit_comp("fs"),
str8_lit_comp("gs"),
str8_lit_comp("tr"),
str8_lit_comp("ldtr"),
str8_lit_comp("ymm0"),
str8_lit_comp("ymm1"),
str8_lit_comp("ymm2"),
str8_lit_comp("ymm3"),
str8_lit_comp("ymm4"),
str8_lit_comp("ymm5"),
str8_lit_comp("ymm6"),
str8_lit_comp("ymm7"),
};
String8 regs_g_alias_code_x86_string_table[36] =
{
str8_lit_comp(""),
str8_lit_comp("ax"),
str8_lit_comp("cx"),
str8_lit_comp("bx"),
str8_lit_comp("dx"),
str8_lit_comp("sp"),
str8_lit_comp("bp"),
str8_lit_comp("si"),
str8_lit_comp("di"),
str8_lit_comp("ip"),
str8_lit_comp("ah"),
str8_lit_comp("ch"),
str8_lit_comp("dh"),
str8_lit_comp("bh"),
str8_lit_comp("al"),
str8_lit_comp("cl"),
str8_lit_comp("dl"),
str8_lit_comp("bl"),
str8_lit_comp("bpl"),
str8_lit_comp("spl"),
str8_lit_comp("xmm0"),
str8_lit_comp("xmm1"),
str8_lit_comp("xmm2"),
str8_lit_comp("xmm3"),
str8_lit_comp("xmm4"),
str8_lit_comp("xmm5"),
str8_lit_comp("xmm6"),
str8_lit_comp("xmm7"),
str8_lit_comp("mm0"),
str8_lit_comp("mm1"),
str8_lit_comp("mm2"),
str8_lit_comp("mm3"),
str8_lit_comp("mm4"),
str8_lit_comp("mm5"),
str8_lit_comp("mm6"),
str8_lit_comp("mm7"),
};
REGS_Rng regs_g_reg_code_x86_rng_table[55] =
{
{0},
{(U16)OffsetOf(REGS_RegBlockX86, eax), 4},
{(U16)OffsetOf(REGS_RegBlockX86, ecx), 4},
{(U16)OffsetOf(REGS_RegBlockX86, edx), 4},
{(U16)OffsetOf(REGS_RegBlockX86, ebx), 4},
{(U16)OffsetOf(REGS_RegBlockX86, esp), 4},
{(U16)OffsetOf(REGS_RegBlockX86, ebp), 4},
{(U16)OffsetOf(REGS_RegBlockX86, esi), 4},
{(U16)OffsetOf(REGS_RegBlockX86, edi), 4},
{(U16)OffsetOf(REGS_RegBlockX86, fsbase), 4},
{(U16)OffsetOf(REGS_RegBlockX86, gsbase), 4},
{(U16)OffsetOf(REGS_RegBlockX86, eflags), 4},
{(U16)OffsetOf(REGS_RegBlockX86, eip), 4},
{(U16)OffsetOf(REGS_RegBlockX86, dr0), 4},
{(U16)OffsetOf(REGS_RegBlockX86, dr1), 4},
{(U16)OffsetOf(REGS_RegBlockX86, dr2), 4},
{(U16)OffsetOf(REGS_RegBlockX86, dr3), 4},
{(U16)OffsetOf(REGS_RegBlockX86, dr4), 4},
{(U16)OffsetOf(REGS_RegBlockX86, dr5), 4},
{(U16)OffsetOf(REGS_RegBlockX86, dr6), 4},
{(U16)OffsetOf(REGS_RegBlockX86, dr7), 4},
{(U16)OffsetOf(REGS_RegBlockX86, st0), 10},
{(U16)OffsetOf(REGS_RegBlockX86, st1), 10},
{(U16)OffsetOf(REGS_RegBlockX86, st2), 10},
{(U16)OffsetOf(REGS_RegBlockX86, st3), 10},
{(U16)OffsetOf(REGS_RegBlockX86, st4), 10},
{(U16)OffsetOf(REGS_RegBlockX86, st5), 10},
{(U16)OffsetOf(REGS_RegBlockX86, st6), 10},
{(U16)OffsetOf(REGS_RegBlockX86, st7), 10},
{(U16)OffsetOf(REGS_RegBlockX86, fcw), 2},
{(U16)OffsetOf(REGS_RegBlockX86, fsw), 2},
{(U16)OffsetOf(REGS_RegBlockX86, ftw), 2},
{(U16)OffsetOf(REGS_RegBlockX86, fop), 2},
{(U16)OffsetOf(REGS_RegBlockX86, fcs), 2},
{(U16)OffsetOf(REGS_RegBlockX86, fds), 2},
{(U16)OffsetOf(REGS_RegBlockX86, fip), 4},
{(U16)OffsetOf(REGS_RegBlockX86, fdp), 4},
{(U16)OffsetOf(REGS_RegBlockX86, mxcsr), 4},
{(U16)OffsetOf(REGS_RegBlockX86, mxcsr_mask), 4},
{(U16)OffsetOf(REGS_RegBlockX86, ss), 2},
{(U16)OffsetOf(REGS_RegBlockX86, cs), 2},
{(U16)OffsetOf(REGS_RegBlockX86, ds), 2},
{(U16)OffsetOf(REGS_RegBlockX86, es), 2},
{(U16)OffsetOf(REGS_RegBlockX86, fs), 2},
{(U16)OffsetOf(REGS_RegBlockX86, gs), 2},
{(U16)OffsetOf(REGS_RegBlockX86, tr), 2},
{(U16)OffsetOf(REGS_RegBlockX86, ldtr), 2},
{(U16)OffsetOf(REGS_RegBlockX86, ymm0), 32},
{(U16)OffsetOf(REGS_RegBlockX86, ymm1), 32},
{(U16)OffsetOf(REGS_RegBlockX86, ymm2), 32},
{(U16)OffsetOf(REGS_RegBlockX86, ymm3), 32},
{(U16)OffsetOf(REGS_RegBlockX86, ymm4), 32},
{(U16)OffsetOf(REGS_RegBlockX86, ymm5), 32},
{(U16)OffsetOf(REGS_RegBlockX86, ymm6), 32},
{(U16)OffsetOf(REGS_RegBlockX86, ymm7), 32},
};
REGS_Slice regs_g_alias_code_x86_slice_table[36] =
{
{0},
{REGS_RegCodeX86_eax, 0, 2},
{REGS_RegCodeX86_ecx, 0, 2},
{REGS_RegCodeX86_ebx, 0, 2},
{REGS_RegCodeX86_edx, 0, 2},
{REGS_RegCodeX86_esp, 0, 2},
{REGS_RegCodeX86_ebp, 0, 2},
{REGS_RegCodeX86_esi, 0, 2},
{REGS_RegCodeX86_edi, 0, 2},
{REGS_RegCodeX86_eip, 0, 2},
{REGS_RegCodeX86_eax, 1, 1},
{REGS_RegCodeX86_ecx, 1, 1},
{REGS_RegCodeX86_edx, 1, 1},
{REGS_RegCodeX86_ebx, 1, 1},
{REGS_RegCodeX86_eax, 0, 1},
{REGS_RegCodeX86_ecx, 0, 1},
{REGS_RegCodeX86_edx, 0, 1},
{REGS_RegCodeX86_ebx, 0, 1},
{REGS_RegCodeX86_ebp, 0, 1},
{REGS_RegCodeX86_esp, 0, 1},
{REGS_RegCodeX86_ymm0, 0, 16},
{REGS_RegCodeX86_ymm1, 0, 16},
{REGS_RegCodeX86_ymm2, 0, 16},
{REGS_RegCodeX86_ymm3, 0, 16},
{REGS_RegCodeX86_ymm4, 0, 16},
{REGS_RegCodeX86_ymm5, 0, 16},
{REGS_RegCodeX86_ymm6, 0, 16},
{REGS_RegCodeX86_ymm7, 0, 16},
{REGS_RegCodeX86_st0, 0, 8},
{REGS_RegCodeX86_st1, 0, 8},
{REGS_RegCodeX86_st2, 0, 8},
{REGS_RegCodeX86_st3, 0, 8},
{REGS_RegCodeX86_st4, 0, 8},
{REGS_RegCodeX86_st5, 0, 8},
{REGS_RegCodeX86_st6, 0, 8},
{REGS_RegCodeX86_st7, 0, 8},
};
C_LINKAGE_END
src/regs/generated/regs.meta.h
+3 -170
View File
@@ -125,7 +125,6 @@ REGS_AliasCodeX64_r12d,
REGS_AliasCodeX64_r13d,
REGS_AliasCodeX64_r14d,
REGS_AliasCodeX64_r15d,
REGS_AliasCodeX64_eip,
REGS_AliasCodeX64_eflags,
REGS_AliasCodeX64_ax,
REGS_AliasCodeX64_cx,
@@ -207,107 +206,6 @@ REGS_AliasCodeX64_mm7,
REGS_AliasCodeX64_COUNT,
} REGS_AliasCodeX64;
typedef enum REGS_RegCodeX86
{
REGS_RegCodeX86_NULL,
REGS_RegCodeX86_eax,
REGS_RegCodeX86_ecx,
REGS_RegCodeX86_edx,
REGS_RegCodeX86_ebx,
REGS_RegCodeX86_esp,
REGS_RegCodeX86_ebp,
REGS_RegCodeX86_esi,
REGS_RegCodeX86_edi,
REGS_RegCodeX86_fsbase,
REGS_RegCodeX86_gsbase,
REGS_RegCodeX86_eflags,
REGS_RegCodeX86_eip,
REGS_RegCodeX86_dr0,
REGS_RegCodeX86_dr1,
REGS_RegCodeX86_dr2,
REGS_RegCodeX86_dr3,
REGS_RegCodeX86_dr4,
REGS_RegCodeX86_dr5,
REGS_RegCodeX86_dr6,
REGS_RegCodeX86_dr7,
REGS_RegCodeX86_st0,
REGS_RegCodeX86_st1,
REGS_RegCodeX86_st2,
REGS_RegCodeX86_st3,
REGS_RegCodeX86_st4,
REGS_RegCodeX86_st5,
REGS_RegCodeX86_st6,
REGS_RegCodeX86_st7,
REGS_RegCodeX86_fcw,
REGS_RegCodeX86_fsw,
REGS_RegCodeX86_ftw,
REGS_RegCodeX86_fop,
REGS_RegCodeX86_fcs,
REGS_RegCodeX86_fds,
REGS_RegCodeX86_fip,
REGS_RegCodeX86_fdp,
REGS_RegCodeX86_mxcsr,
REGS_RegCodeX86_mxcsr_mask,
REGS_RegCodeX86_ss,
REGS_RegCodeX86_cs,
REGS_RegCodeX86_ds,
REGS_RegCodeX86_es,
REGS_RegCodeX86_fs,
REGS_RegCodeX86_gs,
REGS_RegCodeX86_tr,
REGS_RegCodeX86_ldtr,
REGS_RegCodeX86_ymm0,
REGS_RegCodeX86_ymm1,
REGS_RegCodeX86_ymm2,
REGS_RegCodeX86_ymm3,
REGS_RegCodeX86_ymm4,
REGS_RegCodeX86_ymm5,
REGS_RegCodeX86_ymm6,
REGS_RegCodeX86_ymm7,
REGS_RegCodeX86_COUNT,
} REGS_RegCodeX86;
typedef enum REGS_AliasCodeX86
{
REGS_AliasCodeX86_NULL,
REGS_AliasCodeX86_ax,
REGS_AliasCodeX86_cx,
REGS_AliasCodeX86_bx,
REGS_AliasCodeX86_dx,
REGS_AliasCodeX86_sp,
REGS_AliasCodeX86_bp,
REGS_AliasCodeX86_si,
REGS_AliasCodeX86_di,
REGS_AliasCodeX86_ip,
REGS_AliasCodeX86_ah,
REGS_AliasCodeX86_ch,
REGS_AliasCodeX86_dh,
REGS_AliasCodeX86_bh,
REGS_AliasCodeX86_al,
REGS_AliasCodeX86_cl,
REGS_AliasCodeX86_dl,
REGS_AliasCodeX86_bl,
REGS_AliasCodeX86_bpl,
REGS_AliasCodeX86_spl,
REGS_AliasCodeX86_xmm0,
REGS_AliasCodeX86_xmm1,
REGS_AliasCodeX86_xmm2,
REGS_AliasCodeX86_xmm3,
REGS_AliasCodeX86_xmm4,
REGS_AliasCodeX86_xmm5,
REGS_AliasCodeX86_xmm6,
REGS_AliasCodeX86_xmm7,
REGS_AliasCodeX86_mm0,
REGS_AliasCodeX86_mm1,
REGS_AliasCodeX86_mm2,
REGS_AliasCodeX86_mm3,
REGS_AliasCodeX86_mm4,
REGS_AliasCodeX86_mm5,
REGS_AliasCodeX86_mm6,
REGS_AliasCodeX86_mm7,
REGS_AliasCodeX86_COUNT,
} REGS_AliasCodeX86;
typedef struct REGS_RegBlockX64 REGS_RegBlockX64;
struct REGS_RegBlockX64
{
@@ -407,78 +305,13 @@ REGS_Reg16 tr;
REGS_Reg16 ldtr;
};
typedef struct REGS_RegBlockX86 REGS_RegBlockX86;
struct REGS_RegBlockX86
{
REGS_Reg32 eax;
REGS_Reg32 ecx;
REGS_Reg32 edx;
REGS_Reg32 ebx;
REGS_Reg32 esp;
REGS_Reg32 ebp;
REGS_Reg32 esi;
REGS_Reg32 edi;
REGS_Reg32 fsbase;
REGS_Reg32 gsbase;
REGS_Reg32 eflags;
REGS_Reg32 eip;
REGS_Reg32 dr0;
REGS_Reg32 dr1;
REGS_Reg32 dr2;
REGS_Reg32 dr3;
REGS_Reg32 dr4;
REGS_Reg32 dr5;
REGS_Reg32 dr6;
REGS_Reg32 dr7;
REGS_Reg80 st0;
REGS_Reg80 st1;
REGS_Reg80 st2;
REGS_Reg80 st3;
REGS_Reg80 st4;
REGS_Reg80 st5;
REGS_Reg80 st6;
REGS_Reg80 st7;
REGS_Reg16 fcw;
REGS_Reg16 fsw;
REGS_Reg16 ftw;
REGS_Reg16 fop;
REGS_Reg16 fcs;
REGS_Reg16 fds;
REGS_Reg32 fip;
REGS_Reg32 fdp;
REGS_Reg32 mxcsr;
REGS_Reg32 mxcsr_mask;
REGS_Reg16 ss;
REGS_Reg16 cs;
REGS_Reg16 ds;
REGS_Reg16 es;
REGS_Reg16 fs;
REGS_Reg16 gs;
REGS_Reg16 tr;
REGS_Reg16 ldtr;
REGS_Reg256 ymm0;
REGS_Reg256 ymm1;
REGS_Reg256 ymm2;
REGS_Reg256 ymm3;
REGS_Reg256 ymm4;
REGS_Reg256 ymm5;
REGS_Reg256 ymm6;
REGS_Reg256 ymm7;
};
C_LINKAGE_BEGIN
extern REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[95];
extern REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[96];
extern REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[95];
extern String8 regs_g_reg_code_x64_string_table[95];
extern String8 regs_g_alias_code_x64_string_table[96];
extern String8 regs_g_alias_code_x64_string_table[95];
extern REGS_Rng regs_g_reg_code_x64_rng_table[95];
extern REGS_Slice regs_g_alias_code_x64_slice_table[96];
extern REGS_UsageKind regs_g_reg_code_x86_usage_kind_table[55];
extern REGS_UsageKind regs_g_alias_code_x86_usage_kind_table[36];
extern String8 regs_g_reg_code_x86_string_table[55];
extern String8 regs_g_alias_code_x86_string_table[36];
extern REGS_Rng regs_g_reg_code_x86_rng_table[55];
extern REGS_Slice regs_g_alias_code_x86_slice_table[36];
extern REGS_Slice regs_g_alias_code_x64_slice_table[95];
C_LINKAGE_END
src/regs/rdi/generated/regs_rdi.meta.c
+2 -116
View File
@@ -112,64 +112,7 @@ case REGS_RegCodeX64_ldtr:{result = RDI_RegCodeX64_ldtr;}break;
}break;
case Arch_x86:
{
switch(code)
{
default:{}break;
case REGS_RegCodeX86_eax:{result = RDI_RegCodeX86_eax;}break;
case REGS_RegCodeX86_ecx:{result = RDI_RegCodeX86_ecx;}break;
case REGS_RegCodeX86_edx:{result = RDI_RegCodeX86_edx;}break;
case REGS_RegCodeX86_ebx:{result = RDI_RegCodeX86_ebx;}break;
case REGS_RegCodeX86_esp:{result = RDI_RegCodeX86_esp;}break;
case REGS_RegCodeX86_ebp:{result = RDI_RegCodeX86_ebp;}break;
case REGS_RegCodeX86_esi:{result = RDI_RegCodeX86_esi;}break;
case REGS_RegCodeX86_edi:{result = RDI_RegCodeX86_edi;}break;
case REGS_RegCodeX86_fsbase:{result = RDI_RegCodeX86_fsbase;}break;
case REGS_RegCodeX86_gsbase:{result = RDI_RegCodeX86_gsbase;}break;
case REGS_RegCodeX86_eflags:{result = RDI_RegCodeX86_eflags;}break;
case REGS_RegCodeX86_eip:{result = RDI_RegCodeX86_eip;}break;
case REGS_RegCodeX86_dr0:{result = RDI_RegCodeX86_dr0;}break;
case REGS_RegCodeX86_dr1:{result = RDI_RegCodeX86_dr1;}break;
case REGS_RegCodeX86_dr2:{result = RDI_RegCodeX86_dr2;}break;
case REGS_RegCodeX86_dr3:{result = RDI_RegCodeX86_dr3;}break;
case REGS_RegCodeX86_dr4:{result = RDI_RegCodeX86_dr4;}break;
case REGS_RegCodeX86_dr5:{result = RDI_RegCodeX86_dr5;}break;
case REGS_RegCodeX86_dr6:{result = RDI_RegCodeX86_dr6;}break;
case REGS_RegCodeX86_dr7:{result = RDI_RegCodeX86_dr7;}break;
case REGS_RegCodeX86_st0:{result = RDI_RegCodeX86_st0;}break;
case REGS_RegCodeX86_st1:{result = RDI_RegCodeX86_st1;}break;
case REGS_RegCodeX86_st2:{result = RDI_RegCodeX86_st2;}break;
case REGS_RegCodeX86_st3:{result = RDI_RegCodeX86_st3;}break;
case REGS_RegCodeX86_st4:{result = RDI_RegCodeX86_st4;}break;
case REGS_RegCodeX86_st5:{result = RDI_RegCodeX86_st5;}break;
case REGS_RegCodeX86_st6:{result = RDI_RegCodeX86_st6;}break;
case REGS_RegCodeX86_st7:{result = RDI_RegCodeX86_st7;}break;
case REGS_RegCodeX86_fcw:{result = RDI_RegCodeX86_fcw;}break;
case REGS_RegCodeX86_fsw:{result = RDI_RegCodeX86_fsw;}break;
case REGS_RegCodeX86_ftw:{result = RDI_RegCodeX86_ftw;}break;
case REGS_RegCodeX86_fop:{result = RDI_RegCodeX86_fop;}break;
case REGS_RegCodeX86_fcs:{result = RDI_RegCodeX86_fcs;}break;
case REGS_RegCodeX86_fds:{result = RDI_RegCodeX86_fds;}break;
case REGS_RegCodeX86_fip:{result = RDI_RegCodeX86_fip;}break;
case REGS_RegCodeX86_fdp:{result = RDI_RegCodeX86_fdp;}break;
case REGS_RegCodeX86_mxcsr:{result = RDI_RegCodeX86_mxcsr;}break;
case REGS_RegCodeX86_mxcsr_mask:{result = RDI_RegCodeX86_mxcsr_mask;}break;
case REGS_RegCodeX86_ss:{result = RDI_RegCodeX86_ss;}break;
case REGS_RegCodeX86_cs:{result = RDI_RegCodeX86_cs;}break;
case REGS_RegCodeX86_ds:{result = RDI_RegCodeX86_ds;}break;
case REGS_RegCodeX86_es:{result = RDI_RegCodeX86_es;}break;
case REGS_RegCodeX86_fs:{result = RDI_RegCodeX86_fs;}break;
case REGS_RegCodeX86_gs:{result = RDI_RegCodeX86_gs;}break;
case REGS_RegCodeX86_tr:{result = RDI_RegCodeX86_tr;}break;
case REGS_RegCodeX86_ldtr:{result = RDI_RegCodeX86_ldtr;}break;
case REGS_RegCodeX86_ymm0:{result = RDI_RegCodeX86_ymm0;}break;
case REGS_RegCodeX86_ymm1:{result = RDI_RegCodeX86_ymm1;}break;
case REGS_RegCodeX86_ymm2:{result = RDI_RegCodeX86_ymm2;}break;
case REGS_RegCodeX86_ymm3:{result = RDI_RegCodeX86_ymm3;}break;
case REGS_RegCodeX86_ymm4:{result = RDI_RegCodeX86_ymm4;}break;
case REGS_RegCodeX86_ymm5:{result = RDI_RegCodeX86_ymm5;}break;
case REGS_RegCodeX86_ymm6:{result = RDI_RegCodeX86_ymm6;}break;
case REGS_RegCodeX86_ymm7:{result = RDI_RegCodeX86_ymm7;}break;
}
NotImplemented;
}break;
}
return result;
@@ -283,64 +226,7 @@ case RDI_RegCodeX64_ldtr:{result = REGS_RegCodeX64_ldtr;}break;
}break;
case Arch_x86:
{
switch(code)
{
default:{}break;
case RDI_RegCodeX86_eax:{result = REGS_RegCodeX86_eax;}break;
case RDI_RegCodeX86_ecx:{result = REGS_RegCodeX86_ecx;}break;
case RDI_RegCodeX86_edx:{result = REGS_RegCodeX86_edx;}break;
case RDI_RegCodeX86_ebx:{result = REGS_RegCodeX86_ebx;}break;
case RDI_RegCodeX86_esp:{result = REGS_RegCodeX86_esp;}break;
case RDI_RegCodeX86_ebp:{result = REGS_RegCodeX86_ebp;}break;
case RDI_RegCodeX86_esi:{result = REGS_RegCodeX86_esi;}break;
case RDI_RegCodeX86_edi:{result = REGS_RegCodeX86_edi;}break;
case RDI_RegCodeX86_fsbase:{result = REGS_RegCodeX86_fsbase;}break;
case RDI_RegCodeX86_gsbase:{result = REGS_RegCodeX86_gsbase;}break;
case RDI_RegCodeX86_eflags:{result = REGS_RegCodeX86_eflags;}break;
case RDI_RegCodeX86_eip:{result = REGS_RegCodeX86_eip;}break;
case RDI_RegCodeX86_dr0:{result = REGS_RegCodeX86_dr0;}break;
case RDI_RegCodeX86_dr1:{result = REGS_RegCodeX86_dr1;}break;
case RDI_RegCodeX86_dr2:{result = REGS_RegCodeX86_dr2;}break;
case RDI_RegCodeX86_dr3:{result = REGS_RegCodeX86_dr3;}break;
case RDI_RegCodeX86_dr4:{result = REGS_RegCodeX86_dr4;}break;
case RDI_RegCodeX86_dr5:{result = REGS_RegCodeX86_dr5;}break;
case RDI_RegCodeX86_dr6:{result = REGS_RegCodeX86_dr6;}break;
case RDI_RegCodeX86_dr7:{result = REGS_RegCodeX86_dr7;}break;
case RDI_RegCodeX86_st0:{result = REGS_RegCodeX86_st0;}break;
case RDI_RegCodeX86_st1:{result = REGS_RegCodeX86_st1;}break;
case RDI_RegCodeX86_st2:{result = REGS_RegCodeX86_st2;}break;
case RDI_RegCodeX86_st3:{result = REGS_RegCodeX86_st3;}break;
case RDI_RegCodeX86_st4:{result = REGS_RegCodeX86_st4;}break;
case RDI_RegCodeX86_st5:{result = REGS_RegCodeX86_st5;}break;
case RDI_RegCodeX86_st6:{result = REGS_RegCodeX86_st6;}break;
case RDI_RegCodeX86_st7:{result = REGS_RegCodeX86_st7;}break;
case RDI_RegCodeX86_fcw:{result = REGS_RegCodeX86_fcw;}break;
case RDI_RegCodeX86_fsw:{result = REGS_RegCodeX86_fsw;}break;
case RDI_RegCodeX86_ftw:{result = REGS_RegCodeX86_ftw;}break;
case RDI_RegCodeX86_fop:{result = REGS_RegCodeX86_fop;}break;
case RDI_RegCodeX86_fcs:{result = REGS_RegCodeX86_fcs;}break;
case RDI_RegCodeX86_fds:{result = REGS_RegCodeX86_fds;}break;
case RDI_RegCodeX86_fip:{result = REGS_RegCodeX86_fip;}break;
case RDI_RegCodeX86_fdp:{result = REGS_RegCodeX86_fdp;}break;
case RDI_RegCodeX86_mxcsr:{result = REGS_RegCodeX86_mxcsr;}break;
case RDI_RegCodeX86_mxcsr_mask:{result = REGS_RegCodeX86_mxcsr_mask;}break;
case RDI_RegCodeX86_ss:{result = REGS_RegCodeX86_ss;}break;
case RDI_RegCodeX86_cs:{result = REGS_RegCodeX86_cs;}break;
case RDI_RegCodeX86_ds:{result = REGS_RegCodeX86_ds;}break;
case RDI_RegCodeX86_es:{result = REGS_RegCodeX86_es;}break;
case RDI_RegCodeX86_fs:{result = REGS_RegCodeX86_fs;}break;
case RDI_RegCodeX86_gs:{result = REGS_RegCodeX86_gs;}break;
case RDI_RegCodeX86_tr:{result = REGS_RegCodeX86_tr;}break;
case RDI_RegCodeX86_ldtr:{result = REGS_RegCodeX86_ldtr;}break;
case RDI_RegCodeX86_ymm0:{result = REGS_RegCodeX86_ymm0;}break;
case RDI_RegCodeX86_ymm1:{result = REGS_RegCodeX86_ymm1;}break;
case RDI_RegCodeX86_ymm2:{result = REGS_RegCodeX86_ymm2;}break;
case RDI_RegCodeX86_ymm3:{result = REGS_RegCodeX86_ymm3;}break;
case RDI_RegCodeX86_ymm4:{result = REGS_RegCodeX86_ymm4;}break;
case RDI_RegCodeX86_ymm5:{result = REGS_RegCodeX86_ymm5;}break;
case RDI_RegCodeX86_ymm6:{result = REGS_RegCodeX86_ymm6;}break;
case RDI_RegCodeX86_ymm7:{result = REGS_RegCodeX86_ymm7;}break;
}
NotImplemented;
}break;
}
return result;
src/regs/rdi/regs_rdi.mdesk
+2 -10
View File
@@ -22,11 +22,7 @@
`}break;`;
`case Arch_x86:`;
`{`;
`switch(code)`
`{`;
`default:{}break;`;
@expand(REGS_RegTableX86 a) `case REGS_RegCodeX86_$(a.name):{result = RDI_RegCodeX86_$(a.name);}break;`;
`}`;
`NotImplemented;`
`}break;`;
`}`;
`return result;`;
@@ -51,11 +47,7 @@
`}break;`;
`case Arch_x86:`;
`{`;
`switch(code)`
`{`;
`default:{}break;`;
@expand(REGS_RegTableX86 a) `case RDI_RegCodeX86_$(a.name):{result = REGS_RegCodeX86_$(a.name);}break;`;
`}`;
`NotImplemented;`
`}break;`;
`}`;
`return result;`;
src/regs/regs.c
+4 -4
View File
@@ -65,7 +65,7 @@ regs_rip_from_arch_block(Arch arch, void *block)
{
default:{}break;
case Arch_x64:{result = ((REGS_RegBlockX64 *)block)->rip.u64;}break;
case Arch_x86:{result = (U64)((REGS_RegBlockX86 *)block)->eip.u32;}break;
case Arch_x86:{NotImplemented;}break;
}
return result;
}
@@ -78,7 +78,7 @@ regs_rsp_from_arch_block(Arch arch, void *block)
{
default:{}break;
case Arch_x64:{result = ((REGS_RegBlockX64 *)block)->rsp.u64;}break;
case Arch_x86:{result = (U64)((REGS_RegBlockX86 *)block)->esp.u32;}break;
case Arch_x86:{NotImplemented;}break;
}
return result;
}
@@ -90,7 +90,7 @@ regs_arch_block_write_rip(Arch arch, void *block, U64 rip)
{
default:{}break;
case Arch_x64:{((REGS_RegBlockX64 *)block)->rip.u64 = rip;}break;
case Arch_x86:{((REGS_RegBlockX86 *)block)->eip.u32 = (U32)rip;}break;
case Arch_x86:{NotImplemented;}break;
}
}
@@ -101,6 +101,6 @@ regs_arch_block_write_rsp(Arch arch, void *block, U64 rsp)
{
default:{}break;
case Arch_x64:{((REGS_RegBlockX64 *)block)->rsp.u64 = rsp;}break;
case Arch_x86:{((REGS_RegBlockX86 *)block)->esp.u32 = (U32)rsp;}break;
case Arch_x86:{NotImplemented;}break;
}
}
src/regs/regs.mdesk
-172
View File
@@ -122,10 +122,6 @@ REGS_AliasTableX64:
{r13d r13 0 32 Normal}
{r14d r14 0 32 Normal}
{r15d r15 0 32 Normal}
// TODO(allen): figure this one out; visual studio disagrees
{eip rip 0 32 Normal}
{eflags rflags 0 32 Normal}
{ax rax 0 16 Normal}
{cx rcx 0 16 Normal}
@@ -206,114 +202,6 @@ REGS_AliasTableX64:
{mm7 st7 0 64 Vector}
}
////////////////////////////////
//~ rjf: X86 Tables
@table(name size usage)
REGS_RegTableX86:
{
{eax 32 Normal}
{ecx 32 Normal}
{edx 32 Normal}
{ebx 32 Normal}
{esp 32 Normal}
{ebp 32 Normal}
{esi 32 Normal}
{edi 32 Normal}
{fsbase 32 Normal}
{gsbase 32 Normal}
{eflags 32 Normal}
{eip 32 Normal}
{dr0 32 Normal}
{dr1 32 Normal}
{dr2 32 Normal}
{dr3 32 Normal}
{dr4 32 Normal}
{dr5 32 Normal}
{dr6 32 Normal}
{dr7 32 Normal}
// FSave registers
// TODO(allen): I am suspicious of this stuff here.
// Are fpr0-7 and st0-7 actually different things? Visual studio doesn't show
// frp0-7. Not sure if the mm0-7 aliases are setup the right way either.
{st0 80 Normal}
{st1 80 Normal}
{st2 80 Normal}
{st3 80 Normal}
{st4 80 Normal}
{st5 80 Normal}
{st6 80 Normal}
{st7 80 Normal}
{fcw 16 Normal}
{fsw 16 Normal}
{ftw 16 Normal}
{fop 16 Normal}
{fcs 16 Normal}
{fds 16 Normal}
{fip 32 Normal}
{fdp 32 Normal}
{mxcsr 32 Normal}
// TODO(allen): I don't think this is really a "register" - think about this...
{mxcsr_mask 32 Normal}
{ss 16 Normal}
{cs 16 Normal}
{ds 16 Normal}
{es 16 Normal}
{fs 16 Normal}
{gs 16 Normal}
{tr 16 Normal}
{ldtr 16 Normal}
// SIMD REGISTERS
{ymm0 256 Vector}
{ymm1 256 Vector}
{ymm2 256 Vector}
{ymm3 256 Vector}
{ymm4 256 Vector}
{ymm5 256 Vector}
{ymm6 256 Vector}
{ymm7 256 Vector}
}
@table(name base off size usage)
REGS_AliasTableX86:
{
{ax eax 0 16 Normal}
{cx ecx 0 16 Normal}
{bx ebx 0 16 Normal}
{dx edx 0 16 Normal}
{sp esp 0 16 Normal}
{bp ebp 0 16 Normal}
{si esi 0 16 Normal}
{di edi 0 16 Normal}
{ip eip 0 16 Normal}
{ah eax 8 8 Normal}
{ch ecx 8 8 Normal}
{dh edx 8 8 Normal}
{bh ebx 8 8 Normal}
{al eax 0 8 Normal}
{cl ecx 0 8 Normal}
{dl edx 0 8 Normal}
{bl ebx 0 8 Normal}
{bpl ebp 0 8 Normal}
{spl esp 0 8 Normal}
{xmm0 ymm0 0 128 Vector}
{xmm1 ymm1 0 128 Vector}
{xmm2 ymm2 0 128 Vector}
{xmm3 ymm3 0 128 Vector}
{xmm4 ymm4 0 128 Vector}
{xmm5 ymm5 0 128 Vector}
{xmm6 ymm6 0 128 Vector}
{xmm7 ymm7 0 128 Vector}
{mm0 st0 0 64 Vector}
{mm1 st1 0 64 Vector}
{mm2 st2 0 64 Vector}
{mm3 st3 0 64 Vector}
{mm4 st4 0 64 Vector}
{mm5 st5 0 64 Vector}
{mm6 st6 0 64 Vector}
{mm7 st7 0 64 Vector}
}
////////////////////////////////
//~ rjf: Architecture Tables
@@ -321,7 +209,6 @@ REGS_AliasTableX86:
REGS_ArchTable:
{
{X64 x64}
{X86 x86}
}
////////////////////////////////
@@ -383,65 +270,6 @@ regs_g_alias_code_x64_usage_kind_table:
@expand(REGS_AliasTableX64 a) `{REGS_RegCodeX64_$(a.base), $(a.off/8), $(a.size/8)}`,
}
////////////////////////////////
//~ rjf: X86 Generators
@enum REGS_RegCodeX86:
{
NULL,
@expand(REGS_RegTableX86 a) `$(a.name)`,
COUNT,
}
@enum REGS_AliasCodeX86:
{
NULL,
@expand(REGS_AliasTableX86 a) `$(a.name)`,
COUNT,
}
@struct REGS_RegBlockX86:
{
@expand(REGS_RegTableX86 a) `REGS_Reg$(a.size) $(a.name)`,
}
@data(REGS_UsageKind)
regs_g_reg_code_x86_usage_kind_table:
{
`REGS_UsageKind_Normal`;
@expand(REGS_RegTableX86 a) `REGS_UsageKind_$(a.usage)`;
}
@data(REGS_UsageKind) regs_g_alias_code_x86_usage_kind_table:
{
`REGS_UsageKind_Normal`;
@expand(REGS_AliasTableX86 a) `REGS_UsageKind_$(a.usage)`;
}
@data(String8) regs_g_reg_code_x86_string_table:
{
`str8_lit_comp("")`;
@expand(REGS_RegTableX86 a) `str8_lit_comp("$(a.name)")`;
}
@data(String8) regs_g_alias_code_x86_string_table:
{
`str8_lit_comp("")`;
@expand(REGS_AliasTableX86 a) `str8_lit_comp("$(a.name)")`;
}
@data(REGS_Rng) regs_g_reg_code_x86_rng_table:
{
`{0}`;
@expand(REGS_RegTableX86 a) `{(U16)OffsetOf(REGS_RegBlockX86, $(a.name)), $(a.size/8)}`,
}
@data(REGS_Slice) regs_g_alias_code_x86_slice_table:
{
`{0}`;
@expand(REGS_AliasTableX86 a) `{REGS_RegCodeX86_$(a.base), $(a.off/8), $(a.size/8)}`,
}
////////////////////////////////
//~ rjf: Architecture-Dynamic Helper Implementation Generators