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remove x86 register code

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This commit is contained in:
Nikita Smith
2025-12-05 16:39:02 -08:00
parent ce77442d37
commit 8005c31276
23 changed files with 31 additions and 1625 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/regs/generated/regs.meta.c
+3 -312
View File
@@ -10,7 +10,6 @@ switch(arch)
{
default:{}break;
case Arch_x64:{result = sizeof(REGS_RegBlockX64);}break;
case Arch_x86:{result = sizeof(REGS_RegBlockX86);}break;
}
return result;
}
@@ -21,7 +20,6 @@ switch(arch)
{
default:{}break;
case Arch_x64:{result = REGS_RegCodeX64_COUNT;}break;
case Arch_x86:{result = REGS_RegCodeX86_COUNT;}break;
}
return result;
}
@@ -32,7 +30,6 @@ switch(arch)
{
default:{}break;
case Arch_x64:{result = REGS_AliasCodeX64_COUNT;}break;
case Arch_x86:{result = REGS_AliasCodeX86_COUNT;}break;
}
return result;
}
@@ -43,7 +40,6 @@ switch(arch)
{
default:{}break;
case Arch_x64:{result = regs_g_reg_code_x64_string_table;}break;
case Arch_x86:{result = regs_g_reg_code_x86_string_table;}break;
}
return result;
}
@@ -54,7 +50,6 @@ switch(arch)
{
default:{}break;
case Arch_x64:{result = regs_g_alias_code_x64_string_table;}break;
case Arch_x86:{result = regs_g_alias_code_x86_string_table;}break;
}
return result;
}
@@ -65,7 +60,6 @@ switch(arch)
{
default:{}break;
case Arch_x64:{result = regs_g_reg_code_x64_rng_table;}break;
case Arch_x86:{result = regs_g_reg_code_x86_rng_table;}break;
}
return result;
}
@@ -76,7 +70,6 @@ switch(arch)
{
default:{}break;
case Arch_x64:{result = regs_g_alias_code_x64_slice_table;}break;
case Arch_x86:{result = regs_g_alias_code_x86_slice_table;}break;
}
return result;
}
@@ -87,7 +80,6 @@ switch(arch)
{
default:{}break;
case Arch_x64:{result = regs_g_reg_code_x64_usage_kind_table;}break;
case Arch_x86:{result = regs_g_reg_code_x86_usage_kind_table;}break;
}
return result;
}
@@ -98,7 +90,6 @@ switch(arch)
{
default:{}break;
case Arch_x64:{result = regs_g_alias_code_x64_usage_kind_table;}break;
case Arch_x86:{result = regs_g_alias_code_x86_usage_kind_table;}break;
}
return result;
}
@@ -202,7 +193,7 @@ REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
};
REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[96] =
REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[95] =
{
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
@@ -259,7 +250,6 @@ REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
@@ -401,7 +391,7 @@ str8_lit_comp("tr"),
str8_lit_comp("ldtr"),
};
String8 regs_g_alias_code_x64_string_table[96] =
String8 regs_g_alias_code_x64_string_table[95] =
{
str8_lit_comp(""),
str8_lit_comp("eax"),
@@ -420,7 +410,6 @@ str8_lit_comp("r12d"),
str8_lit_comp("r13d"),
str8_lit_comp("r14d"),
str8_lit_comp("r15d"),
str8_lit_comp("eip"),
str8_lit_comp("eflags"),
str8_lit_comp("ax"),
str8_lit_comp("cx"),
@@ -600,7 +589,7 @@ REGS_Rng regs_g_reg_code_x64_rng_table[95] =
{(U16)OffsetOf(REGS_RegBlockX64, ldtr), 2},
};
REGS_Slice regs_g_alias_code_x64_slice_table[96] =
REGS_Slice regs_g_alias_code_x64_slice_table[95] =
{
{0},
{REGS_RegCodeX64_rax, 0, 4},
@@ -619,7 +608,6 @@ REGS_Slice regs_g_alias_code_x64_slice_table[96] =
{REGS_RegCodeX64_r13, 0, 4},
{REGS_RegCodeX64_r14, 0, 4},
{REGS_RegCodeX64_r15, 0, 4},
{REGS_RegCodeX64_rip, 0, 4},
{REGS_RegCodeX64_rflags, 0, 4},
{REGS_RegCodeX64_rax, 0, 2},
{REGS_RegCodeX64_rcx, 0, 2},
@@ -700,302 +688,5 @@ REGS_Slice regs_g_alias_code_x64_slice_table[96] =
{REGS_RegCodeX64_st7, 0, 8},
};
REGS_UsageKind regs_g_reg_code_x86_usage_kind_table[55] =
{
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
};
REGS_UsageKind regs_g_alias_code_x86_usage_kind_table[36] =
{
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
};
String8 regs_g_reg_code_x86_string_table[55] =
{
str8_lit_comp(""),
str8_lit_comp("eax"),
str8_lit_comp("ecx"),
str8_lit_comp("edx"),
str8_lit_comp("ebx"),
str8_lit_comp("esp"),
str8_lit_comp("ebp"),
str8_lit_comp("esi"),
str8_lit_comp("edi"),
str8_lit_comp("fsbase"),
str8_lit_comp("gsbase"),
str8_lit_comp("eflags"),
str8_lit_comp("eip"),
str8_lit_comp("dr0"),
str8_lit_comp("dr1"),
str8_lit_comp("dr2"),
str8_lit_comp("dr3"),
str8_lit_comp("dr4"),
str8_lit_comp("dr5"),
str8_lit_comp("dr6"),
str8_lit_comp("dr7"),
str8_lit_comp("st0"),
str8_lit_comp("st1"),
str8_lit_comp("st2"),
str8_lit_comp("st3"),
str8_lit_comp("st4"),
str8_lit_comp("st5"),
str8_lit_comp("st6"),
str8_lit_comp("st7"),
str8_lit_comp("fcw"),
str8_lit_comp("fsw"),
str8_lit_comp("ftw"),
str8_lit_comp("fop"),
str8_lit_comp("fcs"),
str8_lit_comp("fds"),
str8_lit_comp("fip"),
str8_lit_comp("fdp"),
str8_lit_comp("mxcsr"),
str8_lit_comp("mxcsr_mask"),
str8_lit_comp("ss"),
str8_lit_comp("cs"),
str8_lit_comp("ds"),
str8_lit_comp("es"),
str8_lit_comp("fs"),
str8_lit_comp("gs"),
str8_lit_comp("tr"),
str8_lit_comp("ldtr"),
str8_lit_comp("ymm0"),
str8_lit_comp("ymm1"),
str8_lit_comp("ymm2"),
str8_lit_comp("ymm3"),
str8_lit_comp("ymm4"),
str8_lit_comp("ymm5"),
str8_lit_comp("ymm6"),
str8_lit_comp("ymm7"),
};
String8 regs_g_alias_code_x86_string_table[36] =
{
str8_lit_comp(""),
str8_lit_comp("ax"),
str8_lit_comp("cx"),
str8_lit_comp("bx"),
str8_lit_comp("dx"),
str8_lit_comp("sp"),
str8_lit_comp("bp"),
str8_lit_comp("si"),
str8_lit_comp("di"),
str8_lit_comp("ip"),
str8_lit_comp("ah"),
str8_lit_comp("ch"),
str8_lit_comp("dh"),
str8_lit_comp("bh"),
str8_lit_comp("al"),
str8_lit_comp("cl"),
str8_lit_comp("dl"),
str8_lit_comp("bl"),
str8_lit_comp("bpl"),
str8_lit_comp("spl"),
str8_lit_comp("xmm0"),
str8_lit_comp("xmm1"),
str8_lit_comp("xmm2"),
str8_lit_comp("xmm3"),
str8_lit_comp("xmm4"),
str8_lit_comp("xmm5"),
str8_lit_comp("xmm6"),
str8_lit_comp("xmm7"),
str8_lit_comp("mm0"),
str8_lit_comp("mm1"),
str8_lit_comp("mm2"),
str8_lit_comp("mm3"),
str8_lit_comp("mm4"),
str8_lit_comp("mm5"),
str8_lit_comp("mm6"),
str8_lit_comp("mm7"),
};
REGS_Rng regs_g_reg_code_x86_rng_table[55] =
{
{0},
{(U16)OffsetOf(REGS_RegBlockX86, eax), 4},
{(U16)OffsetOf(REGS_RegBlockX86, ecx), 4},
{(U16)OffsetOf(REGS_RegBlockX86, edx), 4},
{(U16)OffsetOf(REGS_RegBlockX86, ebx), 4},
{(U16)OffsetOf(REGS_RegBlockX86, esp), 4},
{(U16)OffsetOf(REGS_RegBlockX86, ebp), 4},
{(U16)OffsetOf(REGS_RegBlockX86, esi), 4},
{(U16)OffsetOf(REGS_RegBlockX86, edi), 4},
{(U16)OffsetOf(REGS_RegBlockX86, fsbase), 4},
{(U16)OffsetOf(REGS_RegBlockX86, gsbase), 4},
{(U16)OffsetOf(REGS_RegBlockX86, eflags), 4},
{(U16)OffsetOf(REGS_RegBlockX86, eip), 4},
{(U16)OffsetOf(REGS_RegBlockX86, dr0), 4},
{(U16)OffsetOf(REGS_RegBlockX86, dr1), 4},
{(U16)OffsetOf(REGS_RegBlockX86, dr2), 4},
{(U16)OffsetOf(REGS_RegBlockX86, dr3), 4},
{(U16)OffsetOf(REGS_RegBlockX86, dr4), 4},
{(U16)OffsetOf(REGS_RegBlockX86, dr5), 4},
{(U16)OffsetOf(REGS_RegBlockX86, dr6), 4},
{(U16)OffsetOf(REGS_RegBlockX86, dr7), 4},
{(U16)OffsetOf(REGS_RegBlockX86, st0), 10},
{(U16)OffsetOf(REGS_RegBlockX86, st1), 10},
{(U16)OffsetOf(REGS_RegBlockX86, st2), 10},
{(U16)OffsetOf(REGS_RegBlockX86, st3), 10},
{(U16)OffsetOf(REGS_RegBlockX86, st4), 10},
{(U16)OffsetOf(REGS_RegBlockX86, st5), 10},
{(U16)OffsetOf(REGS_RegBlockX86, st6), 10},
{(U16)OffsetOf(REGS_RegBlockX86, st7), 10},
{(U16)OffsetOf(REGS_RegBlockX86, fcw), 2},
{(U16)OffsetOf(REGS_RegBlockX86, fsw), 2},
{(U16)OffsetOf(REGS_RegBlockX86, ftw), 2},
{(U16)OffsetOf(REGS_RegBlockX86, fop), 2},
{(U16)OffsetOf(REGS_RegBlockX86, fcs), 2},
{(U16)OffsetOf(REGS_RegBlockX86, fds), 2},
{(U16)OffsetOf(REGS_RegBlockX86, fip), 4},
{(U16)OffsetOf(REGS_RegBlockX86, fdp), 4},
{(U16)OffsetOf(REGS_RegBlockX86, mxcsr), 4},
{(U16)OffsetOf(REGS_RegBlockX86, mxcsr_mask), 4},
{(U16)OffsetOf(REGS_RegBlockX86, ss), 2},
{(U16)OffsetOf(REGS_RegBlockX86, cs), 2},
{(U16)OffsetOf(REGS_RegBlockX86, ds), 2},
{(U16)OffsetOf(REGS_RegBlockX86, es), 2},
{(U16)OffsetOf(REGS_RegBlockX86, fs), 2},
{(U16)OffsetOf(REGS_RegBlockX86, gs), 2},
{(U16)OffsetOf(REGS_RegBlockX86, tr), 2},
{(U16)OffsetOf(REGS_RegBlockX86, ldtr), 2},
{(U16)OffsetOf(REGS_RegBlockX86, ymm0), 32},
{(U16)OffsetOf(REGS_RegBlockX86, ymm1), 32},
{(U16)OffsetOf(REGS_RegBlockX86, ymm2), 32},
{(U16)OffsetOf(REGS_RegBlockX86, ymm3), 32},
{(U16)OffsetOf(REGS_RegBlockX86, ymm4), 32},
{(U16)OffsetOf(REGS_RegBlockX86, ymm5), 32},
{(U16)OffsetOf(REGS_RegBlockX86, ymm6), 32},
{(U16)OffsetOf(REGS_RegBlockX86, ymm7), 32},
};
REGS_Slice regs_g_alias_code_x86_slice_table[36] =
{
{0},
{REGS_RegCodeX86_eax, 0, 2},
{REGS_RegCodeX86_ecx, 0, 2},
{REGS_RegCodeX86_ebx, 0, 2},
{REGS_RegCodeX86_edx, 0, 2},
{REGS_RegCodeX86_esp, 0, 2},
{REGS_RegCodeX86_ebp, 0, 2},
{REGS_RegCodeX86_esi, 0, 2},
{REGS_RegCodeX86_edi, 0, 2},
{REGS_RegCodeX86_eip, 0, 2},
{REGS_RegCodeX86_eax, 1, 1},
{REGS_RegCodeX86_ecx, 1, 1},
{REGS_RegCodeX86_edx, 1, 1},
{REGS_RegCodeX86_ebx, 1, 1},
{REGS_RegCodeX86_eax, 0, 1},
{REGS_RegCodeX86_ecx, 0, 1},
{REGS_RegCodeX86_edx, 0, 1},
{REGS_RegCodeX86_ebx, 0, 1},
{REGS_RegCodeX86_ebp, 0, 1},
{REGS_RegCodeX86_esp, 0, 1},
{REGS_RegCodeX86_ymm0, 0, 16},
{REGS_RegCodeX86_ymm1, 0, 16},
{REGS_RegCodeX86_ymm2, 0, 16},
{REGS_RegCodeX86_ymm3, 0, 16},
{REGS_RegCodeX86_ymm4, 0, 16},
{REGS_RegCodeX86_ymm5, 0, 16},
{REGS_RegCodeX86_ymm6, 0, 16},
{REGS_RegCodeX86_ymm7, 0, 16},
{REGS_RegCodeX86_st0, 0, 8},
{REGS_RegCodeX86_st1, 0, 8},
{REGS_RegCodeX86_st2, 0, 8},
{REGS_RegCodeX86_st3, 0, 8},
{REGS_RegCodeX86_st4, 0, 8},
{REGS_RegCodeX86_st5, 0, 8},
{REGS_RegCodeX86_st6, 0, 8},
{REGS_RegCodeX86_st7, 0, 8},
};
C_LINKAGE_END
src/regs/generated/regs.meta.h
+3 -170
View File
@@ -125,7 +125,6 @@ REGS_AliasCodeX64_r12d,
REGS_AliasCodeX64_r13d,
REGS_AliasCodeX64_r14d,
REGS_AliasCodeX64_r15d,
REGS_AliasCodeX64_eip,
REGS_AliasCodeX64_eflags,
REGS_AliasCodeX64_ax,
REGS_AliasCodeX64_cx,
@@ -207,107 +206,6 @@ REGS_AliasCodeX64_mm7,
REGS_AliasCodeX64_COUNT,
} REGS_AliasCodeX64;
typedef enum REGS_RegCodeX86
{
REGS_RegCodeX86_NULL,
REGS_RegCodeX86_eax,
REGS_RegCodeX86_ecx,
REGS_RegCodeX86_edx,
REGS_RegCodeX86_ebx,
REGS_RegCodeX86_esp,
REGS_RegCodeX86_ebp,
REGS_RegCodeX86_esi,
REGS_RegCodeX86_edi,
REGS_RegCodeX86_fsbase,
REGS_RegCodeX86_gsbase,
REGS_RegCodeX86_eflags,
REGS_RegCodeX86_eip,
REGS_RegCodeX86_dr0,
REGS_RegCodeX86_dr1,
REGS_RegCodeX86_dr2,
REGS_RegCodeX86_dr3,
REGS_RegCodeX86_dr4,
REGS_RegCodeX86_dr5,
REGS_RegCodeX86_dr6,
REGS_RegCodeX86_dr7,
REGS_RegCodeX86_st0,
REGS_RegCodeX86_st1,
REGS_RegCodeX86_st2,
REGS_RegCodeX86_st3,
REGS_RegCodeX86_st4,
REGS_RegCodeX86_st5,
REGS_RegCodeX86_st6,
REGS_RegCodeX86_st7,
REGS_RegCodeX86_fcw,
REGS_RegCodeX86_fsw,
REGS_RegCodeX86_ftw,
REGS_RegCodeX86_fop,
REGS_RegCodeX86_fcs,
REGS_RegCodeX86_fds,
REGS_RegCodeX86_fip,
REGS_RegCodeX86_fdp,
REGS_RegCodeX86_mxcsr,
REGS_RegCodeX86_mxcsr_mask,
REGS_RegCodeX86_ss,
REGS_RegCodeX86_cs,
REGS_RegCodeX86_ds,
REGS_RegCodeX86_es,
REGS_RegCodeX86_fs,
REGS_RegCodeX86_gs,
REGS_RegCodeX86_tr,
REGS_RegCodeX86_ldtr,
REGS_RegCodeX86_ymm0,
REGS_RegCodeX86_ymm1,
REGS_RegCodeX86_ymm2,
REGS_RegCodeX86_ymm3,
REGS_RegCodeX86_ymm4,
REGS_RegCodeX86_ymm5,
REGS_RegCodeX86_ymm6,
REGS_RegCodeX86_ymm7,
REGS_RegCodeX86_COUNT,
} REGS_RegCodeX86;
typedef enum REGS_AliasCodeX86
{
REGS_AliasCodeX86_NULL,
REGS_AliasCodeX86_ax,
REGS_AliasCodeX86_cx,
REGS_AliasCodeX86_bx,
REGS_AliasCodeX86_dx,
REGS_AliasCodeX86_sp,
REGS_AliasCodeX86_bp,
REGS_AliasCodeX86_si,
REGS_AliasCodeX86_di,
REGS_AliasCodeX86_ip,
REGS_AliasCodeX86_ah,
REGS_AliasCodeX86_ch,
REGS_AliasCodeX86_dh,
REGS_AliasCodeX86_bh,
REGS_AliasCodeX86_al,
REGS_AliasCodeX86_cl,
REGS_AliasCodeX86_dl,
REGS_AliasCodeX86_bl,
REGS_AliasCodeX86_bpl,
REGS_AliasCodeX86_spl,
REGS_AliasCodeX86_xmm0,
REGS_AliasCodeX86_xmm1,
REGS_AliasCodeX86_xmm2,
REGS_AliasCodeX86_xmm3,
REGS_AliasCodeX86_xmm4,
REGS_AliasCodeX86_xmm5,
REGS_AliasCodeX86_xmm6,
REGS_AliasCodeX86_xmm7,
REGS_AliasCodeX86_mm0,
REGS_AliasCodeX86_mm1,
REGS_AliasCodeX86_mm2,
REGS_AliasCodeX86_mm3,
REGS_AliasCodeX86_mm4,
REGS_AliasCodeX86_mm5,
REGS_AliasCodeX86_mm6,
REGS_AliasCodeX86_mm7,
REGS_AliasCodeX86_COUNT,
} REGS_AliasCodeX86;
typedef struct REGS_RegBlockX64 REGS_RegBlockX64;
struct REGS_RegBlockX64
{
@@ -407,78 +305,13 @@ REGS_Reg16 tr;
REGS_Reg16 ldtr;
};
typedef struct REGS_RegBlockX86 REGS_RegBlockX86;
struct REGS_RegBlockX86
{
REGS_Reg32 eax;
REGS_Reg32 ecx;
REGS_Reg32 edx;
REGS_Reg32 ebx;
REGS_Reg32 esp;
REGS_Reg32 ebp;
REGS_Reg32 esi;
REGS_Reg32 edi;
REGS_Reg32 fsbase;
REGS_Reg32 gsbase;
REGS_Reg32 eflags;
REGS_Reg32 eip;
REGS_Reg32 dr0;
REGS_Reg32 dr1;
REGS_Reg32 dr2;
REGS_Reg32 dr3;
REGS_Reg32 dr4;
REGS_Reg32 dr5;
REGS_Reg32 dr6;
REGS_Reg32 dr7;
REGS_Reg80 st0;
REGS_Reg80 st1;
REGS_Reg80 st2;
REGS_Reg80 st3;
REGS_Reg80 st4;
REGS_Reg80 st5;
REGS_Reg80 st6;
REGS_Reg80 st7;
REGS_Reg16 fcw;
REGS_Reg16 fsw;
REGS_Reg16 ftw;
REGS_Reg16 fop;
REGS_Reg16 fcs;
REGS_Reg16 fds;
REGS_Reg32 fip;
REGS_Reg32 fdp;
REGS_Reg32 mxcsr;
REGS_Reg32 mxcsr_mask;
REGS_Reg16 ss;
REGS_Reg16 cs;
REGS_Reg16 ds;
REGS_Reg16 es;
REGS_Reg16 fs;
REGS_Reg16 gs;
REGS_Reg16 tr;
REGS_Reg16 ldtr;
REGS_Reg256 ymm0;
REGS_Reg256 ymm1;
REGS_Reg256 ymm2;
REGS_Reg256 ymm3;
REGS_Reg256 ymm4;
REGS_Reg256 ymm5;
REGS_Reg256 ymm6;
REGS_Reg256 ymm7;
};
C_LINKAGE_BEGIN
extern REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[95];
extern REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[96];
extern REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[95];
extern String8 regs_g_reg_code_x64_string_table[95];
extern String8 regs_g_alias_code_x64_string_table[96];
extern String8 regs_g_alias_code_x64_string_table[95];
extern REGS_Rng regs_g_reg_code_x64_rng_table[95];
extern REGS_Slice regs_g_alias_code_x64_slice_table[96];
extern REGS_UsageKind regs_g_reg_code_x86_usage_kind_table[55];
extern REGS_UsageKind regs_g_alias_code_x86_usage_kind_table[36];
extern String8 regs_g_reg_code_x86_string_table[55];
extern String8 regs_g_alias_code_x86_string_table[36];
extern REGS_Rng regs_g_reg_code_x86_rng_table[55];
extern REGS_Slice regs_g_alias_code_x86_slice_table[36];
extern REGS_Slice regs_g_alias_code_x64_slice_table[95];
C_LINKAGE_END
src/regs/rdi/generated/regs_rdi.meta.c
+2 -116
View File
@@ -112,64 +112,7 @@ case REGS_RegCodeX64_ldtr:{result = RDI_RegCodeX64_ldtr;}break;
}break;
case Arch_x86:
{
switch(code)
{
default:{}break;
case REGS_RegCodeX86_eax:{result = RDI_RegCodeX86_eax;}break;
case REGS_RegCodeX86_ecx:{result = RDI_RegCodeX86_ecx;}break;
case REGS_RegCodeX86_edx:{result = RDI_RegCodeX86_edx;}break;
case REGS_RegCodeX86_ebx:{result = RDI_RegCodeX86_ebx;}break;
case REGS_RegCodeX86_esp:{result = RDI_RegCodeX86_esp;}break;
case REGS_RegCodeX86_ebp:{result = RDI_RegCodeX86_ebp;}break;
case REGS_RegCodeX86_esi:{result = RDI_RegCodeX86_esi;}break;
case REGS_RegCodeX86_edi:{result = RDI_RegCodeX86_edi;}break;
case REGS_RegCodeX86_fsbase:{result = RDI_RegCodeX86_fsbase;}break;
case REGS_RegCodeX86_gsbase:{result = RDI_RegCodeX86_gsbase;}break;
case REGS_RegCodeX86_eflags:{result = RDI_RegCodeX86_eflags;}break;
case REGS_RegCodeX86_eip:{result = RDI_RegCodeX86_eip;}break;
case REGS_RegCodeX86_dr0:{result = RDI_RegCodeX86_dr0;}break;
case REGS_RegCodeX86_dr1:{result = RDI_RegCodeX86_dr1;}break;
case REGS_RegCodeX86_dr2:{result = RDI_RegCodeX86_dr2;}break;
case REGS_RegCodeX86_dr3:{result = RDI_RegCodeX86_dr3;}break;
case REGS_RegCodeX86_dr4:{result = RDI_RegCodeX86_dr4;}break;
case REGS_RegCodeX86_dr5:{result = RDI_RegCodeX86_dr5;}break;
case REGS_RegCodeX86_dr6:{result = RDI_RegCodeX86_dr6;}break;
case REGS_RegCodeX86_dr7:{result = RDI_RegCodeX86_dr7;}break;
case REGS_RegCodeX86_st0:{result = RDI_RegCodeX86_st0;}break;
case REGS_RegCodeX86_st1:{result = RDI_RegCodeX86_st1;}break;
case REGS_RegCodeX86_st2:{result = RDI_RegCodeX86_st2;}break;
case REGS_RegCodeX86_st3:{result = RDI_RegCodeX86_st3;}break;
case REGS_RegCodeX86_st4:{result = RDI_RegCodeX86_st4;}break;
case REGS_RegCodeX86_st5:{result = RDI_RegCodeX86_st5;}break;
case REGS_RegCodeX86_st6:{result = RDI_RegCodeX86_st6;}break;
case REGS_RegCodeX86_st7:{result = RDI_RegCodeX86_st7;}break;
case REGS_RegCodeX86_fcw:{result = RDI_RegCodeX86_fcw;}break;
case REGS_RegCodeX86_fsw:{result = RDI_RegCodeX86_fsw;}break;
case REGS_RegCodeX86_ftw:{result = RDI_RegCodeX86_ftw;}break;
case REGS_RegCodeX86_fop:{result = RDI_RegCodeX86_fop;}break;
case REGS_RegCodeX86_fcs:{result = RDI_RegCodeX86_fcs;}break;
case REGS_RegCodeX86_fds:{result = RDI_RegCodeX86_fds;}break;
case REGS_RegCodeX86_fip:{result = RDI_RegCodeX86_fip;}break;
case REGS_RegCodeX86_fdp:{result = RDI_RegCodeX86_fdp;}break;
case REGS_RegCodeX86_mxcsr:{result = RDI_RegCodeX86_mxcsr;}break;
case REGS_RegCodeX86_mxcsr_mask:{result = RDI_RegCodeX86_mxcsr_mask;}break;
case REGS_RegCodeX86_ss:{result = RDI_RegCodeX86_ss;}break;
case REGS_RegCodeX86_cs:{result = RDI_RegCodeX86_cs;}break;
case REGS_RegCodeX86_ds:{result = RDI_RegCodeX86_ds;}break;
case REGS_RegCodeX86_es:{result = RDI_RegCodeX86_es;}break;
case REGS_RegCodeX86_fs:{result = RDI_RegCodeX86_fs;}break;
case REGS_RegCodeX86_gs:{result = RDI_RegCodeX86_gs;}break;
case REGS_RegCodeX86_tr:{result = RDI_RegCodeX86_tr;}break;
case REGS_RegCodeX86_ldtr:{result = RDI_RegCodeX86_ldtr;}break;
case REGS_RegCodeX86_ymm0:{result = RDI_RegCodeX86_ymm0;}break;
case REGS_RegCodeX86_ymm1:{result = RDI_RegCodeX86_ymm1;}break;
case REGS_RegCodeX86_ymm2:{result = RDI_RegCodeX86_ymm2;}break;
case REGS_RegCodeX86_ymm3:{result = RDI_RegCodeX86_ymm3;}break;
case REGS_RegCodeX86_ymm4:{result = RDI_RegCodeX86_ymm4;}break;
case REGS_RegCodeX86_ymm5:{result = RDI_RegCodeX86_ymm5;}break;
case REGS_RegCodeX86_ymm6:{result = RDI_RegCodeX86_ymm6;}break;
case REGS_RegCodeX86_ymm7:{result = RDI_RegCodeX86_ymm7;}break;
}
NotImplemented;
}break;
}
return result;
@@ -283,64 +226,7 @@ case RDI_RegCodeX64_ldtr:{result = REGS_RegCodeX64_ldtr;}break;
}break;
case Arch_x86:
{
switch(code)
{
default:{}break;
case RDI_RegCodeX86_eax:{result = REGS_RegCodeX86_eax;}break;
case RDI_RegCodeX86_ecx:{result = REGS_RegCodeX86_ecx;}break;
case RDI_RegCodeX86_edx:{result = REGS_RegCodeX86_edx;}break;
case RDI_RegCodeX86_ebx:{result = REGS_RegCodeX86_ebx;}break;
case RDI_RegCodeX86_esp:{result = REGS_RegCodeX86_esp;}break;
case RDI_RegCodeX86_ebp:{result = REGS_RegCodeX86_ebp;}break;
case RDI_RegCodeX86_esi:{result = REGS_RegCodeX86_esi;}break;
case RDI_RegCodeX86_edi:{result = REGS_RegCodeX86_edi;}break;
case RDI_RegCodeX86_fsbase:{result = REGS_RegCodeX86_fsbase;}break;
case RDI_RegCodeX86_gsbase:{result = REGS_RegCodeX86_gsbase;}break;
case RDI_RegCodeX86_eflags:{result = REGS_RegCodeX86_eflags;}break;
case RDI_RegCodeX86_eip:{result = REGS_RegCodeX86_eip;}break;
case RDI_RegCodeX86_dr0:{result = REGS_RegCodeX86_dr0;}break;
case RDI_RegCodeX86_dr1:{result = REGS_RegCodeX86_dr1;}break;
case RDI_RegCodeX86_dr2:{result = REGS_RegCodeX86_dr2;}break;
case RDI_RegCodeX86_dr3:{result = REGS_RegCodeX86_dr3;}break;
case RDI_RegCodeX86_dr4:{result = REGS_RegCodeX86_dr4;}break;
case RDI_RegCodeX86_dr5:{result = REGS_RegCodeX86_dr5;}break;
case RDI_RegCodeX86_dr6:{result = REGS_RegCodeX86_dr6;}break;
case RDI_RegCodeX86_dr7:{result = REGS_RegCodeX86_dr7;}break;
case RDI_RegCodeX86_st0:{result = REGS_RegCodeX86_st0;}break;
case RDI_RegCodeX86_st1:{result = REGS_RegCodeX86_st1;}break;
case RDI_RegCodeX86_st2:{result = REGS_RegCodeX86_st2;}break;
case RDI_RegCodeX86_st3:{result = REGS_RegCodeX86_st3;}break;
case RDI_RegCodeX86_st4:{result = REGS_RegCodeX86_st4;}break;
case RDI_RegCodeX86_st5:{result = REGS_RegCodeX86_st5;}break;
case RDI_RegCodeX86_st6:{result = REGS_RegCodeX86_st6;}break;
case RDI_RegCodeX86_st7:{result = REGS_RegCodeX86_st7;}break;
case RDI_RegCodeX86_fcw:{result = REGS_RegCodeX86_fcw;}break;
case RDI_RegCodeX86_fsw:{result = REGS_RegCodeX86_fsw;}break;
case RDI_RegCodeX86_ftw:{result = REGS_RegCodeX86_ftw;}break;
case RDI_RegCodeX86_fop:{result = REGS_RegCodeX86_fop;}break;
case RDI_RegCodeX86_fcs:{result = REGS_RegCodeX86_fcs;}break;
case RDI_RegCodeX86_fds:{result = REGS_RegCodeX86_fds;}break;
case RDI_RegCodeX86_fip:{result = REGS_RegCodeX86_fip;}break;
case RDI_RegCodeX86_fdp:{result = REGS_RegCodeX86_fdp;}break;
case RDI_RegCodeX86_mxcsr:{result = REGS_RegCodeX86_mxcsr;}break;
case RDI_RegCodeX86_mxcsr_mask:{result = REGS_RegCodeX86_mxcsr_mask;}break;
case RDI_RegCodeX86_ss:{result = REGS_RegCodeX86_ss;}break;
case RDI_RegCodeX86_cs:{result = REGS_RegCodeX86_cs;}break;
case RDI_RegCodeX86_ds:{result = REGS_RegCodeX86_ds;}break;
case RDI_RegCodeX86_es:{result = REGS_RegCodeX86_es;}break;
case RDI_RegCodeX86_fs:{result = REGS_RegCodeX86_fs;}break;
case RDI_RegCodeX86_gs:{result = REGS_RegCodeX86_gs;}break;
case RDI_RegCodeX86_tr:{result = REGS_RegCodeX86_tr;}break;
case RDI_RegCodeX86_ldtr:{result = REGS_RegCodeX86_ldtr;}break;
case RDI_RegCodeX86_ymm0:{result = REGS_RegCodeX86_ymm0;}break;
case RDI_RegCodeX86_ymm1:{result = REGS_RegCodeX86_ymm1;}break;
case RDI_RegCodeX86_ymm2:{result = REGS_RegCodeX86_ymm2;}break;
case RDI_RegCodeX86_ymm3:{result = REGS_RegCodeX86_ymm3;}break;
case RDI_RegCodeX86_ymm4:{result = REGS_RegCodeX86_ymm4;}break;
case RDI_RegCodeX86_ymm5:{result = REGS_RegCodeX86_ymm5;}break;
case RDI_RegCodeX86_ymm6:{result = REGS_RegCodeX86_ymm6;}break;
case RDI_RegCodeX86_ymm7:{result = REGS_RegCodeX86_ymm7;}break;
}
NotImplemented;
}break;
}
return result;
src/regs/rdi/regs_rdi.mdesk
+2 -10
View File
@@ -22,11 +22,7 @@
`}break;`;
`case Arch_x86:`;
`{`;
`switch(code)`
`{`;
`default:{}break;`;
@expand(REGS_RegTableX86 a) `case REGS_RegCodeX86_$(a.name):{result = RDI_RegCodeX86_$(a.name);}break;`;
`}`;
`NotImplemented;`
`}break;`;
`}`;
`return result;`;
@@ -51,11 +47,7 @@
`}break;`;
`case Arch_x86:`;
`{`;
`switch(code)`
`{`;
`default:{}break;`;
@expand(REGS_RegTableX86 a) `case RDI_RegCodeX86_$(a.name):{result = REGS_RegCodeX86_$(a.name);}break;`;
`}`;
`NotImplemented;`
`}break;`;
`}`;
`return result;`;
src/regs/regs.c
+4 -4
View File
@@ -65,7 +65,7 @@ regs_rip_from_arch_block(Arch arch, void *block)
{
default:{}break;
case Arch_x64:{result = ((REGS_RegBlockX64 *)block)->rip.u64;}break;
case Arch_x86:{result = (U64)((REGS_RegBlockX86 *)block)->eip.u32;}break;
case Arch_x86:{NotImplemented;}break;
}
return result;
}
@@ -78,7 +78,7 @@ regs_rsp_from_arch_block(Arch arch, void *block)
{
default:{}break;
case Arch_x64:{result = ((REGS_RegBlockX64 *)block)->rsp.u64;}break;
case Arch_x86:{result = (U64)((REGS_RegBlockX86 *)block)->esp.u32;}break;
case Arch_x86:{NotImplemented;}break;
}
return result;
}
@@ -90,7 +90,7 @@ regs_arch_block_write_rip(Arch arch, void *block, U64 rip)
{
default:{}break;
case Arch_x64:{((REGS_RegBlockX64 *)block)->rip.u64 = rip;}break;
case Arch_x86:{((REGS_RegBlockX86 *)block)->eip.u32 = (U32)rip;}break;
case Arch_x86:{NotImplemented;}break;
}
}
@@ -101,6 +101,6 @@ regs_arch_block_write_rsp(Arch arch, void *block, U64 rsp)
{
default:{}break;
case Arch_x64:{((REGS_RegBlockX64 *)block)->rsp.u64 = rsp;}break;
case Arch_x86:{((REGS_RegBlockX86 *)block)->esp.u32 = (U32)rsp;}break;
case Arch_x86:{NotImplemented;}break;
}
}
src/regs/regs.mdesk
-172
View File
@@ -122,10 +122,6 @@ REGS_AliasTableX64:
{r13d r13 0 32 Normal}
{r14d r14 0 32 Normal}
{r15d r15 0 32 Normal}
// TODO(allen): figure this one out; visual studio disagrees
{eip rip 0 32 Normal}
{eflags rflags 0 32 Normal}
{ax rax 0 16 Normal}
{cx rcx 0 16 Normal}
@@ -206,114 +202,6 @@ REGS_AliasTableX64:
{mm7 st7 0 64 Vector}
}
////////////////////////////////
//~ rjf: X86 Tables
@table(name size usage)
REGS_RegTableX86:
{
{eax 32 Normal}
{ecx 32 Normal}
{edx 32 Normal}
{ebx 32 Normal}
{esp 32 Normal}
{ebp 32 Normal}
{esi 32 Normal}
{edi 32 Normal}
{fsbase 32 Normal}
{gsbase 32 Normal}
{eflags 32 Normal}
{eip 32 Normal}
{dr0 32 Normal}
{dr1 32 Normal}
{dr2 32 Normal}
{dr3 32 Normal}
{dr4 32 Normal}
{dr5 32 Normal}
{dr6 32 Normal}
{dr7 32 Normal}
// FSave registers
// TODO(allen): I am suspicious of this stuff here.
// Are fpr0-7 and st0-7 actually different things? Visual studio doesn't show
// frp0-7. Not sure if the mm0-7 aliases are setup the right way either.
{st0 80 Normal}
{st1 80 Normal}
{st2 80 Normal}
{st3 80 Normal}
{st4 80 Normal}
{st5 80 Normal}
{st6 80 Normal}
{st7 80 Normal}
{fcw 16 Normal}
{fsw 16 Normal}
{ftw 16 Normal}
{fop 16 Normal}
{fcs 16 Normal}
{fds 16 Normal}
{fip 32 Normal}
{fdp 32 Normal}
{mxcsr 32 Normal}
// TODO(allen): I don't think this is really a "register" - think about this...
{mxcsr_mask 32 Normal}
{ss 16 Normal}
{cs 16 Normal}
{ds 16 Normal}
{es 16 Normal}
{fs 16 Normal}
{gs 16 Normal}
{tr 16 Normal}
{ldtr 16 Normal}
// SIMD REGISTERS
{ymm0 256 Vector}
{ymm1 256 Vector}
{ymm2 256 Vector}
{ymm3 256 Vector}
{ymm4 256 Vector}
{ymm5 256 Vector}
{ymm6 256 Vector}
{ymm7 256 Vector}
}
@table(name base off size usage)
REGS_AliasTableX86:
{
{ax eax 0 16 Normal}
{cx ecx 0 16 Normal}
{bx ebx 0 16 Normal}
{dx edx 0 16 Normal}
{sp esp 0 16 Normal}
{bp ebp 0 16 Normal}
{si esi 0 16 Normal}
{di edi 0 16 Normal}
{ip eip 0 16 Normal}
{ah eax 8 8 Normal}
{ch ecx 8 8 Normal}
{dh edx 8 8 Normal}
{bh ebx 8 8 Normal}
{al eax 0 8 Normal}
{cl ecx 0 8 Normal}
{dl edx 0 8 Normal}
{bl ebx 0 8 Normal}
{bpl ebp 0 8 Normal}
{spl esp 0 8 Normal}
{xmm0 ymm0 0 128 Vector}
{xmm1 ymm1 0 128 Vector}
{xmm2 ymm2 0 128 Vector}
{xmm3 ymm3 0 128 Vector}
{xmm4 ymm4 0 128 Vector}
{xmm5 ymm5 0 128 Vector}
{xmm6 ymm6 0 128 Vector}
{xmm7 ymm7 0 128 Vector}
{mm0 st0 0 64 Vector}
{mm1 st1 0 64 Vector}
{mm2 st2 0 64 Vector}
{mm3 st3 0 64 Vector}
{mm4 st4 0 64 Vector}
{mm5 st5 0 64 Vector}
{mm6 st6 0 64 Vector}
{mm7 st7 0 64 Vector}
}
////////////////////////////////
//~ rjf: Architecture Tables
@@ -321,7 +209,6 @@ REGS_AliasTableX86:
REGS_ArchTable:
{
{X64 x64}
{X86 x86}
}
////////////////////////////////
@@ -383,65 +270,6 @@ regs_g_alias_code_x64_usage_kind_table:
@expand(REGS_AliasTableX64 a) `{REGS_RegCodeX64_$(a.base), $(a.off/8), $(a.size/8)}`,
}
////////////////////////////////
//~ rjf: X86 Generators
@enum REGS_RegCodeX86:
{
NULL,
@expand(REGS_RegTableX86 a) `$(a.name)`,
COUNT,
}
@enum REGS_AliasCodeX86:
{
NULL,
@expand(REGS_AliasTableX86 a) `$(a.name)`,
COUNT,
}
@struct REGS_RegBlockX86:
{
@expand(REGS_RegTableX86 a) `REGS_Reg$(a.size) $(a.name)`,
}
@data(REGS_UsageKind)
regs_g_reg_code_x86_usage_kind_table:
{
`REGS_UsageKind_Normal`;
@expand(REGS_RegTableX86 a) `REGS_UsageKind_$(a.usage)`;
}
@data(REGS_UsageKind) regs_g_alias_code_x86_usage_kind_table:
{
`REGS_UsageKind_Normal`;
@expand(REGS_AliasTableX86 a) `REGS_UsageKind_$(a.usage)`;
}
@data(String8) regs_g_reg_code_x86_string_table:
{
`str8_lit_comp("")`;
@expand(REGS_RegTableX86 a) `str8_lit_comp("$(a.name)")`;
}
@data(String8) regs_g_alias_code_x86_string_table:
{
`str8_lit_comp("")`;
@expand(REGS_AliasTableX86 a) `str8_lit_comp("$(a.name)")`;
}
@data(REGS_Rng) regs_g_reg_code_x86_rng_table:
{
`{0}`;
@expand(REGS_RegTableX86 a) `{(U16)OffsetOf(REGS_RegBlockX86, $(a.name)), $(a.size/8)}`,
}
@data(REGS_Slice) regs_g_alias_code_x86_slice_table:
{
`{0}`;
@expand(REGS_AliasTableX86 a) `{REGS_RegCodeX86_$(a.base), $(a.off/8), $(a.size/8)}`,
}
////////////////////////////////
//~ rjf: Architecture-Dynamic Helper Implementation Generators