mirror of
https://github.com/Ed94/pikuma_ps1.git
synced 2026-06-01 18:41:13 -07:00
202 lines
8.4 KiB
ArmAsm
202 lines
8.4 KiB
ArmAsm
.psx
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.create "./build/hellogpu.bin", 0x80010000
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.include "./code/graphics_system/dsl.s"
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; Entry Point of Code
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.org 0x80010000
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; IO PORT
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IO_BASE_ADDR equ 0x1F80 ; IO Ports Memory map base address
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; GPU Registers
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gpio_port0 equ 0x1810 ; 1F801810h-Write GP0: Send GP0 Commands/Packets (Rendering and VRAM Access)
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gpio_port1 equ 0x1814 ; 1F801814h-Write GP1: Send GP1 Commands (Display Control) (and DMA Control)
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; GPU Command Format: [7:8] Command (8-bit), [0:6] Paraemter (24-bit)
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gcmd_offset equ 24
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gp_Reset equ 0x0 << gcmd_offset
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; On: 0x0
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; Off: 0x1
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gp_DisplayEnabled equ (0x03 << gcmd_offset) | 0x0
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gp_DisplayDisabled equ (0x03 << gcmd_offset) | 0x1
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; GP1(08h) - Display mode
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; 0-1 Horizontal Resolution 1 (0=256, 1=320, 2=512, 3=640) ;GPUSTAT.17-18
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; 2 Vertical Resolution (0=240, 1=480, when Bit5=1) ;GPUSTAT.19
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; 3 Video Mode (0=NTSC/60Hz, 1=PAL/50Hz) ;GPUSTAT.20
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; 4 Display Area Color Depth (0=15bit, 1=24bit) ;GPUSTAT.21
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; 5 Vertical Interlace (0=Off, 1=On) ;GPUSTAT.22
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; 6 Horizontal Resolution 2 (0=256/320/512/640, 1=368) ;GPUSTAT.16
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; 7 Flip screen horizontally (0=Off, 1=On, v1 only) ;GPUSTAT.14
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; 8-23 Not used (zero)
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@DisplayMode equ 0x08
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gp_DisplayMode_320x240_15bit_NTSC equ @DisplayMode << gcmd_offset | 0x0 << 7 | 0x0 << 6 | 0x0 << 5 | 0x0 << 4 | 0x0 << 3 | 0x0 << 2 | 0x1
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; GP1(06h) - Horizontal Display range (on Screen)
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; X2 = X1 + pixels * cycles_per_pix
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; 0 - 11 X1 (260h + 0) ; 12bit ; \ counted in video clock units,
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; 12 - 23 X2 (260h + 320 * 8) ; 12bit ; / relative to HSYNC
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gp_HorizontalDisplayRange_3168_608 equ 0x06 << gcmd_offset | 0xC60 << 12 | 0x260
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; GP1(07h) - Vertical Display range (on Screen)
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; 0 - 9 Y1 (NTSC = 88h - (240 / 2), (PAL = A3h - (288 / 2)) ; \ scanline numbers on screen,
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; 10 - 19 Y2 (NTSC = 88h + (240 / 2), (PAL = A3h + (288 / 2)) ; / relative to VSYNC
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; 20 - 23 Not used (zero)
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gp_VerticalDisplayRange_264_24 equ 0x07 << gcmd_offset | 264 << 10 | 24
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;GP0(E1h) - Draw Mode setting (aka "Texpage")
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; 0 - 3 Texture page X Base (N * 64) (ie. in 64-halfword steps) ; GPUSTAT.0-3
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; 4 Texture page Y Base 1 (N * 256) (ie. 0, 256, 512 or 768) ; GPUSTAT.4
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; 5 - 6 Semi-transparency (0 = B / 2 + F / 2, 1 = B + F, 2 = B - F, 3 = B + F / 4) ; GPUSTAT.5-6
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; 7 - 8 Texture page colors (0 = 4 bit, 1 = 8bit, 2 = 15bit, 3 = Reserved) ; GPUSTAT.7-8
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; 9 Dither 24bit to 15bit (0=Off / strip LSBs, 1 = Dither Enabled) ; GPUSTAT.9
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; 10 Drawing to display area (0=Prohibited, 1=Allowed) ; GPUSTAT.10
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; 11 Texture page Y Base 2 (N * 512) (only for 2 MB VRAM) ; GPUSTAT.15
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; 12 Textured Rectangle X-Flip (BIOS does set this bit on power-up...?)
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; 13 Textured Rectangle Y-Flip (BIOS does set it equal to GPUSTAT.13...?)
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; 14 - 23 Not used (should be 0)
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; 24 - 31 Command (E1h)
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gp_ModeSetting_DrawAllowed equ 10
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gp_ModeSetting_DipArea equ 0xE1 << gcmd_offset | 0x1 << gp_ModeSetting_DrawAllowed
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; GP0(E3h) - Set Drawing Area top left (X1,Y1)
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; GP0(E4h) - Set Drawing Area bottom right (X2,Y2)
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; Sets the drawing area corners. The Render commands GP0(20h..7Fh) are automatically clipping any pixels that are outside of this region.
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; 0 - 9 X-coordinate (0..1023)
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; 10 - 18 Y-coordinate (0..511) ; \ on v0 GPU (max 1 MB VRAM)
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; 19 - 23 Not used (zero) ; /
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; 10 - 19 Y-coordinate (0..1023) ; \ on v2 GPU (max 2 MB VRAM)
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; 20 - 23 Not used (zero) ; /
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; 24 - 31 Command (Exh)
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gp_SetArea_TopLeft equ 0xE3 << gcmd_offset
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gp_SetArea_BottomRight equ 0xE4 << gcmd_offset
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; GP0(E5h) - Set Drawing Offset (X,Y)
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; 0-9 X-coordinate (0..1023)
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; 10-18 Y-coordinate (0..511) ;\on v0 GPU (max 1 MB VRAM)
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; 19-23 Not used (zero) ;/
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; 10-19 Y-coordinate (0..1023) ;\on v2 GPU (max 2 MB VRAM)
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; 20-23 Not used (zero) ;/
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; 24-31 Command (Exh)
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gp_SetOffset equ 0xE5 << gcmd_offset
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; GPU Memory Transfer Commands
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; GP0(02h) Fill Vram
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; GP0(02h) - Fill Rectangle in VRAM
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; 1st Color+Command (CcBbGgRrh) ;24bit RGB value (see note)
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; 2nd Top Left Corner (YyyyXxxxh) ;Xpos counted in halfwords, steps of 10h
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; 3rd Width+Height (YsizXsizh) ;Xsiz counted in halfwords, steps of 10h
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; Fills the area in the frame buffer with the value in RGB.
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; Horizontally the filling is done in 16-pixel (32-bytes) units (see below masking/rounding).
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; The "Color" parameter is a 24bit RGB value, however, the actual fill data is 16bit:
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; The hardware automatically converts the 24bit RGB value to 15bit RGB (with bit15=0).
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; Fill is NOT affected by the Mask settings (acts as if Mask.Bit0,1 are both zero).
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gp_RectFillVM equ 0x02 << gcmd_offset
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; GPU Render Polygon Commands
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; When the upper 3 bits of the first GP0 command are set to 1 (001),
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; then the command can be decoded using the following bitfield:
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; bit number value meaning
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; 31-29 001 polygon render
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; 28 1/0 gouraud / flat shading
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; 27 1/0 4 / 3 vertices
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; 26 1/0 textured / untextured
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; 25 1/0 semi-transparent / opaque
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; 24 1/0 raw texture / modulation
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; 23-0 rgb first color value.
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gp_Poly_FirstColor equ 0
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gp_Poly_RawTexture equ 1 << 24
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gp_Poly_SemiTrans equ 1 << 25
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gp_Poly_Textured equ 1 << 26
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gp_Poly_Quad equ 1 << 27
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gp_Poly_Tri equ 0 << 27
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gp_Poly_ShadeFlat equ 0 << 28
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gp_Poly_ShadeGourand equ 1 << 28
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gp_Polygon equ 0x20 << gcmd_offset
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gp_b10_X equ 0
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gp_b10_Y equ 10
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gp_b16_X equ 0
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gp_b16_Y equ 16
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.macro gp_push_pak, port, packet, reg_scratch
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load_imm reg_scratch, packet
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store_word reg_scratch, port
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.endmacro
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.macro gcmd_push, port, cmd, reg_scratch
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load_imm reg_scratch, cmd
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store_word reg_scratch, port
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.endmacro
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Color_RedFF equ 0x0000FF
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Color_PS_GoldenPoppy equ 0x00C3F3
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Color_PS_CelticBlue equ 0x723F00
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Display_Width equ 320
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Display_Height equ 239
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Display_HalfWidth equ 320 / 2
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Display_HalfHeight equ 240 / 2
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main:
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reg_io_offset equ rtmp_0
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load_uimm rtmp_0, IO_BASE_ADDR
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; Setup Display Control
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; 1. GP1: Reset GPU
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load_imm rtmp_1, gp_Reset ; 00 = Reset GPU
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store_word rtmp_1, gpio_port1(reg_io_offset) ; Writing to GP1
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; 2. GP1: Display Enable
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load_imm rtmp_1, gp_DisplayEnabled
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store_word rtmp_1, gpio_port1(reg_io_offset) ; Write to GP1
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; 3. GP1: Dispaly Mode (320x240, 15-bit, NTSC)
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load_imm rtmp_1, gp_DisplayMode_320x240_15bit_NTSC
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store_word rtmp_1, gpio_port1(reg_io_offset) ; Write to GP1
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; 4. GP1: Horizontal Range
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load_imm rtmp_1, gp_HorizontalDisplayRange_3168_608
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store_word rtmp_1, gpio_port1(reg_io_offset)
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; 5. GP1: Vertical Range
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load_imm rtmp_1, gp_VerticalDisplayRange_264_24
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store_word rtmp_1, gpio_port1(reg_io_offset)
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; Setup VRAM Access
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; 1. GP0: Drawing mode settings
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load_imm rtmp_1, gp_ModeSetting_DipArea
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store_word rtmp_1, gpio_port0(reg_io_offset)
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; 2. GP0: Drawing area Top-Left
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load_imm rtmp_1, gp_SetArea_TopLeft | 0 << gp_b10_Y | 0 << gp_b10_X
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store_word rtmp_1, gpio_port0(reg_io_offset)
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; 3. GP0: Drawing area Bottom-Right
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load_imm rtmp_1, gp_SetArea_BottomRight | Display_Height << gp_b10_Y | Display_Width << gp_b10_X
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store_word rtmp_1, gpio_port0(reg_io_offset)
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; 4. GP0: Drawing area offset X & Y
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load_imm rtmp_1, gp_SetOffset | 0 << gp_b10_Y | 0 << gp_b10_X
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store_word rtmp_1, gpio_port0(reg_io_offset)
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; Clear the screen
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; 1. GP0: Fill rectangle on display area
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load_imm rtmp_1, gp_RectFillVM | Color_PS_CelticBlue
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store_word rtmp_1, gpio_port0(reg_io_offset)
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load_imm rtmp_1, 0 << gp_b16_Y | 0 << gp_b16_X
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store_word rtmp_1, gpio_port0(reg_io_offset)
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load_imm rtmp_1, Display_Height << gp_b16_Y | Display_Width << gp_b16_X
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store_word rtmp_1, gpio_port0(reg_io_offset)
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; Draw a flat-shaded triangle
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; 1. GP0: Send packets to GP0 to draw a triangle
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load_imm rtmp_1, gp_Polygon | Color_PS_GoldenPoppy
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store_word rtmp_1, gpio_port0(reg_io_offset)
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load_imm rtmp_1, -100 + Display_HalfHeight << gp_b16_Y | -100 + Display_HalfWidth << gp_b16_X
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store_word rtmp_1, gpio_port0(reg_io_offset)
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load_imm rtmp_1, 20 + Display_HalfHeight << gp_b16_Y | 20 + Display_HalfWidth << gp_b16_X
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store_word rtmp_1, gpio_port0(reg_io_offset)
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load_imm rtmp_1, -50 + Display_HalfHeight << gp_b16_Y | 30 + Display_HalfWidth << gp_b16_X
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store_word rtmp_1, gpio_port0(reg_io_offset)
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idle:
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jump idle :: nop
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.close
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