minor

code/duffle/dsl.h

@@ -37,20 +37,54 @@
 #define FI_           inline   __attribute__((always_inline))      // inline always
 #define NI_           internal __attribute__((noinline))           // inline never
 #define RO_           __attribute__((section(".rodata")))          // Read only data allocation
-#define R_            restrict                                     // pointers are either restricted or volatile and nothing else 
-#define V_            volatile                                     // pointers are either restricted or volatile and nothing else
-#define T_            typeof
+#define T_            typeof                                       // 
 #define T_same(a,b)   _Generic((a), typeof((b)): 1, default: 0)
 
-#define r_(ptr)        C_(T_(ptr[0])*R_, ptr)
-#define v_(ptr)        C_(T_(ptr[0])V_*, ptr)
+#define R_    restrict 
+#define V_    volatile 
+// Fictional, used for intiution.
+#define EUB_  restrict // Execute Unit Bound:    Data is siloed in the ALU Register File. The Load/Store Unit is bypassed. (Route to Execution Unit.  Keep in registers)
+#define ISO_  restrict // Sole-access path:      Isolated Provenance. Alternative to Exu_. Guarantees electrical memory isolation, 
+                       //                        unlocking the compiler’s ability to safely pack data across multiple parallel SIMD lanes (vectorization).
+#define LSU_  volatile // Load/Store Unit Bound: The compiler is forbidden from caching in registers. Forces physical L1 Cache matrix sampling.
+#define LIVE_ volatile // Live External Data:    Alternative to Lsu_ emphasizing the memory is tapped by an external electrical actor.
+
+#define latch_store  /* ~: atomic_store*/         // Blasts voltages from the Store Buffer into the L1 SRAM, physically flipping the cross-coupled inverters to lock the state.
+#define pulse_rfo    /* ~: atomic_xchg*/          // Broadcasts an electrical RFO (Request For Ownership) pulse across the CPU mesh network to invalidate other L1 caches.
+#define tact_acquire /* ~: memory_order_acquire*/ // Clamp. Sends a voltage signal to the instruction decoder to halt the Out-of-Order engine until the load resolves.
+#define tact_release /* ~: memory_order_release*/ // Drain. Forces the Store Buffer flip-flops to completely empty into the L1 cache before proceeding.
+
+// -----------------------------------------------------------------------------
+// Out-of-Order (OoO) Pipeline Modifiers
+// -----------------------------------------------------------------------------
+#define ooo_drift_  __ATOMIC_RELAXED // OoO engine allowed to drift
+#define ooo_anchor_ __ATOMIC_ACQUIRE // Anchor the Load Queue (halt spec lookahead)
+#define ooo_drain_  __ATOMIC_RELEASE // Drain the Store Buffer (force writeback)
+#define ooo_weld_   __ATOMIC_SEQ_CST // Weld pipeline (total order bus lock)
+
+// Latch operations with physical queue modifiers
+#define latch_load_anchor(ptr)       //__atomic_load_n(ptr, ooo_anchor_)
+#define latch_store_drain(ptr, val)  //__atomic_store_n(ptr, val, ooo_drain_)
+#define pulse_xchg_weld(ptr, val)    //__atomic_exchange_n(ptr, val, ooo_weld_)
+//end of: Fictional.
+
+
+// R_ (restrict) establishes an "Eigen" or "Proprius" mapping.
+// Unlike volatile (V_), which assumes the memory can be changed by anything, 
+// R_ tells the compiler that this pointer holds the *sole*, private (idios) 
+// ownership of the memory slice. Writes to this memory are exclusively bound 
+// to this single symbolic mapping for the duration of the scope, guaranteeing 
+// zero aliasing.
+
+#define r_(ptr)        C_(T_(ptr[0])*R_, ptr) // Constrain pointer to restrict
+#define v_(ptr)        C_(T_(ptr[0])V_*, ptr) // 
 #define tr_(type, ptr) C_(type *R_, ptr)
 #define tv_(type, ptr) C_(type V_*, ptr)
 
-#define TypeR_(type)          type *R_ type ## _R
-#define TypeV_(type)          type V_* type ## _V
-#define PtrSet_(type)         TypeR_(type); typedef TypeV_(type)
-#define TSet_(type)           type; typedef PtrSet_(type)
+#define TypeR_(type)   type *R_ type ## _R  // type *restrict type_R
+#define TypeV_(type)   type V_* type ## _V  // type volatile* type_V
+#define PtrSet_(type)  TypeR_(type); typedef TypeV_(type)
+#define TSet_(type)    type; typedef PtrSet_(type)
 
 #define array_len(a)                   (U8)(sizeof(a) / sizeof(typeof((a)[0])))
 #define array_decl(type, ...)          (type[]){__VA_ARGS__}

code/duffle/gte.h

@@ -395,12 +395,17 @@ enum { _C2_OPS_ = 0
  * `base` is the GPR number to bake into the .word constant's `rs` field.
  * These are pure compile-time integers; the C compiler constant-folds
  * them into .word directives. */
+
+enum {
+	GTE_Z_Offset = 4
+};
+
 #define gte_lwc2_v0(base)   enc_cop2_lwc2(gte_in_v0_xy, (base), 0)
-#define gte_lwc2_v0z(base)  enc_cop2_lwc2(gte_in_v0_z,  (base), 4)
+#define gte_lwc2_v0z(base)  enc_cop2_lwc2(gte_in_v0_z,  (base), GTE_Z_Offset)
 #define gte_lwc2_v1(base)   enc_cop2_lwc2(gte_in_v1_xy, (base), 0)
-#define gte_lwc2_v1z(base)  enc_cop2_lwc2(gte_in_v1_z,  (base), 4)
+#define gte_lwc2_v1z(base)  enc_cop2_lwc2(gte_in_v1_z,  (base), GTE_Z_Offset)
 #define gte_lwc2_v2(base)   enc_cop2_lwc2(gte_in_v2_xy, (base), 0)
-#define gte_lwc2_v2z(base)  enc_cop2_lwc2(gte_in_v2_z,  (base), 4)
+#define gte_lwc2_v2z(base)  enc_cop2_lwc2(gte_in_v2_z,  (base), GTE_Z_Offset)
 
 /* gte_load_vN(r_ptr, base) — placeholder-punned lwc2 loaders
  *

code/duffle/mips.h

@@ -57,8 +57,8 @@
 enum {
 /* --- MIPS CPU Registers --- */
 
-	R_0  = R_0_Code,  R_AT = R_AT_Code,   R_V0 = R_V0_Code,   R_V1 = R_V1_Code,
-	R_A0 = R_A0_Code,  R_A1 = R_A1_Code,   R_A2 = R_A2_Code,   R_A3 = R_A3_Code,
+	R_0  = R_0_Code,   R_AT = R_AT_Code,   R_V0 = R_V0_Code,  R_V1 = R_V1_Code,
+	R_A0 = R_A0_Code,  R_A1 = R_A1_Code,   R_A2 = R_A2_Code,  R_A3 = R_A3_Code,
 	R_T0 = R_T0_Code,  R_T1 = R_T1_Code,   R_T2 = R_T2_Code,  R_T3 = R_T3_Code,
 	R_T4 = R_T4_Code,  R_T5 = R_T5_Code,   R_T6 = R_T6_Code,  R_T7 = R_T7_Code,
 	R_S0 = R_S0_Code,  R_S1 = R_S1_Code,   R_S2 = R_S2_Code,  R_S3 = R_S3_Code,

code/gte_hello/hello_gte.c

@@ -247,6 +247,14 @@ void update(PrimitiveArena* pa, U4* ordering_buf)
 
 			// Three independent bases — full register discretion at the call site
 			gte_load_v0(p0, R_T4);
+			/*
+			asm volatile( ".word " "%0" ", %1" : : 
+				"i"(((op_lwc2 & OPCODE_MASK) << OPCODE_SHIFT) | ((R_T4 & REG_MASK) << RS_SHIFT) | ((gte_in_v0_xy & REG_MASK) << RT_SHIFT) | (0            & IMM_MASK)),
+				"i"(((op_lwc2 & OPCODE_MASK) << OPCODE_SHIFT) | ((R_T4 & REG_MASK) << RS_SHIFT) | ((gte_in_v0_z  & REG_MASK) << RT_SHIFT) | (GTE_Z_Offset & IMM_MASK)), 
+				"r"(p0) : 
+				"$2", "$8", "$9", "$31", "memory" 
+			);
+			*/
 			gte_load_v1(p1, R_T5);
 			gte_load_v2(p2, R_T6);
 

scripts/build_psyq.ps1

@@ -379,13 +379,13 @@ function Send-ToEmulator { param(
 # Send-ToEmulator (join-path $path_build 'hello_gte.ps-exe')
 
 # --- Hot Reload via PCSX-Redux Web Server ---
-$exe_path = join-path $path_build 'hello_gte.ps-exe'
-$absolute_path = [System.IO.Path]::GetFullPath($exe_path)
+# $exe_path = join-path $path_build 'hello_gte.ps-exe'
+# $absolute_path = [System.IO.Path]::GetFullPath($exe_path)
 
-# PCSX-Redux expects the file location in the URL query string!
-# We URL-encode the path to ensure backslashes and spaces don't break the HTTP request.
-$encoded_path = [uri]::EscapeDataString($absolute_path)
-$uri = "http://localhost:8080/api/v1/load-exec?path=$encoded_path"
+# PCSX-Redux expects the file location in the URL query string?
+# We URL-encode the path to ensure backslashes and spaces don't break the HTTP request?
+# $encoded_path = [uri]::EscapeDataString($absolute_path)
+# $uri = "http://localhost:8080/api/v1/load-exec?path=$encoded_path"
 
 # Write-Host "Pushing hot-reload to PCSX-Redux..." -ForegroundColor Magenta
 # try {