mirror of
https://github.com/Ed94/pikuma_ps1.git
synced 2026-08-25 02:20:33 +00:00
build_noramlized_v3s4 mostly reviewed.
This commit is contained in:
@@ -37,6 +37,7 @@
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// The 'Yield' sequence for Tape Atoms (mac_yield).
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#define mac_yield(...) \
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load_word(R_AtomJmp, R_TapePtr, 0) \
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LdSlot_ \
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, add_ui_self( R_TapePtr, S_(MipsCode)) \
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, jump_reg( R_AtomJmp) \
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, BdSlot_ nop
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@@ -217,7 +218,7 @@ WORD_COUNT(mac_gte_ld_ir123_v3s4, 3)
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, mac_gte_mv_from_mac123_v3s4(a) \
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GteDelay_ /* Read MAC1/2/3 → a.xyz (overwrites source-A's load targets) */ \
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, mac_shift_aright_v3s4_self(a, 12) /* Right-shift MAC by 12 (S12.20 → S12.0 OuterProduct12) */
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WORD_COUNT(mac_gte_op_cross_v3s4, 16)
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WORD_COUNT(mac_gte_op_cross_v3s4, 13)
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/* atom_dbg_skip */
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#define mac_gte_store_f3(r_primitive_cursor) \
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@@ -291,7 +292,7 @@ WORD_COUNT(mac_gte_sqr_v3s4, 5)
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, shift_aright_var(r_dx, r_dx, r_shift) \
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, shift_aright_var(r_dy, r_dy, r_shift) \
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, shift_aright_var(r_dz, r_dz, r_shift)
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WORD_COUNT(mac_gte_gpf_scale, 12)
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WORD_COUNT(mac_gte_gpf_scale, 13)
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#define mac_trans_mt3s3s4(r_mtx, r_off, r_t0, r_t1, r_t2) \
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load_word( r_t0, r_off, O_(V3_S4,x)) \
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@@ -33,7 +33,7 @@ enum {
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atom_offset_example_atom_proc_skip = _atom_offset_example_atom_proc_skip,
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};
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// --- atom: build_normalize_v3s4 (65 words) ---
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// --- atom: build_normalize_v3s4 (63 words) ---
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#define _atom_offset_aligned_done_srav_path 3
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#define _atom_offset_srav_path_aligned_done 4
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+42
-59
@@ -272,82 +272,65 @@ typedef Struct_(Binds_NormalizeV3S4) {
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U2 dst_offset; /* offset of dst V3_S4 within the BIOS scratchpad */
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};
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typedef Struct_(RegUse_build_normalize_v3s4) {
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Reg src_ptr;
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Reg dst_ptr;
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Reg src_x;
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Reg src_z;
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Reg recip_est;
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Reg norm;
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Reg shift;
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union {
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Reg v_sqr_aligned, dst_offset;
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} t3;
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union { Reg mac2; } t4;
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union { Reg btarget, shift_count, sqrtbl_index, src_offset; } t5;
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union { Reg_(V3_S4) res, src; };
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union { Reg t0, src_ptr, mac2; };
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union { Reg t1, dst_ptr; };
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union { Reg t2, dst_offset, mac1, v_sqr_aligned; };
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union { Reg t3, src_offset, btarget, shift_count, sqrtbl_index; };
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union { Reg t4, mac3, v_sqr_sum, half_shift_tmp, inv_len; };
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union { Reg t5, lzcr, half_shift; };
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};
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/* ─── Full normalize (all 4 stages inline) ───
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* Generic 4-stage GTE normalize (SQR → sum+LZCR → align+sqrtbl → GPF+srav). */
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internal MipsAtom* build_normalize_v3s4(AtomArena_R aa, RegUse_build_normalize_v3s4 r)
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MipsAtom_Proc_(aa, {
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load_half(r.t5.src_offset, R_TapePtr, O_(Binds_NormalizeV3S4, src_offset)),
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load_half(r.t3.dst_offset, R_TapePtr, O_(Binds_NormalizeV3S4, dst_offset)),
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LdSlot_ add_u(r.src_ptr, R_ScratchBase, r.t5.src_offset),
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LdSlot_ add_u(r.dst_ptr, R_ScratchBase, r.t3.dst_offset),
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load_half(r.src_offset, R_TapePtr, O_(Binds_NormalizeV3S4, src_offset)),
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load_half(r.dst_offset, R_TapePtr, O_(Binds_NormalizeV3S4, dst_offset)),
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LdSlot_ add_u(r.src_ptr, R_ScratchBase, r.src_offset),
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LdSlot_ add_u(r.dst_ptr, R_ScratchBase, r.dst_offset),
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LdSlot_ add_ui_self(R_TapePtr, S_(Binds_NormalizeV3S4)),
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/* Load src.x/y/z from r_src_ptr (caller-determined address) into r_src_x / r_recip_est / r_src_z.
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* r_src_x holds src.x throughout stages 1-2; r_recip_est (which is src.y during this phase) is reused as MAC2 in stage 4. */
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mac_load_word_v3(r.src_x, r.recip_est, r.src_z, r.src_ptr, 0),
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mac_load_v3s4(r.src, r.src_ptr, 0),
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/* Stage 1: mtc2 src → IR1/2/3, SQR fires. */
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LdSlot_ mac_gte_sqr_v3s4(r.src_x, r.recip_est, r.src_z, LdSlot_ nop),
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LdSlot_ mac_gte_sqr_v3s4(r.src.x, r.src.y, r.src.z, LdSlot_ nop),
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/* Stage 2: mfc2 MAC1/2/3, sum, mtc2 LZCS. */
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mac_gte_mv_from_data_r_mac123(r.t3.v_sqr_aligned, r.t4.mac2, r.norm), LdSlot_ nop,
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add_u_self( r.norm, r.t3.v_sqr_aligned),
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add_u_self( r.norm, r.t4.mac2),
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gte_mv_to_data_r( r.norm, C2_LZCS), GteDelay_ nop2,
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gte_mv_from_data_r(r.shift, C2_LZCR), GteDelay_ nop,
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/* Stage 2: mfc2 MAC1/2/3, sum, mtc2 LZCS. src_ptr is dead; reuse as mac2. */
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mac_gte_mv_from_data_r_mac123(r.mac1, r.mac2, r.mac3), LdSlot_ nop,
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add_u_self( r.v_sqr_sum, r.mac1),
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add_u_self( r.v_sqr_sum, r.mac2),
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gte_mv_to_data_r( r.v_sqr_sum, C2_LZCS), GteDelay_ nop2,
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gte_mv_from_data_r(r.lzcr, C2_LZCR), GteDelay_ nop,
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/* Stage 3: round LZCR to even, compute half-shift, align |v|² to bit 24.
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* r_norm holds |v|² sum; r_shift holds the LZCR count from mfc2.
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* After the component: r_shift = even(LZCR), r_norm = half-shift, r_t3.v_sqr_aligned = |v|². */
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mac_lzcr_round_even_half_shift(r.shift, r.norm, r.t3.v_sqr_aligned),
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add_si( r.t5.btarget, r.shift, -24),
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branch_lt_zero(r.t5.btarget, atom_offset(aligned_done, srav_path)), BdSlot_ nop, /* bltz → srav_path (LZCR < 24 path) */
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jump_rel(atom_offset(srav_path, aligned_done)), /* b → aligned_done (LZCR >= 24 path) */
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BdSlot_ shift_lleft_var(r.t3.v_sqr_aligned, r.t3.v_sqr_aligned, r.t5.btarget),
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/* Stage 3: even(LZCR), half-shift, align |v|² to bit 24. */
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mac_lzcr_round_even_half_shift(r.lzcr, r.v_sqr_sum, r.v_sqr_aligned),
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add_si( r.btarget, r.lzcr, -24),
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branch_lt_zero(r.btarget, atom_offset(aligned_done, srav_path)), BdSlot_ nop, /* bltz → srav_path (LZCR < 24 path) */
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jump_rel(atom_offset(srav_path, aligned_done)), /* b → aligned_done (LZCR >= 24 path) */
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BdSlot_ shift_lleft_var(r.v_sqr_aligned, r.v_sqr_aligned, r.btarget),
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atom_label(srav_path)
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li_s( r.t5.shift_count, 24),
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sub_s(r.t5.shift_count, r.t5.shift_count, r.shift),
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shift_aright_var(r.t3.v_sqr_aligned, r.t3.v_sqr_aligned, r.t5.shift_count),
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li_s( r.shift_count, 24),
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sub_s(r.shift_count, r.shift_count, r.lzcr),
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shift_aright_var(r.v_sqr_aligned, r.v_sqr_aligned, r.shift_count),
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atom_label(aligned_done)
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// Save the shift count to r_shift before the next 5 instructions overwrite r_norm (the sqrtbl lookup loads 1/|v| into r_norm, which becomes IR0 in stage 4).
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or_u(r.shift, r.norm, 0), /* r_shift ← shift count (preserved through stage 4) */
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add_si( r.t3.v_sqr_aligned, r.t3.v_sqr_aligned, -64), /* r_t3.v_sqr_aligned holds |v|² aligned (top bit at bit 7). */
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shift_lleft(r.t3.v_sqr_aligned, r.t3.v_sqr_aligned, 1),
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mac_load_word_imm(r.t5.sqrtbl_index, & gte_normalize_sqr_tbl), add_u_self(r.t5.sqrtbl_index, r.t3.v_sqr_aligned),
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load_half(r.norm, r.t5.sqrtbl_index, 0), /* r_norm = sqrtbl[aligned-64] = 1/|v| (IR0 in stage 4) */
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or_u(r.half_shift, r.half_shift_tmp, 0),
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add_si( r.v_sqr_aligned, r.v_sqr_aligned, -64),
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shift_lleft(r.v_sqr_aligned, r.v_sqr_aligned, 1),
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mac_load_word_imm(r.sqrtbl_index, & gte_normalize_sqr_tbl), add_u_self(r.sqrtbl_index, r.v_sqr_aligned),
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load_half(r.inv_len, r.sqrtbl_index, 0),
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LdSlot_ nop,
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/* r.src_z holds src.z from the initial load (r.src_z is a dedicated slot,
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* never clobbered between the load at body start and the stage-4 GPF use below).
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* Stage 4: GPF + srav finalize (r_shift = shift count, r_norm = 1/|v|). */
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mac_gte_general_purpose_interopolation(
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r.norm,
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r.src_x, /* IR1 = src.x (preserved in r_tmp — r_mac2_scratch was clobbered to MAC2 in stage 1.5) */
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r.recip_est,
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r.src_z, /* IR3 = src.z (reloaded) */
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r.t4.mac2, r.recip_est, r.src_z,
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GteDelay_ nop,
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GteDelay_ nop
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mac_gte_general_purpose_interopolation(r.inv_len,
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r.src.x, r.src.y, r.src.z,
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r.res.x, r.res.y, r.res.z,
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GteDelay_ load_word(R_AtomJmp, R_TapePtr, 0), LdSlot_ // ac_yield: word 1
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GteDelay_ add_ui_self( R_TapePtr, S_(MipsCode)) // ac_yield: word 2
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),
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/* sra by r_shift = (31-LZCR)/2 (saved before sqrtbl lookup) */
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mac_shift_aright_var_v3_self(r.t4.mac2, r.recip_est, r.src_z, r.shift),
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/* Store result.x/y/z to r_dst_ptr (caller-determined dst address). */
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mac_store_word_v3(r.t4.mac2, r.recip_est, r.src_z, r.dst_ptr, 0),
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mac_shift_aright_var_v3s4_self(r.res, r.half_shift),
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mac_store_v3s4(r.res, r.dst_ptr, 0),
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mac_yield()
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jump_reg(R_AtomJmp), BdSlot_ nop // ac_yield: word 3-4
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// mac_yield()
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})
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/* ─── GTE OP cross product (a × b → out) ───
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@@ -263,7 +263,7 @@ FI_ void tb_scope_run_end(TapeBuilder* tb) { tb_emit(tb,tape_exit); tape_run(tb_
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// The 'Yield' sequence for Tape Atoms (mac_yield).
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atom_dbg_skip MipsAtomComp_(ac_yield) {
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load_word(R_AtomJmp, R_TapePtr, 0),
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load_word(R_AtomJmp, R_TapePtr, 0), LdSlot_
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add_ui_self( R_TapePtr, S_(MipsCode)),
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jump_reg( R_AtomJmp), BdSlot_ nop,
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};
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@@ -151,17 +151,13 @@ internal void compile_init_atoms(void) {
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smem.normalize_v3s4 = build_normalize_v3s4(& ab,
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RegUse_(build_normalize_v3s4) {
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.src_ptr = ralloc(),
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.dst_ptr = ralloc(),
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.recip_est = ralloc(),
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.norm = ralloc(),
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.shift = ralloc(),
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.src_x = ralloc(),
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.src_z = ralloc(),
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// .shift_count = ralloc(), /* dedicated slot for stage-3 → stage-4 shift count */
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.t3 = ralloc(),
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.t4 = ralloc(),
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.t5 = ralloc(),
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.res = ralloc_v3(),
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.t0 = ralloc(),
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.t1 = ralloc(),
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.t2 = ralloc(),
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.t3 = ralloc(),
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.t4 = ralloc(),
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.t5 = ralloc(),
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});
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regfile_reset(& rf);
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