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https://github.com/Ed94/pikuma_ps1.git
synced 2026-08-05 23:28:47 +00:00
drafting
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@@ -81,18 +81,12 @@ atom_dbg_skip MipsAtom_(tape_exit) { jump_reg(rret_addr), nop };
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//TODO(Ed): Do we backup R_S0-7 here? Have it in a heavier tape run as a opt-in? Same with V0-1 and A0-3?
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/* Generalized Tape Engine Runner */
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FI_ void tape_run(Slice_MipsCode tape) { register U4* tape_ptr rgcc(R_TapePtr) = u4_r(tape.ptr); asm volatile(
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// Removed, not needed
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/*add_ui( R_SP, R_SP, -MipsStackAlignment)*/ /* Allocate stack space */
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/*, store_word( R_RA, R_SP, 0)*/ /* Safely backup $ra to the stack */
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asm_words(
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load_word( R_AtomJmp, R_TapePtr, 0) /* Bootstrap the first jump */
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, add_ui_self(R_TapePtr, S_(MipsCode)) /* Advance tape */
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, call_reg( R_AtomJmp) /* jalr $t9 */
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, nop /* Branch delay slot */
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load_word( R_AtomJmp, R_TapePtr, 0) /* Bootstrap the first jump */
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, add_ui_self(R_TapePtr, S_(MipsCode)) /* Advance tape */
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, call_reg( R_AtomJmp) /* jalr $t9 */
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, nop /* Branch delay slot */
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)
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// Removed, not needed
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/*, load_word( R_RA, R_SP, 0)* /* Restore $ra from stack */
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/*, add_ui_self(R_SP, MipsStackAlignment)*/ /* Deallocate stack space */
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asm_rpins, r_use(tape_ptr)
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asm_clobber:
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rlit(R_AT)
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@@ -36,3 +36,108 @@ enum {
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void pad_init(U4 mode) asm("PadInit");
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U4 pad_read(U4 id) asm("PadRead");
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/* ============================================================
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* SIO0 raw controller polling surface (Phase 1 scaffolding)
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* Source of truth: docs/psx-spx/docs/serialinterfacessio.md
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* docs/psx-spx/docs/controllersandmemorycards.md
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* https://github.com/Lameguy64/PSn00bSDK (spi.c)
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* ============================================================ */
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enum {
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/* SIO0 register offsets relative to IOBASE 0xBF800000 */
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pad_SIO_DATA_OFFSET = 0x1040, /* 8-bit data (TX write / RX read) */
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pad_SIO_STAT_OFFSET = 0x1044, /* 16-bit status */
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pad_SIO_MODE_OFFSET = 0x1048, /* 16-bit mode */
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pad_SIO_CTRL_OFFSET = 0x104A, /* 16-bit control */
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pad_SIO_BAUD_OFFSET = 0x104E, /* 16-bit baud */
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/* SIO_CTRL bit flags */
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pad_SIO_CTRL_RESET = 0x0040, /* reset most SIO registers */
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pad_SIO_CTRL_TX_ENABLE = 0x0001, /* TX enable */
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pad_SIO_CTRL_DTR_CS = 0x0002, /* DTR drives /CS on controller */
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pad_SIO_CTRL_ACK = 0x0010, /* acknowledge / clear status */
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pad_SIO_CTRL_DSR_IRQ = 0x1000, /* enable /ACK IRQ (unused; polling) */
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/* SIO_STAT bit flags */
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pad_SIO_STAT_TX_READY = 0x0001,
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pad_SIO_STAT_RX_NOT_EMPTY = 0x0002,
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pad_SIO_STAT_TX_IDLE = 0x0004,
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pad_SIO_STAT_DSR_ACK = 0x0080,
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/* SIO init values (per docs/psx-spx/docs/serialinterfacessio.md) */
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pad_SIO_MODE_INIT = 0x000D, /* MUL1, 8-bit, no parity, idle-high */
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pad_SIO_BAUD_INIT = 0x0088, /* ~250 kHz standard rate */
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pad_SIO_CTRL_CLEANUP = 0x0010, /* raise /CS + clear stale status */
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/* Controller protocol bytes (per docs/psx-spx/docs/controllersandmemorycards.md) */
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pad_PROTO_ADDR = 0x01,
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pad_PROTO_CMD_READ = 0x42,
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pad_PROTO_CMD_ENTERCFG = 0x43,
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pad_PROTO_CMD_SETLED = 0x44,
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pad_PROTO_PREFIX = 0x5A,
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pad_PROTO_PREFIX_QUIRK = 0x00, /* DualShock: Analog-button swap after cfg */
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/* Controller response ID nibble (low 4 bits of ID byte) */
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pad_PROTO_ID_DIGITAL = 0x41,
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pad_PROTO_ID_ANALOG_STK = 0x53,
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pad_PROTO_ID_ANALOG = 0x73,
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pad_PROTO_ID_CONFIG = 0xF3,
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/* Per-state constants */
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pad_SIO_SETTLE_BEFORE_TX = 1000, /* iterations after CTRL=0x0010 */
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pad_SIO_SETTLE_AFTER_TX = 2000, /* iterations after CTRL=port_select */
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pad_SIO_WAIT_BUDGET = 4096, /* max iterations per /ACK or RX wait */
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pad_SIO_CFG_MAX_ATTEMPTS = 3, /* DualShock config retries before reject */
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};
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/* Pad status enum (per-port outcome) */
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typedef Enum_(U4, PadSioStatus) {
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PadSioStatus_Disconnected,
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PadSioStatus_Digital,
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PadSioStatus_AnalogStick,
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PadSioStatus_Analog,
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PadSioStatus_ConfigRejected,
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PadSioStatus_Invalid,
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PadSioStatus_TxTimeout,
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PadSioStatus_RxTimeout,
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PadSioStatus_AckTimeout,
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};
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/* PadState — per-port runtime state */
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typedef Struct_(PadState) {
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PadSioStatus status;
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U4 buttons;
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U1 left_x;
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U1 left_y;
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U1 right_x;
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U1 right_y;
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U4 attempt;
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};
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/* PadSioInit — boot-time C-side pointer table passed into the tape */
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typedef Struct_(PadSioInit) {
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U4 sio_base_addr[2];
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PadState* pad_state_ptr[2];
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};
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/* Register aliases for the new atoms (post-2026-07-10 ABI) */
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#ifndef atom_reg
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#define atom_reg /* atom_reg: opt the preceding enum entry into the DWARF registry */
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#endif
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enum {
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R_PadSioBase = R_T6 atom_reg, /* caller-pinned IO_BASE_ADDR */
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R_PadState = R_T7 atom_reg, /* caller-pinned PadState* */
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R_PadStatus = R_T4 atom_reg, /* scratch for status reads */
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R_PadCountdown = R_T5 atom_reg, /* scratch for countdown budget */
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#define R_PadSioBase_Code R_T6_Code
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#define R_PadState_Code R_T7_Code
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#define R_PadStatus_Code R_T4_Code
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#define R_PadCountdown_Code R_T5_Code
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};
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/* Address of SIO0 block in KSEG1 (the PS1-side uncached mirror) */
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enum {
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pad_IO_KSEG1_BASE = 0xBF800000,
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};
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