mirror of
https://github.com/Ed94/perfaware.git
synced 2026-10-14 09:59:40 -07:00
1148 lines
26 KiB
C
1148 lines
26 KiB
C
#ifdef INTELLISENSE_DIRECTIVES
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# pragma once
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# include "encoder.h"
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#endif
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// =========================================================================================
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// Encoding Table
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//
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// Part 1 target: the instruction cross-section exercised by Computer Enhance listing 0042.
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// Later Part 1 simulation listings use a subset of this table.
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//
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// Fixed opcode bits are kept in binary/signature form;
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// ModR/M /digit selectors use their encoded enumeration values.
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// =========================================================================================
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RO_ global X8616_Encoding x8616_encodings[] =
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{
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// MOV---------------------------------------------------------------------
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/* MOV: 100010 d w | mod reg r/m */ {
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.opcode = {
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.bits = x8616_opcode_mov_rm_r << X8616_OPCODE_DW_PREFIX_SHIFT,
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.mask = X8616_OPCODE_DW_PREFIX_MASK,
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},
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.fields = {
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.d = { X8616_OPCODE_DW_D_SHIFT, 1 },
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.w = { X8616_OPCODE_DW_W_SHIFT, 1 },
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},
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.operands = { x8616_operand_rm, x8616_operand_reg_modrm },
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.op = x8616_op_mov,
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},
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/* MOV imm -> r/m: 1100011 w | mod 000 r/m */ {
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.opcode = {
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.bits = x8616_opcode_mov_rm_i << X8616_OPCODE_W_PREFIX_SHIFT,
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.mask = X8616_OPCODE_W_PREFIX_MASK,
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},
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.mod_rm = {
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.bits = x8616_digit_0 << X8616_MODRM_REG_SHIFT,
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.mask = X8616_MODRM_REG_MASK,
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},
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.fields = {
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.w = { X8616_OPCODE_W_W_SHIFT, 1 },
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},
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.operands = { x8616_operand_rm, x8616_operand_imm },
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.op = x8616_op_mov,
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},
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/* MOV imm -> reg: 1011 w reg */ {
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.opcode = {
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.bits = x8616_opcode_mov_r_i << X8616_OPCODE_WREG_PREFIX_SHIFT,
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.mask = X8616_OPCODE_WREG_PREFIX_MASK,
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},
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.fields = {
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.w = { X8616_OPCODE_WREG_W_SHIFT, 1 },
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.reg = { X8616_OPCODE_WREG_REG_SHIFT, X8616_OPCODE_WREG_REG_WIDTH },
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},
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.operands = { x8616_operand_reg_opcode, x8616_operand_imm },
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.op = x8616_op_mov,
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},
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/* MOV accumulator <-> direct memory: 101000 d w */ {
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.opcode = {
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.bits = x8616_opcode_mov_acc_mem << X8616_OPCODE_DW_PREFIX_SHIFT,
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.mask = X8616_OPCODE_DW_PREFIX_MASK,
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},
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.fields = {
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.d = { X8616_OPCODE_DW_D_SHIFT, 1 },
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.w = { X8616_OPCODE_DW_W_SHIFT, 1 },
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},
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.operands = { x8616_operand_acc, x8616_operand_mem_direct },
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.op = x8616_op_mov,
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},
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/* MOV segment <-> r/m: 100011 d 0 | mod 0 sr r/m */ {
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.opcode = {
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.bits = x8616_opcode_mov_seg_rm << X8616_OPCODE_D0_PREFIX_SHIFT,
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.mask = X8616_OPCODE_D0_PREFIX_MASK,
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},
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.mod_rm = {
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.bits = 0,
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.mask = X8616_MODRM_SEG_FIXED_MASK,
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},
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.fields = {
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.d = { X8616_OPCODE_D0_D_SHIFT, 1 },
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},
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.operands = { x8616_operand_rm, x8616_operand_segment_modrm },
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.width = x8616_width_word,
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.op = x8616_op_mov,
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},
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// Stack / exchange--------------------------------------------------------
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/* PUSH r/m16: 11111111 | mod 110 r/m */ {
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.opcode = {
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.bits = x8616_opcode_group_ff,
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.mask = X8616_OPCODE_MASK,
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},
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.mod_rm = {
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.bits = x8616_ff_push << X8616_MODRM_REG_SHIFT,
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.mask = X8616_MODRM_REG_MASK,
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},
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.operands = { x8616_operand_rm },
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.width = x8616_width_word,
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.op = x8616_op_push,
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},
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/* PUSH reg16: 01010 reg */ {
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.opcode = {
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.bits = x8616_opcode_push_reg << X8616_OPCODE_REG_PREFIX_SHIFT,
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.mask = X8616_OPCODE_REG_PREFIX_MASK,
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},
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.fields = {
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.reg = { X8616_OPCODE_REG_REG_SHIFT, X8616_OPCODE_REG_REG_WIDTH },
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},
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.operands = { x8616_operand_reg_opcode },
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.width = x8616_width_word,
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.op = x8616_op_push,
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},
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/* PUSH segment: 000 sr 110 */ {
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.opcode = {
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.bits = X8616_OPCODE_PUSH_SR_FIXED,
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.mask = X8616_OPCODE_SR_PATTERN_MASK,
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},
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.fields = {
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.sr = { X8616_OPCODE_SR_SHIFT, X8616_OPCODE_SR_WIDTH },
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},
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.operands = { x8616_operand_segment_opcode },
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.width = x8616_width_word,
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.op = x8616_op_push,
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},
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/* POP r/m16: 10001111 | mod 000 r/m */ {
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.opcode = {
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.bits = x8616_opcode_pop_rm,
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.mask = X8616_OPCODE_MASK,
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},
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.mod_rm = {
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.bits = x8616_digit_0 << X8616_MODRM_REG_SHIFT,
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.mask = X8616_MODRM_REG_MASK,
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},
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.operands = { x8616_operand_rm },
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.width = x8616_width_word,
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.op = x8616_op_pop,
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},
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/* POP reg16: 01011 reg */ {
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.opcode = {
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.bits = x8616_opcode_pop_reg << X8616_OPCODE_REG_PREFIX_SHIFT,
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.mask = X8616_OPCODE_REG_PREFIX_MASK,
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},
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.fields = {
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.reg = { X8616_OPCODE_REG_REG_SHIFT, X8616_OPCODE_REG_REG_WIDTH },
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},
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.operands = { x8616_operand_reg_opcode },
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.width = x8616_width_word,
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.op = x8616_op_pop,
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},
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/* POP segment: 000 sr 111 */ {
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.opcode = {
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.bits = X8616_OPCODE_POP_SR_FIXED,
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.mask = X8616_OPCODE_SR_PATTERN_MASK,
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},
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.fields = {
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.sr = { X8616_OPCODE_SR_SHIFT, X8616_OPCODE_SR_WIDTH },
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},
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.operands = { x8616_operand_segment_opcode },
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.width = x8616_width_word,
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.op = x8616_op_pop,
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},
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/* XCHG r/m,reg: 1000011 w | mod reg r/m */ {
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.opcode = {
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.bits = x8616_opcode_xchg_rm_r << X8616_OPCODE_W_PREFIX_SHIFT,
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.mask = X8616_OPCODE_W_PREFIX_MASK,
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},
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.fields = {
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.w = { X8616_OPCODE_W_W_SHIFT, 1 },
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},
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.operands = { x8616_operand_reg_modrm, x8616_operand_rm },
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.op = x8616_op_xchg,
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},
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/* XCHG AX,reg16: 10010 reg (also encodes NOP at reg=AX) */ {
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.opcode = {
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.bits = x8616_opcode_xchg_ax_reg << X8616_OPCODE_REG_PREFIX_SHIFT,
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.mask = X8616_OPCODE_REG_PREFIX_MASK,
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},
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.fields = {
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.reg = { X8616_OPCODE_REG_REG_SHIFT, X8616_OPCODE_REG_REG_WIDTH },
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},
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.operands = { x8616_operand_acc, x8616_operand_reg_opcode },
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.width = x8616_width_word,
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.op = x8616_op_xchg,
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},
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// I/O / address / flags---------------------------------------------------
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/* IN acc,imm8: 1110010 w */ {
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.opcode = {
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.bits = x8616_opcode_in_i << X8616_OPCODE_W_PREFIX_SHIFT,
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.mask = X8616_OPCODE_W_PREFIX_MASK,
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},
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.fields = {
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.w = { X8616_OPCODE_W_W_SHIFT, 1 },
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},
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.operands = { x8616_operand_acc, x8616_operand_imm8 },
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.op = x8616_op_in,
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},
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/* IN acc,DX: 1110110 w */ {
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.opcode = {
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.bits = x8616_opcode_in_dx << X8616_OPCODE_W_PREFIX_SHIFT,
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.mask = X8616_OPCODE_W_PREFIX_MASK,
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},
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.fields = {
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.w = { X8616_OPCODE_W_W_SHIFT, 1 },
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},
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.operands = { x8616_operand_acc, x8616_operand_dx },
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.op = x8616_op_in,
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},
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/* OUT imm8,acc: 1110011 w */ {
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.opcode = {
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.bits = x8616_opcode_out_i << X8616_OPCODE_W_PREFIX_SHIFT,
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.mask = X8616_OPCODE_W_PREFIX_MASK,
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},
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.fields = {
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.w = { X8616_OPCODE_W_W_SHIFT, 1 },
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},
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.operands = { x8616_operand_imm8, x8616_operand_acc },
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.op = x8616_op_out,
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},
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/* OUT DX,acc: 1110111 w */ {
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.opcode = {
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.bits = x8616_opcode_out_dx << X8616_OPCODE_W_PREFIX_SHIFT,
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.mask = X8616_OPCODE_W_PREFIX_MASK,
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},
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.fields = {
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.w = { X8616_OPCODE_W_W_SHIFT, 1 },
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},
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.operands = { x8616_operand_dx, x8616_operand_acc },
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.op = x8616_op_out,
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},
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/* XLAT */ {
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.opcode = {
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.bits = x8616_opcode_xlat,
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.mask = X8616_OPCODE_MASK,
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},
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.op = x8616_op_xlat,
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},
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/* LEA: mod reg r/m */ {
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.opcode = {
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.bits = x8616_opcode_lea,
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.mask = X8616_OPCODE_MASK,
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},
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.operands = { x8616_operand_reg_modrm, x8616_operand_rm },
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.width = x8616_width_word,
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.op = x8616_op_lea,
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},
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/* LDS: mod reg r/m */ {
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.opcode = {
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.bits = x8616_opcode_lds,
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.mask = X8616_OPCODE_MASK,
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},
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.operands = { x8616_operand_reg_modrm, x8616_operand_rm },
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.width = x8616_width_word,
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.op = x8616_op_lds,
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},
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/* LES: mod reg r/m */ {
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.opcode = {
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.bits = x8616_opcode_les,
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.mask = X8616_OPCODE_MASK,
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},
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.operands = { x8616_operand_reg_modrm, x8616_operand_rm },
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.width = x8616_width_word,
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.op = x8616_op_les,
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},
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/* LAHF */ {
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.opcode = {
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.bits = x8616_opcode_lahf,
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.mask = X8616_OPCODE_MASK,
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},
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.op = x8616_op_lahf,
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},
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/* SAHF */ {
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.opcode = {
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.bits = x8616_opcode_sahf,
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.mask = X8616_OPCODE_MASK,
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},
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.op = x8616_op_sahf,
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},
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/* PUSHF */ {
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.opcode = {
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.bits = x8616_opcode_pushf,
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.mask = X8616_OPCODE_MASK,
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},
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.op = x8616_op_pushf,
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},
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/* POPF */ {
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.opcode = {
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.bits = x8616_opcode_popf,
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.mask = X8616_OPCODE_MASK,
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},
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.op = x8616_op_popf,
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},
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// Arithmetic / logical----------------------------------------------------
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// 00 ttt 0 d w | 00 ttt 10 w | 100000 s w /ttt
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/* ALU r/m,reg: 00 ttt 0 d w */ {
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.opcode = {
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.bits = x8616_enc_alu_class(),
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.mask = x8616_field_mask(X8616_OPCODE_ALU_CLASS_SHIFT, X8616_OPCODE_ALU_CLASS_WIDTH)
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| x8616_field_mask(X8616_OPCODE_ALU_BIT2_SHIFT, 1),
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},
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.fields = {
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.alu = { X8616_OPCODE_ALU_TTT_SHIFT, X8616_OPCODE_ALU_TTT_WIDTH },
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.d = { X8616_OPCODE_DW_D_SHIFT, 1 },
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.w = { X8616_OPCODE_DW_W_SHIFT, 1 },
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},
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.operands = { x8616_operand_rm, x8616_operand_reg_modrm },
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.op = x8616_op_invalid,
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},
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/* ALU acc,imm: 00 ttt 10 w */ {
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.opcode = {
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.bits = x8616_enc_alu_class() | (X8616_OPCODE_ALU_ACC_FORM << X8616_OPCODE_ALU_ACC_FORM_SHIFT),
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.mask = x8616_field_mask(X8616_OPCODE_ALU_CLASS_SHIFT, X8616_OPCODE_ALU_CLASS_WIDTH)
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| x8616_field_mask(X8616_OPCODE_ALU_ACC_FORM_SHIFT, 2),
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},
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.fields = {
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.alu = { X8616_OPCODE_ALU_TTT_SHIFT, X8616_OPCODE_ALU_TTT_WIDTH },
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.w = { X8616_OPCODE_W_W_SHIFT, 1 },
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},
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.operands = { x8616_operand_acc, x8616_operand_imm },
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.op = x8616_op_invalid,
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},
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/* ALU imm,r/m: 100000 s w /ttt */ {
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.opcode = {
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.bits = x8616_opcode_alu_rm_i << X8616_OPCODE_SW_PREFIX_SHIFT,
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.mask = X8616_OPCODE_SW_PREFIX_MASK,
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},
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.fields = {
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.alu = { X8616_MODRM_REG_SHIFT, X8616_MODRM_REG_WIDTH },
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.s = { X8616_OPCODE_SW_S_SHIFT, 1 },
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.w = { X8616_OPCODE_SW_W_SHIFT, 1 },
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},
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.operands = { x8616_operand_rm, x8616_operand_imm },
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.op = x8616_op_invalid,
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},
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// INC / DEC / unary / adjust---------------------------------------------
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/* INC r/m: 1111111 w /0 */ {
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.opcode = {
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.bits = x8616_opcode_incdec_rm << X8616_OPCODE_W_PREFIX_SHIFT,
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.mask = X8616_OPCODE_W_PREFIX_MASK,
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},
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.mod_rm = {
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.bits = x8616_inc << X8616_MODRM_REG_SHIFT,
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.mask = X8616_MODRM_REG_MASK,
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},
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.fields = {
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.w = { X8616_OPCODE_W_W_SHIFT, 1 },
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},
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.operands = { x8616_operand_rm },
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.op = x8616_op_inc,
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},
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/* INC reg16: 01000 reg */ {
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.opcode = {
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.bits = x8616_opcode_inc_reg << X8616_OPCODE_REG_PREFIX_SHIFT,
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.mask = X8616_OPCODE_REG_PREFIX_MASK,
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},
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.fields = {
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.reg = { X8616_OPCODE_REG_REG_SHIFT, X8616_OPCODE_REG_REG_WIDTH },
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},
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.operands = { x8616_operand_reg_opcode },
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.width = x8616_width_word,
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.op = x8616_op_inc,
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},
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/* AAA */ {
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.opcode = {
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.bits = x8616_opcode_aaa,
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.mask = X8616_OPCODE_MASK,
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},
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.op = x8616_op_aaa,
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},
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/* DAA */ {
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.opcode = {
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.bits = x8616_opcode_daa,
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.mask = X8616_OPCODE_MASK,
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},
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.op = x8616_op_daa,
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},
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/* DEC r/m: 1111111 w /1 */ {
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.opcode = {
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.bits = x8616_opcode_incdec_rm << X8616_OPCODE_W_PREFIX_SHIFT,
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.mask = X8616_OPCODE_W_PREFIX_MASK,
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},
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.mod_rm = {
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.bits = x8616_dec << X8616_MODRM_REG_SHIFT,
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.mask = X8616_MODRM_REG_MASK,
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},
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.fields = {
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.w = { X8616_OPCODE_W_W_SHIFT, 1 },
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},
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.operands = { x8616_operand_rm },
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.op = x8616_op_dec,
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},
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/* DEC reg16: 01001 reg */ {
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.opcode = {
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.bits = x8616_opcode_dec_reg << X8616_OPCODE_REG_PREFIX_SHIFT,
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.mask = X8616_OPCODE_REG_PREFIX_MASK,
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},
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.fields = {
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.reg = { X8616_OPCODE_REG_REG_SHIFT, X8616_OPCODE_REG_REG_WIDTH },
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},
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.operands = { x8616_operand_reg_opcode },
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.width = x8616_width_word,
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.op = x8616_op_dec,
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},
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/* NEG r/m: 1111011 w /neg */ {
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.opcode = {
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.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
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.mask = X8616_OPCODE_W_PREFIX_MASK,
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},
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.mod_rm = {
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.bits = x8616_g3_neg << X8616_MODRM_REG_SHIFT,
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.mask = X8616_MODRM_REG_MASK,
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},
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.fields = {
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.w = { X8616_OPCODE_W_W_SHIFT, 1 },
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},
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.operands = { x8616_operand_rm },
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.op = x8616_op_neg,
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},
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/* MUL r/m: 1111011 w /mul */ {
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.opcode = {
|
|
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_W_PREFIX_MASK,
|
|
},
|
|
.mod_rm = {
|
|
.bits = x8616_g3_mul << X8616_MODRM_REG_SHIFT,
|
|
.mask = X8616_MODRM_REG_MASK,
|
|
},
|
|
.fields = {
|
|
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
|
|
},
|
|
.operands = { x8616_operand_rm },
|
|
.op = x8616_op_mul,
|
|
},
|
|
|
|
/* IMUL r/m: 1111011 w /imul */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_W_PREFIX_MASK,
|
|
},
|
|
.mod_rm = {
|
|
.bits = x8616_g3_imul << X8616_MODRM_REG_SHIFT,
|
|
.mask = X8616_MODRM_REG_MASK,
|
|
},
|
|
.fields = {
|
|
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
|
|
},
|
|
.operands = { x8616_operand_rm },
|
|
.op = x8616_op_imul,
|
|
},
|
|
|
|
/* DIV r/m: 1111011 w /div */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_W_PREFIX_MASK,
|
|
},
|
|
.mod_rm = {
|
|
.bits = x8616_g3_div << X8616_MODRM_REG_SHIFT,
|
|
.mask = X8616_MODRM_REG_MASK,
|
|
},
|
|
.fields = {
|
|
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
|
|
},
|
|
.operands = { x8616_operand_rm },
|
|
.op = x8616_op_div,
|
|
},
|
|
|
|
/* IDIV r/m: 1111011 w /idiv */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_W_PREFIX_MASK,
|
|
},
|
|
.mod_rm = {
|
|
.bits = x8616_g3_idiv << X8616_MODRM_REG_SHIFT,
|
|
.mask = X8616_MODRM_REG_MASK,
|
|
},
|
|
.fields = {
|
|
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
|
|
},
|
|
.operands = { x8616_operand_rm },
|
|
.op = x8616_op_idiv,
|
|
},
|
|
|
|
/* NOT r/m: 1111011 w /not */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_W_PREFIX_MASK,
|
|
},
|
|
.mod_rm = {
|
|
.bits = x8616_g3_not << X8616_MODRM_REG_SHIFT,
|
|
.mask = X8616_MODRM_REG_MASK,
|
|
},
|
|
.fields = {
|
|
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
|
|
},
|
|
.operands = { x8616_operand_rm },
|
|
.op = x8616_op_not,
|
|
},
|
|
|
|
/* AAS */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_aas,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_aas,
|
|
},
|
|
|
|
/* DAS */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_das,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_das,
|
|
},
|
|
|
|
/* AAM: 11010100 00001010 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_aam,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.post_opcode = {
|
|
.bits = X8616_POST_OPCODE_AAM_AAD,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_aam,
|
|
},
|
|
|
|
/* AAD: 11010101 00001010 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_aad,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.post_opcode = {
|
|
.bits = X8616_POST_OPCODE_AAM_AAD,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_aad,
|
|
},
|
|
|
|
/* CBW */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_cbw,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_cbw,
|
|
},
|
|
|
|
/* CWD */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_cwd,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_cwd,
|
|
},
|
|
|
|
// Shift / rotate / TEST---------------------------------------------------
|
|
|
|
/* ROL r/m,1|CL: 110100 v w */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_shift_rm << X8616_OPCODE_VW_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_VW_PREFIX_MASK,
|
|
},
|
|
.mod_rm = {
|
|
.bits = x8616_rol << X8616_MODRM_REG_SHIFT,
|
|
.mask = X8616_MODRM_REG_MASK,
|
|
},
|
|
.fields = {
|
|
.v = { X8616_OPCODE_VW_V_SHIFT, 1 },
|
|
.w = { X8616_OPCODE_VW_W_SHIFT, 1 },
|
|
},
|
|
.operands = { x8616_operand_rm, x8616_operand_shift_count },
|
|
.op = x8616_op_rol,
|
|
},
|
|
|
|
/* ROR r/m,1|CL: 110100 v w */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_shift_rm << X8616_OPCODE_VW_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_VW_PREFIX_MASK,
|
|
},
|
|
.mod_rm = {
|
|
.bits = x8616_ror << X8616_MODRM_REG_SHIFT,
|
|
.mask = X8616_MODRM_REG_MASK,
|
|
},
|
|
.fields = {
|
|
.v = { X8616_OPCODE_VW_V_SHIFT, 1 },
|
|
.w = { X8616_OPCODE_VW_W_SHIFT, 1 },
|
|
},
|
|
.operands = { x8616_operand_rm, x8616_operand_shift_count },
|
|
.op = x8616_op_ror,
|
|
},
|
|
|
|
/* RCL r/m,1|CL: 110100 v w */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_shift_rm << X8616_OPCODE_VW_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_VW_PREFIX_MASK,
|
|
},
|
|
.mod_rm = {
|
|
.bits = x8616_rcl << X8616_MODRM_REG_SHIFT,
|
|
.mask = X8616_MODRM_REG_MASK,
|
|
},
|
|
.fields = {
|
|
.v = { X8616_OPCODE_VW_V_SHIFT, 1 },
|
|
.w = { X8616_OPCODE_VW_W_SHIFT, 1 },
|
|
},
|
|
.operands = { x8616_operand_rm, x8616_operand_shift_count },
|
|
.op = x8616_op_rcl,
|
|
},
|
|
|
|
/* RCR r/m,1|CL: 110100 v w */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_shift_rm << X8616_OPCODE_VW_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_VW_PREFIX_MASK,
|
|
},
|
|
.mod_rm = {
|
|
.bits = x8616_rcr << X8616_MODRM_REG_SHIFT,
|
|
.mask = X8616_MODRM_REG_MASK,
|
|
},
|
|
.fields = {
|
|
.v = { X8616_OPCODE_VW_V_SHIFT, 1 },
|
|
.w = { X8616_OPCODE_VW_W_SHIFT, 1 },
|
|
},
|
|
.operands = { x8616_operand_rm, x8616_operand_shift_count },
|
|
.op = x8616_op_rcr,
|
|
},
|
|
|
|
/* SHL r/m,1|CL: 110100 v w */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_shift_rm << X8616_OPCODE_VW_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_VW_PREFIX_MASK,
|
|
},
|
|
.mod_rm = {
|
|
.bits = x8616_shl << X8616_MODRM_REG_SHIFT,
|
|
.mask = X8616_MODRM_REG_MASK,
|
|
},
|
|
.fields = {
|
|
.v = { X8616_OPCODE_VW_V_SHIFT, 1 },
|
|
.w = { X8616_OPCODE_VW_W_SHIFT, 1 },
|
|
},
|
|
.operands = { x8616_operand_rm, x8616_operand_shift_count },
|
|
.op = x8616_op_shl,
|
|
},
|
|
|
|
/* SHR r/m,1|CL: 110100 v w */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_shift_rm << X8616_OPCODE_VW_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_VW_PREFIX_MASK,
|
|
},
|
|
.mod_rm = {
|
|
.bits = x8616_shr << X8616_MODRM_REG_SHIFT,
|
|
.mask = X8616_MODRM_REG_MASK,
|
|
},
|
|
.fields = {
|
|
.v = { X8616_OPCODE_VW_V_SHIFT, 1 },
|
|
.w = { X8616_OPCODE_VW_W_SHIFT, 1 },
|
|
},
|
|
.operands = { x8616_operand_rm, x8616_operand_shift_count },
|
|
.op = x8616_op_shr,
|
|
},
|
|
|
|
/* SAR r/m,1|CL: 110100 v w */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_shift_rm << X8616_OPCODE_VW_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_VW_PREFIX_MASK,
|
|
},
|
|
.mod_rm = {
|
|
.bits = x8616_sar << X8616_MODRM_REG_SHIFT,
|
|
.mask = X8616_MODRM_REG_MASK,
|
|
},
|
|
.fields = {
|
|
.v = { X8616_OPCODE_VW_V_SHIFT, 1 },
|
|
.w = { X8616_OPCODE_VW_W_SHIFT, 1 },
|
|
},
|
|
.operands = { x8616_operand_rm, x8616_operand_shift_count },
|
|
.op = x8616_op_sar,
|
|
},
|
|
|
|
/* TEST r/m,reg: 1000010 w */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_test_rm_r << X8616_OPCODE_W_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_W_PREFIX_MASK,
|
|
},
|
|
.fields = {
|
|
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
|
|
},
|
|
.operands = { x8616_operand_rm, x8616_operand_reg_modrm },
|
|
.op = x8616_op_test,
|
|
},
|
|
|
|
/* TEST r/m,imm: 1111011 w /0 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_group3 << X8616_OPCODE_W_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_W_PREFIX_MASK,
|
|
},
|
|
.mod_rm = {
|
|
.bits = x8616_g3_test << X8616_MODRM_REG_SHIFT,
|
|
.mask = X8616_MODRM_REG_MASK,
|
|
},
|
|
.fields = {
|
|
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
|
|
},
|
|
.operands = { x8616_operand_rm, x8616_operand_imm },
|
|
.op = x8616_op_test,
|
|
},
|
|
|
|
/* TEST accumulator,imm: 1010100 w */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_test_acc_i << X8616_OPCODE_W_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_W_PREFIX_MASK,
|
|
},
|
|
.fields = {
|
|
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
|
|
},
|
|
.operands = { x8616_operand_acc, x8616_operand_imm },
|
|
.op = x8616_op_test,
|
|
},
|
|
|
|
// String / prefixes-------------------------------------------------------
|
|
|
|
/* REP/REPNE prefix: 1111001 z */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_rep << X8616_OPCODE_Z_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_Z_PREFIX_MASK,
|
|
},
|
|
.fields = {
|
|
.z = { X8616_OPCODE_Z_Z_SHIFT, 1 },
|
|
},
|
|
.flags = x8616_encoding_prefix,
|
|
.op = x8616_op_rep,
|
|
},
|
|
|
|
/* MOVS: ... w */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_movs << X8616_OPCODE_W_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_W_PREFIX_MASK,
|
|
},
|
|
.fields = {
|
|
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
|
|
},
|
|
.op = x8616_op_movs,
|
|
},
|
|
|
|
/* CMPS: ... w */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_cmps << X8616_OPCODE_W_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_W_PREFIX_MASK,
|
|
},
|
|
.fields = {
|
|
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
|
|
},
|
|
.op = x8616_op_cmps,
|
|
},
|
|
|
|
/* SCAS: ... w */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_scas << X8616_OPCODE_W_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_W_PREFIX_MASK,
|
|
},
|
|
.fields = {
|
|
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
|
|
},
|
|
.op = x8616_op_scas,
|
|
},
|
|
|
|
/* LODS: ... w */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_lods << X8616_OPCODE_W_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_W_PREFIX_MASK,
|
|
},
|
|
.fields = {
|
|
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
|
|
},
|
|
.op = x8616_op_lods,
|
|
},
|
|
|
|
/* STOS: ... w */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_stos << X8616_OPCODE_W_PREFIX_SHIFT,
|
|
.mask = X8616_OPCODE_W_PREFIX_MASK,
|
|
},
|
|
.fields = {
|
|
.w = { X8616_OPCODE_W_W_SHIFT, 1 },
|
|
},
|
|
.op = x8616_op_stos,
|
|
},
|
|
|
|
/* LOCK prefix */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_lock,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.flags = x8616_encoding_prefix,
|
|
.op = x8616_op_lock,
|
|
},
|
|
|
|
/* Segment override: 001 sr 110 */ {
|
|
.opcode = {
|
|
.bits = X8616_OPCODE_SEG_FIXED,
|
|
.mask = X8616_OPCODE_SR_PATTERN_MASK,
|
|
},
|
|
.fields = {
|
|
.sr = { X8616_OPCODE_SR_SHIFT, X8616_OPCODE_SR_WIDTH },
|
|
},
|
|
.flags = x8616_encoding_prefix,
|
|
.op = x8616_op_segment,
|
|
},
|
|
|
|
// Control transfer--------------------------------------------------------
|
|
|
|
/* CALL rel16 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_call_rel16,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.operands = { x8616_operand_rel16 },
|
|
.op = x8616_op_call,
|
|
},
|
|
|
|
/* CALL r/m16: FF /2 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_group_ff,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.mod_rm = {
|
|
.bits = x8616_ff_call_near << X8616_MODRM_REG_SHIFT,
|
|
.mask = X8616_MODRM_REG_MASK,
|
|
},
|
|
.operands = { x8616_operand_rm },
|
|
.width = x8616_width_word,
|
|
.op = x8616_op_call,
|
|
},
|
|
|
|
/* CALL far ptr16:16 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_call_far,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.operands = { x8616_operand_far_ptr },
|
|
.flags = x8616_encoding_far,
|
|
.op = x8616_op_call,
|
|
},
|
|
|
|
/* CALL far r/m16: FF /3 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_group_ff,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.mod_rm = {
|
|
.bits = x8616_ff_call_far << X8616_MODRM_REG_SHIFT,
|
|
.mask = X8616_MODRM_REG_MASK,
|
|
},
|
|
.operands = { x8616_operand_rm },
|
|
.width = x8616_width_word,
|
|
.flags = x8616_encoding_far,
|
|
.op = x8616_op_call,
|
|
},
|
|
|
|
/* JMP rel16 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_jmp_rel16,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.operands = { x8616_operand_rel16 },
|
|
.op = x8616_op_jmp,
|
|
},
|
|
|
|
/* JMP rel8 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_jmp_rel8,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.operands = { x8616_operand_rel8 },
|
|
.op = x8616_op_jmp,
|
|
},
|
|
|
|
/* JMP r/m16: FF /4 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_group_ff,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.mod_rm = {
|
|
.bits = x8616_ff_jmp_near << X8616_MODRM_REG_SHIFT,
|
|
.mask = X8616_MODRM_REG_MASK,
|
|
},
|
|
.operands = { x8616_operand_rm },
|
|
.width = x8616_width_word,
|
|
.op = x8616_op_jmp,
|
|
},
|
|
|
|
/* JMP far ptr16:16 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_jmp_far,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.operands = { x8616_operand_far_ptr },
|
|
.flags = x8616_encoding_far,
|
|
.op = x8616_op_jmp,
|
|
},
|
|
|
|
/* JMP far r/m16: FF /5 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_group_ff,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.mod_rm = {
|
|
.bits = x8616_ff_jmp_far << X8616_MODRM_REG_SHIFT,
|
|
.mask = X8616_MODRM_REG_MASK,
|
|
},
|
|
.operands = { x8616_operand_rm },
|
|
.width = x8616_width_word,
|
|
.flags = x8616_encoding_far,
|
|
.op = x8616_op_jmp,
|
|
},
|
|
|
|
/* RET */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_ret,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_ret,
|
|
},
|
|
|
|
/* RET imm16 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_ret_i,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.operands = { x8616_operand_imm16 },
|
|
.op = x8616_op_ret,
|
|
},
|
|
|
|
/* RETF */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_retf,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_retf,
|
|
},
|
|
|
|
/* RETF imm16 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_retf_i,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.operands = { x8616_operand_imm16 },
|
|
.op = x8616_op_retf,
|
|
},
|
|
|
|
/* Jcc rel8: 0111 cccc */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_jcc << X8616_OPCODE_CC_PREFIX_SHIFT,
|
|
.mask = x8616_stem_mask(X8616_OPCODE_CC_PREFIX_SHIFT),
|
|
},
|
|
.fields = {
|
|
.cc = { X8616_OPCODE_CC_SHIFT, X8616_OPCODE_CC_WIDTH },
|
|
},
|
|
.operands = { x8616_operand_rel8 },
|
|
.op = x8616_op_invalid,
|
|
},
|
|
|
|
|
|
/* LOOPNZ rel8 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_loopnz,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.operands = { x8616_operand_rel8 },
|
|
.op = x8616_op_loopnz,
|
|
},
|
|
|
|
/* LOOPZ rel8 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_loopz,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.operands = { x8616_operand_rel8 },
|
|
.op = x8616_op_loopz,
|
|
},
|
|
|
|
/* LOOP rel8 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_loop,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.operands = { x8616_operand_rel8 },
|
|
.op = x8616_op_loop,
|
|
},
|
|
|
|
/* JCXZ rel8 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_jcxz,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.operands = { x8616_operand_rel8 },
|
|
.op = x8616_op_jcxz,
|
|
},
|
|
|
|
// Interrupt / machine control--------------------------------------------
|
|
|
|
/* INT imm8 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_int,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.operands = { x8616_operand_imm8 },
|
|
.op = x8616_op_int,
|
|
},
|
|
|
|
/* INT3 */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_int3,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_int3,
|
|
},
|
|
|
|
/* INTO */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_into,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_into,
|
|
},
|
|
|
|
/* IRET */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_iret,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_iret,
|
|
},
|
|
|
|
/* CLC */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_clc,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_clc,
|
|
},
|
|
|
|
/* CMC */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_cmc,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_cmc,
|
|
},
|
|
|
|
/* STC */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_stc,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_stc,
|
|
},
|
|
|
|
/* CLD */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_cld,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_cld,
|
|
},
|
|
|
|
/* STD */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_std,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_std,
|
|
},
|
|
|
|
/* CLI */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_cli,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_cli,
|
|
},
|
|
|
|
/* STI */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_sti,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_sti,
|
|
},
|
|
|
|
/* HLT */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_hlt,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_hlt,
|
|
},
|
|
|
|
/* WAIT */ {
|
|
.opcode = {
|
|
.bits = x8616_opcode_wait,
|
|
.mask = X8616_OPCODE_MASK,
|
|
},
|
|
.op = x8616_op_wait,
|
|
},
|
|
|
|
};
|
|
|
|
enum {
|
|
X8616_ENCODING_COUNT = S_(x8616_encodings) / S_(x8616_encodings[0]),
|
|
};
|