5-post thread, 0 media, July 2026. SAR (signed shift-right) trick:
HW uses only 5|6 LSBs of shift-by so mixed-use control words don't
need MSB masking - saves an instruction. Working through a single
uber-instruction interpreted language for code generation: never
misses the instruction cache, executes fully out of micro-op cache,
fully data driven, direct map 64K entry symbol table. Borrows from
SIMD GPU programming: instead of branching/predicating to avoid
stores, just store to a discarded area (negative offset on GPU,
designated trash address on CPU). No exit condition logic in infinite
loop - exit via storing to set address, external watchdog polls at
some sleep frequency. SAR trick can grab 3 values: SF (MSB), CF
(shift-out bit -1), and output - SF+CF for CMOVcc, output for next
shift. Sibling to the 2079746130309415185 micro macro-forth and
2078349730204078527 8-byte aligned Forth word threads - the
uber-instruction version of the runtime-language work.
