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docs(twitter): add 1687062786273062912 corpus (NOTimothyLottes SPC 8-deep swap BO + 3-thread load)
5-post thread, 2 JPGs, 2023-08-03. SPC: 8-deep swap all aliasing same BO (image) fixes Game Mode crash with external display. Pipelined load: 2 ms to black screen; 460 ms to allocate 4 GiB GTT video RAM; 558 ms to copy 256 MiB cart from page cache to USWC (page faults), all in parallel. Cold-launch worst case (cache cleared): 1.5 sec to read 256 MiB from stock SSD; no compile after this, 'literally in game at this point.' 3-thread load: (1.) X11 then spin present/ keyboard, (2.) AMDgpu device open + SDMA after CART read then dispatch, (3.) CART disk->USWC GTT read(). SSD needs linear reads to be fast so don't manually thread read(). Sibling to SPC project intro (1687257354490818561).
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title: "SPC: Using 8 deep swap all aliasing same BO (image) fixes Game Mode crash with e"
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author: "NOTimothyLottes"
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handle: "@NOTimothyLottes"
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post_url: "https://x.com/NOTimothyLottes/status/1687062786273062912"
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post_id: "1687062786273062912"
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timestamp: "2023-08-03 11:28:07"
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post_count: 5
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reply_count: 1
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repost_count: 1
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like_count: 4
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view_count: 654
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# @NOTimothyLottes — SPC: Using 8 deep swap all aliasing same BO (image) fixes Game Mode crash with e
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## Post 1 (2023-08-03 11:28:07)
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SPC: Using 8 deep swap all aliasing same BO (image) fixes Game Mode crash with external display. Pipelined load gets to black screen in 2 ms. Takes 460 ms to allocate 4 GiB GTT video ram, 558 ms to copy 256 MiB cart from page cache to USWC (page faults), all in parallel.
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## Post 2 (2023-08-03 11:40:20) — reply to Post 1
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Clearing page cache to simulate a cold launch: Takes 1.5 sec to read 256 MiB from the stock SSD. This is worst case load time in desktop mode. Won't be any compile/etc after this. So literally in game at this point. Speed of light. This is how it is done.
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## Post 3 (2023-08-03 11:41:23) — reply to Post 2
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Forgot the timing capture ... Load from SSD.
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## Post 4 (2023-08-03 11:50:33) — reply to Post 3
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There are only 3 threads on load: (1.) to open X11 then spin doing present/keyboard, (2.) to open the AMDgpu device, SDMA copy after CART read, and then eventually spin doing dispatchs, (3.) one to load the CART from disk to mapped USWC GTT via read().
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## Post 5 (2023-08-03 11:53:14) — reply to Post 4
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Something I don't know: does read() since it's kernel- side automatically get some multi-core parallelism? Not a good idea to manually thread the read() because SSD needs linear reads to be fast. Not possible to know if the reads are page cache hits in advance either ...
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