mirror of
https://github.com/Ed94/bare_x86.git
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350 lines
12 KiB
ArmAsm
350 lines
12 KiB
ArmAsm
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;=============================================================================================================
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;=============================================================================================================
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;=============================================================================================================
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; AAL - Assembly Abstraction layer
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; x86-64
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; Provides a suite of docs, functionatliy, macros, etc.
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;
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; Made while learning x86
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; Edward R. Gonzalez
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;=============================================================================================================
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;=============================================================================================================
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;=============================================================================================================
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;
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; See
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; https://en.wikibooks.org/wiki/X86_Assembly/16,_32,_and_64_Bits
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; https://wiki.osdev.org/X86-64
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; http://www.ctyme.com/rbrown.htm
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; https://github.com/Captainarash/The_Holy_Book_of_X86/blob/master/book_vol_1.txt
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;=============================================================================================================
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; Calling Convention
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;=============================================================================================================
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; Calling convention - Caller/Callee Saved Registers
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;
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; Caller rules: When calling a function the registers
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; RAX, RCX, RDX, R8, R9, R10, R11 are considered volatile and must be saved into the stack
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; by the caller, if it relies on them
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; (unless otherwise safety-provable by analysis such as whole program optimization).
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;
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; Callee rules:
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; RBX, RBP, RDI, RSI, RSP, R12, R13, R14, and R15
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; are considered nonvolatile and must be saved and restored from the stack by the callee if it modify them.
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;=============================================================================================================
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; END OF CALLING CONVENTION
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;=============================================================================================================
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;=============================================================================================================
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; Register Documentation
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;=============================================================================================================
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; General Purpose
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; 8 High Low 16 32 64 Intended Purpose
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; AH AL AX EAX RAX Accumulator
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; BH BL BX EBX RBX Base
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; CH CL CX ECX RCX Counter
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; DH DL DX EDX RDX Data (Used to extend the A register)
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; SIL SI ESI RSI Source index for strings ops
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; DIL DI EDI RDI Destination index for string operations
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; SPL SPL ESP RSP Stack pointer
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; BPL BP EBP RBP Base pointer (meant for stack frames)
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; R8B R8W R8D R8 General Purpose (and below)
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; R9B R9W R9D R9
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; R10B R10W R10D R10
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; R11B R11W R11D R11
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; R12B R12W R12D R12
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; R13B R13W R13D R13
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; R14B R14W R14D R14
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; R15B R15W R15D R15
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; Instruction Pointer
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; 16 32 64
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; IP EIP RIP
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; Segment
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; 16
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; CS Code Segment
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; DS Data Segment
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; SS Stack Segment
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; ES Extra Segment
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; FS General-purpose
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; GS General-purpose
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; RFLAGS
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; Bit(s) Label Description
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; 0 CF Carry Flag
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; 1 1 Reserved
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; 2 PF Parity Flag
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; 3 0 Reserved
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; 4 AF Auxiliary Carry Flag
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; 5 0 Reserved
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; 6 ZF Zero Flag
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; 7 SF Sign Flag
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; 8 TF Trap Flag
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; 9 IF Interrupt Enable Flag
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; 10 DF Direction Flag
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; 11 OF Overflow Flag
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; 12-13 IOPL I/O Privilege Level
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; 14 NT Nested Task
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; 15 0 Reserved
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; 16 RF Resume Flag
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; 17 VM Virtual-8086 Mode
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; 18 AC Alignment Check / Access Control
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; 19 VIF Virtual Interrupt Flag
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; 20 VIP Virtual Interrupt Pending
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; 21 ID ID Flag
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; 22-63 0 Reserved
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; Control
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; CR0
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; Bit(s) Label Description
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; 0 PE Protected Mode Enable
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; 1 MP Monitor Co-Processor
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; 2 EM Emulation
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; 3 TS Task Switched
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; 4 ET Extension Type
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; 5 NE Numeric Error
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; 6-15 0 Reserved
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; 16 WP Write Protect
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; 17 0 Reserved
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; 18 AM Alignment Mask
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; 19-28 0 Reserved
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; 29 NW Not-Write Through
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; 30 CD Cache Disable
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; 31 PG Paging
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; 32-63 0 Reserved
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; CR2
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; Contains the linear (virtual) address which triggered a page fault, available in the page fault's interrupt handler.
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;
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; CR3
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; Bit(s) Label Description Condition
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; 0-11 0-2 0 Reserved CR4.PCIDE = 0
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; 3 PWT Page-Level Write Through
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; 5 PCD Page-Level Cache Disable
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; 5-11 0 Reserved
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; 0-11 PCID CR4.PCIDE = 1
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; 12-63 Physical Base Address of the PML4
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;
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; Note that this must be page aligned
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;
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; CR4
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; Bit(s) Label Description
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; 0 VME Virtual-8086 Mode Extensions
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; 1 PVI Protected Mode Virtual Interrupts
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; 2 TSD Time Stamp enabled only in ring 0
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; 3 DE Debugging Extensions
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; 4 PSE Page Size Extension
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; 5 PAE Physical Address Extension
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; 6 MCE Machine Check Exception
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; 7 PGE Page Global Enable
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; 8 PCE Performance Monitoring Counter Enable
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; 9 OSFXSR OS support for fxsave and fxrstor instructions
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; 10 OSXMMEXCPT OS Support for unmasked simd floating point exceptions
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; 11 UMIP User-Mode Instruction Prevention (SGDT, SIDT, SLDT, SMSW, and STR are disabled in user mode)
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; 12 0 Reserved
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; 13 VMXE Virtual Machine Extensions Enable
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; 14 SMXE Safer Mode Extensions Enable
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; 15 0 Reserved
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; 17 PCIDE PCID Enable
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; 18 OSXSAVE XSAVE And Processor Extended States Enable
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; 19 0 Reserved
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; 20 SMEP Supervisor Mode Executions Protection Enable
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; 21 SMAP Supervisor Mode Access Protection Enable
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; 22 PKE Enable protection keys for user-mode pages
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; 23 CET Enable Control-flow Enforcement Technology
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; 24 PKS Enable protection keys for supervisor-mode pages
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; 25-63 0 Reserved
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; CR8
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; CR8 is a new register accessible in 64-bit mode using the REX prefix.
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; CR8 is used to prioritize external interrupts and is referred to as the task-priority register (TPR).
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;
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; The AMD64 architecture allows software to define up to 15 external interrupt-priority classes.
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; Priority classes are numbered from 1 to 15, with priority-class 1 being the lowest and priority-class 15 the highest.
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; CR8 uses the four low-order bits for specifying a task priority and the remaining 60 bits are reserved and must be written with zeros.
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;
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; System software can use the TPR register to temporarily block low-priority interrupts from interrupting a high-priority task.
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; This is accomplished by loading TPR with a value corresponding to the highest-priority interrupt that is to be blocked.
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; For example, loading TPR with a value of 9 (1001b) blocks all interrupts with a priority class of 9 or less,
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; while allowing all interrupts with a priority class of 10 or more to be recognized.
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; Loading TPR with 0 enables all external interrupts. Loading TPR with 15 (1111b) disables all external interrupts.
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;
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; The TPR is cleared to 0 on reset.
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; Bit Purpose
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; 0-3 Priority
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; 4-63 Reserved
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; CR1, CR5-7, CR9-15
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; Reserved, the cpu will throw a #ud exeption when trying to access them.
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;
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; CR1, CR5-7, CR9-15
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; Reserved, the cpu will throw a #ud exeption when trying to access them.
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;
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; MSRs
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;
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; IA32_EFER
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; Extended Feature Enable Register (EFER) is a model-specific register added in the AMD K6 processor,
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; to allow enabling the SYSCALL/SYSRET instruction, and later for entering and exiting long mode.
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; This register becomes architectural in AMD64 and has been adopted by Intel. Its MSR number is 0xC0000080.
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;
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; Bit(s) Label Description
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; 0 SCE System Call Extensions
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; 1-7 0 Reserved
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; 8 LME Long Mode Enable
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; 10 LMA Long Mode Active
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; 11 NXE No-Execute Enable
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; 12 SVME Secure Virtual Machine Enable
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; 13 LMSLE Long Mode Segment Limit Enable
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; 14 FFXSR Fast FXSAVE/FXRSTOR
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; 15 TCE Translation Cache Extension
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; 16-63 0 Reserved
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;
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; FS.base, GS.base
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;
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; MSRs with the addresses 0xC0000100 (for FS) and 0xC0000101 (for GS) contain the base addresses of the FS and GS segment registers.
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; These are commonly used for thread-pointers in user code and CPU-local pointers in kernel code. Safe to contain anything,
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; since use of a segment does not confer additional privileges to user code.
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;
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; In newer CPUs, these can also be written with WRFSBASE and WRGSBASE instructions at any privilege level.
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;
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; KernelGSBase
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; MSR with the address 0xC0000102.
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; Is basically a buffer that gets exchanged with GS.base after a swapgs instruction.
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; Usually used to seperate kernel and user use of the GS register.
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;
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; Debug Registers
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;
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; DR0 - DR3
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; Contain linear addresses of up to 4 breakpoints. If paging is enabled, they are translated to physical addresses.
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; DR6
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; It permits the debugger to determine which debug conditions have occured.
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; When an enabled debug exception is enabled, low order bits 0-3 are set before entering debug exception handler.
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; DR7
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; Bit Description
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; 0 Local DR0 Breakpoint
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; 1 Global DR0 Breakpoint
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; 2 Local DR1 Breakpoint
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; 3 Global DR1 Breakpoint
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; 4 Local DR2 Breakpoint
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; 5 Global DR2 Breakpoint
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; 6 Local DR3 Breakpoint
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; 7 Global DR3 Breakpoint
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; 16-17 Conditions for DR0
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; 18-19 Size of DR0 Breakpoint
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; 20-21 Conditions for DR1
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; 22-23 Size of DR1 Breakpoint
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; 24-25 Conditions for DR2
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; 26-27 Size of DR2 Breakpoint
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; 28-29 Conditions for DR3
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; 30-31 Size of DR3 Breakpoint
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;
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; A local breakpoint bit deactivates on hardware task switches, while a global does not.
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; 00b condition means execution break, 01b means a write watchpoint, and 11b means an R/W watchpoint.
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; 10b is reserved for I/O R/W (unsupported).
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;
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; Test Registers
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; Name Description
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; TR3 - TR5 Undocumented
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; TR6 Test Command Register
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; TR7 Test Data Register
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;
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; Protected Mode Registers
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; GDTR
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;
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; Operand Size Label Description
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; 64-bit 32-bit
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; Bits 0-15 (Same) Limit Size of GDT
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; Bits 16-79 Bits 16-47 Base Starting Address of GDT
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;
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; LDTR
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; Stores the segment selector of the LDT.
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;
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; TR
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; Stores the segment selector of the TSS.
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;
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; IDTR
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; Operand Size Label Description
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; 64-bit 32-bit
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; Bits 0-15 (Same) Limit Size of IDT
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; Bits 16-79 Bits 16-47 Base Starting Address of IDT
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;=============================================================================================================
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; END OF REGISTER DOCUMENTATION
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;=============================================================================================================
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%ifndef AAL_x86_Def
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;=============================================================================================================
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; Instructions Library
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;=============================================================================================================
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; NO-Operation : Exchanges value of rax with rax to achieve nothing.
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%define nop XCHG rax, rax
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;=============================================================================================================
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; END - Instructions Library
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;=============================================================================================================
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;=============================================================================================================
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; Interrupts
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;=============================================================================================================
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; BIOS
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; CX, DX Interval in microseconds
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; CX : High, DX : Low
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; SystemService
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%define BIOS_Wait 0x86
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; Memory
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; Real Mode - Conventional Lower Memory
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%define Mem_RM_CLower_Start 0x0500
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%define Mem_RM_CLower_End 0x7BFF
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; 2 Byte Boundary Alignment
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%define Mem_RM_CLower_2BB_End 0x7BE0
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; Real Mode - Conventional Upper memory
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%define Mem_RM_CUpper_Start 0x7E00
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%define Mem_RM_CUpper_End 0x7FFF
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; 2 Byte Boundary Alignment
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%define Mem_RM_CUpper_2BB_End 0x7FE0
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; Real Mode - OS Boot Sector
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%define Mem_BootSector_Start 0x7C00
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%define Mem_BootSector_512 0x7CFE
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%define Mem_BootSector_End 0x7DFF
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; Misc System Services
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%define SystemService 0x15
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; Video
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%define VideoService 0x10
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; Returns
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; AH = Number of character columns
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; AL = Display mode
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; BH = Active Page
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%define Video_GetCurrentMode 0x0F
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; Used to set the video mode.
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%define Video_SetMode 0x00
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; SetVideoMode - Modes
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; cbOff : Color Burst Off
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%define VideoMode_Text_40x25_cbOff 0x00
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%define VideoMode_Text_40x25 0x01
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%define VideoMode_Text_80x25_cbOff 0x02
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%define VideoMode_Text_80x25 0x03
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%define VideoMode_Graphics_320x200 0x04
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%define VideoMode_Graphics_320x200_cboff 0x05
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%define VideoMode_Graphics_640x200 0x06
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; Output a character
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%define Video_TeleType 0xE
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; Where memory buffer for Video's Text mode starts
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%define Video_Text_MemBuffer 0xB800
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;=============================================================================================================
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; END - Interrupts
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;=============================================================================================================
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%define char_CR 0xD ; Carriage Return
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%define char_LF 0xA ; Line Feed
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%define AAL_x86_Def
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%endif
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