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87 lines
3.2 KiB
HTML
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<h1>20161017 - Notes from Attempting to Understand FPGA Timing Limits</h1>
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<br>
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<i>I'm using the table I built below as a quick reference to think though timing while working on design.
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Reference from last time,
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<a href="http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf">Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics</a>.
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Working from the Speed Grade -3 (fastest) numbers in ns below.</i>
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<br>
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<br>
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<pre>
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==========
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TIMING
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==========
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Simplified drawing below
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Where phase of stages would in practice be different
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Where regions are not to scale
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_______________ _______________
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\_______________/ \_______________/ \
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_______________________________
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(____________STAGE_0____________)_______________________________
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. (____________STAGE_1____________)
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. .
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. .
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|<- 0.45 ->|<- 0.31 ->| |<- 0.64 ->|
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setup hold delay
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BRAM address register BRAM registered read stable
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My mental model is that the 'delay' eats against the 'setup' for the next stage
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Each stage ends in a register (D flip-flop)
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The cumulative post register, combinatorial, and net 'delay' from any logic on the wire
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must not violate the 'setup' time for the stage's register
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The 'hold' effects the limits of the phase of the stage (offset from positive clock edge)
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Timing limits from my (possibly flawed) understanding of the doc,
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term meaning
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==== =======
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BRAM block ram
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CRAM CLB distributed ram
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number meaning
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======= =======
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0.07 ns CLB 6:1 LUT setup time
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0.59 ns CLB complex setup time (larger than 6:1, carry)
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0.12 ns CLB 6:1 LUT hold time
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0.08 ns CLB complex hold time
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------- -------
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0.47 ns CLB 5:1x2 LUT registered delay (2 reg/LUT)
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0.40 ns CLB registered delay otherwise (1 reg/LUT)
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------- -------
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0.10 ns CLB 6:1 LUT combinatorial delay (no register)
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0.27 ns CLB 5:1x2 LUT combinatorial delay
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0.68 ns CLB maximum combinatorial delay for complex (larger than 6:1, carry)
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------- -------
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0.26 ns DSP a setup time
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0.33 ns DSP b setup time
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0.17 ns DSP c setup time
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0.12 ns DSP a hold time
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0.15 ns DSP b hold time
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0.17 ns DSP c hold time
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0.33 ns DSP p registered output delay
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------- -------
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0.45 ns BRAM address setup time
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0.31 ns BRAM address hold time
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0.64 ns BRAM registered read delay before stable time
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------- -------
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0.27 ns CRAM address setup time
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0.69 ns CRAM address setup time with post-load carry or mux usage
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0.55 ns CRAM address hold time
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0.18 ns CRAM address hold time with post-load carry or mux usage
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0.10 ns CRAM read registered output delay (same as 6:1 LUT combinatorial delay)
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0.98 ns CRAM write registered output delay (CRAM 64-entry or smaller, etc)
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2.10 ns CRAM minimum clock period for writes (limits to 476 MHz?)
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</pre>
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