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<h1>20150913 - Minimal Operand CPU ISA For IPC</h1>
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<br>
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<i>Dumping some thoughts on CPU design, one way to design for higher IPC (ILP) with something similar to a dual-stack forth machine...</i><br>
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<br>
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This started from the thought that it might be possible
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to apply almost zero-operand ISA design to a CPU designed for IPC.
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Packing either 3 or 4 operations into a single 32-bit instruction word.
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This form of instruction compression has all sorts of advantages,
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both in reduction of bandwidth
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and as a side effect reducing the wires and ports required to implement.
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Started thinking about a fictional implementation of a 32-bit integer only computer,
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something which, in theory thanks to a minimal ISA,
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could be JIT compiled on a conventional CPU via just a lookup table (would be very fast emulation).
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However in this post I'm deviating from the idea of emulation
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and throwing in ideas which would be better for dedicated hardware (like using per slot data stacks instead of just registers).
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<br>
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<br>
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<pre>
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Each instruction is a fixed 32-bits in size.
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Each instruction holds 4 slots {0,1,2,3}.
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Each slot has an 8-bit opcode.
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11111111111111110000000000000000
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FEDCBA9876543210FEDCBA9876543210
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MSB LSB
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........................ssssssss 8-bit opcode for slot 0
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................tttttttt........ 8-bit opcode for slot 1
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........uuuuuuuu................ 8-bit opcode for slot 2
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vvvvvvvv........................ 8-bit opcode for slot 3
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Slots share the following 32-bit registers,
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return stack pointer : R
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instruction pointer : I
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Each slot has its own 32-bit registers: slot {0,1,2,3},
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top registers : {S,T,U,V}
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2nd registers : {K,L,M,N}
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address registers : {W,X,Y,Z}
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</pre>
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<br>
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The "top" is the top of a very short per-slot data stack
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(which loops around on overflow, and has no memory backing).
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The "2nd" registers are just the 2nd item on the data stack.
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This split data and return stack shares a lot of similarities in structure to Color Forth style hardware.
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The reads of top and address registers of other slots, would see the value from the prior clock.
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So think of all the slots executing in parallel.
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<br>
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<br>
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Dedicated address registers provide some interesting properties.
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Becomes possible to limit the opcode space and operations
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applied to them.
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It also becomes possible to auto prefetch cache lines into L0 (something much closer than L1)
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when the address registers are set.
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So using half the opcode space for 32-bit load and stores with
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a literal range large enough for access to a complete cache line.
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The # below represents how many opcode slots are taken up.
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NOTE, addressing is by 32-bit word, not by byte!
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The load pushes the fetched value on the slot's data stack (so 2nd ends up being the old top).
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The store pops the value off the slot's data stack (so top ends up being the prior 2nd, etc).
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Grabbing 32-bit literals can be done with one opcode "#", taking the next instruction as data, and advancing the CP.
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There is a secondary load path which uses a top register as an address.
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The . is a place-holder for some opcode binary data I didn't feel like flushing out.
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<br>
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<br>
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<pre>
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ENCODING ASM # MEANING
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-------- ---- -- -------
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00ssiiii si@ 64 top(%)=[adr(s)+i]
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01ssiiii si! 64 [adr(s)+i]=top(%)
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1.....ss s@ 4 [top(s)+i]=top(%)
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1....... # 1 top(%)=next instruction
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% = current slot
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s = 2-bit slot index
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i = 4-bit unsigned immediate
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</pre>
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<br>
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Integer operations can take advantage of slot implied destination and first source,
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using another slot's "top" as 2nd source or using the current slot's "2nd".
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Using "2nd" consumes the value from the slot's local data stack.
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Using "top" from another slot does not consume the value.
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These support cross slot source reads without taking much opcode space.
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I left out shifts and other operations, just providing a few examples below,
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<br><br>
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<pre>
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ENCODING ASM # MEANING
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-------- ---- -- -------
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1.....ss s 4 top(%)=src(s)?
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1.....ss s+ 4 top(%)=top(%)+src(s)
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1.....ss s* 4 top(%)=top(%)*src(s)
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1.....ss s& 4 top(%)=top(%)&src(s)
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1.....ss s| 4 top(%)=top(%)|src(s)
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1.....ss s^ 4 top(%)=top(%)^src(s)
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1....... - 1 top(%)=-top(%)
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1....... ~ 1 top(%)=~top(%)
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% = current slot
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s = 2-bit slot index
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src(s) := if(s==%) 2nd(%) else top(s)
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</pre>
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<br>
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Address register operations are separate from standard ALU ops.
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Supporting ability to write to another slot's address register
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unlocks working on address registers in any slot.
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Setting an address register pops the top off the slot's local data stack.
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Fetching an address register pushes the value on the slot's local data stack.
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<br>
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<br>
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<pre>
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ENCODING ASM # MEANING
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-------- ---- -- -------
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1.....ss sP 4 top(%)=adr(s)
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1.....ss sP= 4 adr(s)=top(%)
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1.....ss sP+= 4 adr(s)=adr(s)+top(%)
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% = current slot
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s = 2-bit slot index
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src(s) := if(s==%) 2nd(%) else top(s)
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</pre>
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<br>
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Branching can act as a terminator of the 4 opcode packed 32-bit instruction word.
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So slots after a branch become a nop,
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and the space is reused for a literal for the branch itself.
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So 24-bit, 16-bit, or 8-bit, or 0-bit displacement.
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</div></body></html>
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@@ -89,6 +89,7 @@ O OOO ||..||OO||||||||||OOo || ||||||||||||| ||||OO|| |o| ||||||||OO||OOO
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<a href="20150930.html">20150930 - Tonemapping and Slot Mask Simulation</a><br>
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<a href="20150915.html">20150915 - Bacon Wrapped Sour Cream</a><br>
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<a href="20150914.html">20150914 - Tearaway Unfolded PS4 on Wega CRT HDTV</a><br>
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<a href="20150913.html">20150913 - Minimal Operand CPU ISA For IPC</a><br>
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<a href="20150912.html">20150912 - Self-Correcting Part 2 or Rather a Rant on Why Extreme DoD</a><br>
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<a href="20150911.html">20150911 - Self-Correcting CPU Pipelines</a><br>
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<a href="20150910.html">20150910 - September Trip to Iceland</a><br>
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