1859788005445414927, 1781724275159728279
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---
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title: "@KostasAAA It's a silly thing on many levels."
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type: archive
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source: twitter
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source_url: "https://x.com/jaap_null/status/1783039982560784428"
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author: "Jaap van Muijden"
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handle: jaap_null
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post_id: "1783039982560784428"
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date: 2024-04-24
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archived: 2026-08-25
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draft: true
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tags:
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- archive
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- twitter
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- KostasAAA
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description: "@KostasAAA It's a silly thing on many levels."
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in_reply_to: ""
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parent_post_id: "1781724279798686001"
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---
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## Source
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- URL: https://x.com/jaap_null/status/1783039982560784428
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- Author: Jaap van Muijden (@jaap_null)
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- Posted: 2024-04-24 07:47:13
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## Branch
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**1/**
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@KostasAAA It's a silly thing on many levels. The entire arch. limitation is awkward, then the way compilers deal (or not deal) with it is just broken. Sad to see it's still around.
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## Related
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- Spine: [[archive/threads/KostasAAA/2024-04-20-when-using-arrays-of-resources-bindless-its-worth]]
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+39
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---
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title: "@KostasAAA What's the value of shaderSampledImageArrayDynamicIndexing?"
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type: archive
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source: twitter
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source_url: "https://x.com/matiasgoldberg/status/1783166450733113360"
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author: "Matías N. Goldberg"
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handle: matiasgoldberg
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post_id: "1783166450733113360"
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date: 2024-04-24
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archived: 2026-08-25
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draft: true
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tags:
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- archive
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- twitter
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- KostasAAA
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description: "@KostasAAA What's the value of shaderSampledImageArrayDynamicIndexing?"
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in_reply_to: ""
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parent_post_id: "1781724279798686001"
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---
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## Source
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- URL: https://x.com/matiasgoldberg/status/1783166450733113360
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- Author: Matías N. Goldberg (@matiasgoldberg)
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- Posted: 2024-04-24 16:09:46
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## Branch
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**1/**
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@KostasAAA What's the value of shaderSampledImageArrayDynamicIndexing?
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I'm seeing an alarming number of reports (93%!!!) saying this is true, when that'd be a blatant lie.
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https://vulkan.gpuinfo.org/listdevicescoverage.php?feature=shaderSampledImageArrayDynamicIndexing&platform=all
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## Related
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- Spine: [[archive/threads/KostasAAA/2024-04-20-when-using-arrays-of-resources-bindless-its-worth]]
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+44
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---
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title: "When using arrays of resources/bindless, it's worth paying attention to index divergence."
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type: archive
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source: twitter
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source_url: "https://x.com/KostasAAA/status/1781724275159728279"
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author: "Kostas Anagnostou"
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handle: KostasAAA
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post_id: "1781724275159728279"
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date: 2024-04-20
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archived: 2026-08-25
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draft: true
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tags:
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- archive
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- twitter
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- KostasAAA
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description: "When using arrays of resources/bindless, it's worth paying attention to index divergence."
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in_reply_to: ""
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---
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## Source
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- URL: https://x.com/KostasAAA/status/1781724275159728279
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- Author: Kostas Anagnostou (@KostasAAA)
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- Posted: 2024-04-20 16:39:04
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## Thread
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**1/**
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When using arrays of resources/bindless, it's worth paying attention to index divergence. Even if using thread divergent indices, the compiler will use the index from the first active thread to access a resource, for all threads in the wave, which can cause hard to find bugs 1/3
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**2/**
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This happens even when compiler knows that the index varies per thread. To fix this you need to use the NonUniformResourceIndex qualifier. The compiler will then add a waterfall loop to batch wave threads by resource index and ensure that each thread accesses the correct one. 2/3
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**3/**
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This can have a performance impact though, with the worst case being each thread indexing a different resource, both in terms of thread coherence (looping over each thread individually) and texture cache. For more info https://www.asawicki.info/news_1734_which_values_are_scalar_in_a_shader 3/3
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Branches: [[archive/threads/KostasAAA/2024-04-20-when-using-arrays-of-resources-bindless-its-worth/2024-04-24-jaap_null-its-a-silly-thing-on-many-levels-the-entire-arch]], [[archive/threads/KostasAAA/2024-04-20-when-using-arrays-of-resources-bindless-its-worth/2024-04-24-matiasgoldberg-whats-the-value-of]]
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---
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title: KostasAAA
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type: note
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draft: false
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description: Archived threads by KostasAAA.
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tags:
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- archive
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- twitter
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- KostasAAA
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---
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- [[archive/threads/KostasAAA/2024-04-20-when-using-arrays-of-resources-bindless-its-worth]]
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+107
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---
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title: "@NOTimothyLottes Shouldn’t uniform be a scalar?"
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type: archive
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source: twitter
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source_url: "https://x.com/AgileJebrim/status/1859792525218988305"
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author: "Jebrim"
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handle: AgileJebrim
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post_id: "1859792525218988305"
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date: 2024-11-22
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archived: 2026-08-25
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draft: false
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tags:
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- archive
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- twitter
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- NOTimothyLottes
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description: "@NOTimothyLottes Shouldn’t uniform be a scalar?"
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in_reply_to: ""
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parent_post_id: "1859791162091110754"
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---
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## Source
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- URL: https://x.com/AgileJebrim/status/1859792525218988305
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- Author: Jebrim (@AgileJebrim)
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- Posted: 2024-11-22 02:54:25
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## Branch
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**1/**
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@NOTimothyLottes Shouldn’t uniform be a scalar?
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**2/**
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@AgileJebrim Well 'uniform' in GLSL is a storage qualifier, "Uniforms are so named because they DO NOT CHANGE from one shader invocation to the next within a particular rendering cal" so you probably want another term for SGPR to avoid aliasing qualifiers
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**3/**
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@NOTimothyLottes Within ISPC, uniform means scalar and varying means vector.
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**4/**
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@NOTimothyLottes Looking deeper into the definition of SGPRs. They’re uniform just across each wavefront, rather than the entire dispatch yeah?
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**5/**
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@AgileJebrim Yes it's a separate register file and logic unit that is per-wave instead of per-lane. Since it's introduction in Turing, NV calls them "URX for uniform registers" while AMD calls them SGPRs (scalar general purpose registers)
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**6/**
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@NOTimothyLottes Almost sounding like we need an alternative IR to SPIR-V. One with predicated instructions and these wavefront-uniform registers/instructions. Maybe a PTX -> RDNA backend compiler?
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**7/**
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@AgileJebrim As history goes, most re-writes fall into nearly the same problem as before. I'd rather have the fixes be applied to the existing stuff first (fix SPIR-V and GLSL, etc)
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**8/**
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@NOTimothyLottes Perhaps. That existing PTX Vulkan extension does come to mind though.
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**9/**
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@AgileJebrim @NOTimothyLottes Its kinda annoying to put sgpr like logic in an ir tho as they have very specific limitations on each platform.
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Generalizing them in an ir might actually be a pessimisation.
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**10/**
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@AgileJebrim @NOTimothyLottes Amd for example can't do float ops on sgprs, so when you would allow float ops in the ir, amd has to move them to a vgpr, perform float op, move them back to sgpr for each ir-sgpr float op.
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There are other examples for this.
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And nvidias have even other constrains.
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**11/**
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@CodePotrick @NOTimothyLottes And what’s the alternative right now? Just keep it all in a VGPR all the time?
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**12/**
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@AgileJebrim @NOTimothyLottes Ideally you'd avoid any float ops as long as you can to keep things in sgprs if you need to save registers/want the uniformity.
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If you need float ops on that var its probably best to keep it in vgprs if the alternative would be to transfer between sgpr and vgpr a lot
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**13/**
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@CodePotrick @NOTimothyLottes I wish I could work solely with integers all the time but if I did that on NV hardware, I’d be losing half the available ALUs.
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**14/**
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@CodePotrick @NOTimothyLottes I haven’t looked closely at AMD hardware since I don’t work with it much.
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**15/**
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@AgileJebrim @NOTimothyLottes they have their actual isa public and inspectable which is really nice to know whats actually happening.
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Rga is also really good. Feels like im more in control with amd compared to nvidia.
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Maybe thats just the low level gremlin in my speaking tho ;).
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**16/**
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@CodePotrick @NOTimothyLottes I do have access to some of NVIDIA’s NDA documentation and tools…
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## Related
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- Spine: [[archive/threads/NOTimothyLottes/2024-11-22-sometimes-you-only-want-to-wave-coherent-branch]]
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+74
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---
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title: "Sometimes you only want to wave-coherent branch to something extremely rarely."
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type: archive
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source: twitter
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source_url: "https://x.com/NOTimothyLottes/status/1859788005445414927"
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author: "NOTimothyLottes"
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handle: NOTimothyLottes
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post_id: "1859788005445414927"
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date: 2024-11-22
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archived: 2026-08-25
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draft: false
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tags:
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- archive
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- twitter
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- NOTimothyLottes
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description: "Sometimes you only want to wave-coherent branch to something extremely rarely."
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in_reply_to: ""
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---
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## Source
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- URL: https://x.com/NOTimothyLottes/status/1859788005445414927
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- Author: NOTimothyLottes (@NOTimothyLottes)
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- Posted: 2024-11-22 02:36:28
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## Thread
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**1/**
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Sometimes you only want to wave-coherent branch to something extremely rarely. There is no good way in GLSL to describe that. You always get one branch and one disruption of the linear path [RED]. What you want is [GREEN], common path is linear and branch-free. Gotos would enable
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**2/**
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In theory wave-coherent branch hint and then providing say a 99% taken branch taken compile hint could enable a compiler to know how to do proper code gen here
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**3/**
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The other thing, if you know a path is always taken by some of the lanes, and thus on AMD you want NO branches, and instead just EXEC changing, there is no way to express that either. Doing mix(,,bool) could add extra overhead vs simple EXEC masking
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**4/**
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This second example is why you want to be able to mix 'always-lane-divergent' branch hint, with '50% probability' meaning the HW needs to always execute both paths, and thus use EXEC masking without physical branching (assuming a good compiler)
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**5/**
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Also the lack of an explicit 'scalar' (aka SGPR) qualifier on variables. The compiler gets this wrong, a qualifier just fixes that problem. Non-SGPR platforms can just ignore the qualifier. And sgpr=readlane(maybeSgpr,0) can sometimes actually become a readlane (fail)
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Branches: [[archive/threads/NOTimothyLottes/2024-11-22-sometimes-you-only-want-to-wave-coherent-branch/2024-11-22-AgileJebrim-shouldnt-uniform-be-a-scalar]]
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**6/**
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Other big thing on AMD's PC side, the HW has all these nice SALU ops which set the SCC (scalar flags register), and there is no good way to trick the compiler to doing basic stuff like branch on SALU overflow ...
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**7/**
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I tried using GLSL's uaddCarry() but it at the time pushed the whole operation from SALU back to VALU making the code extra horrible, and uaddCarry() and friends = basic fail, the carry is a bool in HW not an integer, silly lack of good pattern matching there applies
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**8/**
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Anyway this stuff is easily fixable if people just actually cared about it. It's not like you need to scrap the API or invent a new language. Just fix what we have, and people like me will use it, and teach others how to use it well too.
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**9/**
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Also for obvious reasons, at least provide a PRAGMA "not-stupid" that we can place in shaders to avoid all the overhead generating crap that deoptimizes code to check for junior programmer mistakes at runtime, this stuff is bloody hard (and sometimes) impossible to bypass today
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**10/**
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Lets add another thing, if(subgroupElect()){} to try to make stuff SALU is broken. Because subgroupElect() will do all the overhead to find the lowest active lane (even in cases the compiler should know otherwise). And if(gl_SubgroupID==0) for that also isn't well optimized
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**11/**
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Maybe another time we should dive into the problems with shading languages mixing branching with loads and killing all the latency hiding. But too much for this thread...
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@@ -32,6 +32,7 @@ tags:
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- [[archive/threads/NOTimothyLottes/2024-11-16-that-line-of-thinking-is-universal-solution-to]]
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- [[archive/threads/NOTimothyLottes/2024-11-19-after-vk-device-is-open-i-signal-a-background]]
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- [[archive/threads/NOTimothyLottes/2024-11-21-32-oh-damn-32-should-probably-stop-now-until-next]]
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- [[archive/threads/NOTimothyLottes/2024-11-22-sometimes-you-only-want-to-wave-coherent-branch]]
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- [[archive/threads/NOTimothyLottes/2024-12-15-texel-buffer-is-needed-for-whatever-formats-one]]
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- [[archive/threads/NOTimothyLottes/2024-12-16-also-i-wouldnt-just-modify-an-existing-compiler]]
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- [[archive/threads/NOTimothyLottes/2024-12-16-then-there-are-rough-edges-to-texel-buffer]]
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@@ -15,6 +15,7 @@ Example of the note shape (single spine, no branches): [[archive/threads/How to
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- [[archive/threads/AgileJebrim]]
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- [[archive/threads/FFmpeg]]
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- [[archive/threads/KostasAAA]]
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- [[archive/threads/NOTimothyLottes]]
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- [[archive/threads/SebAaltonen]]
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- [[archive/threads/VPCOMPRESSB]]
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