1950935464149483683
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---
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title: "@NOTimothyLottes SPIR-V."
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type: archive
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source: twitter
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source_url: "https://x.com/AgileJebrim/status/1950936023447302584"
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author: "Jebrim"
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handle: AgileJebrim
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post_id: "1950936023447302584"
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date: 2025-07-31
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archived: 2026-08-25
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draft: false
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tags:
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- archive
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- twitter
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- NOTimothyLottes
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description: "@NOTimothyLottes SPIR-V."
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in_reply_to: ""
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parent_post_id: "1950935464149483683"
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---
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## Source
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- URL: https://x.com/AgileJebrim/status/1950936023447302584
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- Author: Jebrim (@AgileJebrim)
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- Posted: 2025-07-31 15:06:09
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## Branch
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**1/**
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@NOTimothyLottes SPIR-V. I’ve given up on trying to massage frontend compilers to do exactly what I want. I’m just letting others write in whatever shader language they want and then taking the SPIR-V it generates and reoptimizing it the way I want it.
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**2/**
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@NOTimothyLottes One of the motivating factors is the fact that people already have a bunch of existing code, so the less work needed on their part to rewrite it, the better.
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**3/**
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@AgileJebrim If IHV compilers all handled well the case where the SPIR-V skips most SSA and leverages OpLoad/Store to global shader data (as in registers not memory), it might be a lot more tractable to go direct to SPIR-V.
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**4/**
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@NOTimothyLottes I’m forcing the case where each invocation has access to a full 256 registers, which should hopefully limit the whole SSA/register spill problem. I haven’t tried intentionally breaking SSA though. Even if I did, there’s no way such UB would ever be certifiable.
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**5/**
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@AgileJebrim I don't know of any case where 256 registers had acceptable performance. And that includes IHV hand assembly. Full unrolling on GCN needed at least 2 waves/SIMD (128 regs max). And I personally target around 64 for anything going through a compiler.
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**6/**
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@AgileJebrim Note on some newer AMD GPUs they increased the regfile by 50% I think, which would be a 96 max reg target
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**7/**
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@AgileJebrim Some of the larger problems with compilers is common sub-expression elimination. Meaning they will take out intentional recoputation or reloads and add register pressure. Often one has to fake a different value by ORing to a dynamic loaded zero (not known at compiler time)
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**8/**
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@AgileJebrim Meaning at medium levels of complexity the compilers are always going way over the register budget you'd target with hand written ASM. SSA ensures this. There are no aliasing hints in the IR.
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## Related
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- Spine: [[archive/threads/NOTimothyLottes/2025-07-31-been-on-the-fence-on-writing-shader-interfaces-in]]
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+51
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---
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title: "@NOTimothyLottes What's the top \"something else\"? I've been out of the space for a while."
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type: archive
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source: twitter
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source_url: "https://x.com/olson_dan/status/1951144195843928435"
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author: "Dan Olson"
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handle: olson_dan
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post_id: "1951144195843928435"
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date: 2025-08-01
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archived: 2026-08-25
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draft: false
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tags:
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- archive
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- twitter
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- NOTimothyLottes
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description: "@NOTimothyLottes What's the top \"something else\"? I've been out of the space for a while."
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in_reply_to: ""
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parent_post_id: "1950935464149483683"
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---
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## Source
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- URL: https://x.com/olson_dan/status/1951144195843928435
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- Author: Dan Olson (@olson_dan)
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- Posted: 2025-08-01 04:53:21
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## Branch
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**1/**
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@NOTimothyLottes What's the top "something else"? I've been out of the space for a while.
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**2/**
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@olson_dan Wanting to build something that effectively loads/stores a 'cart' file which contains all the 'code+data' of the game in a restartable package. The code cannot be GLSL because I'm not going to link in a huge compiler. Leaves something that generates SPIR-V on the fly. New lang
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**3/**
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@NOTimothyLottes @olson_dan For a long time i have contemplated writing a small GLSL->SPIR-V compiler. I think you could get away with something very simple, if you are conservative with your language use.
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**4/**
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@EskilSteenberg @olson_dan Have a crazy idea for GPU shader dev inspired by a C64 SID tracker where you have a 'pattern' for the 'instrument' which shows SID fx changing over time, along with the standard multi-channel pattern nestily using the instrument ...
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**5/**
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@EskilSteenberg @olson_dan ... Effectively a macro assembly language style thing where defines can be played back interleaved for things like ILP or loop unrolling etc. But programmer controlling interleaving, and register offsets, etc. Then ultimately output to SPIR-V direct (no GLSL step).
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## Related
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- Spine: [[archive/threads/NOTimothyLottes/2025-07-31-been-on-the-fence-on-writing-shader-interfaces-in]]
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+7
-2
@@ -14,7 +14,8 @@ tags:
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- twitter
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- NOTimothyLottes
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description: "@onatt0 @EskilSteenberg @olson_dan So far the plan is to have the data read/write from the GPU, but still use the CPU to do the SPIR-V generation from said data."
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in_reply_to: "1951591243328135279"
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in_reply_to: ""
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parent_post_id: "1951591243328135279"
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---
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## Source
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@@ -23,8 +24,12 @@ in_reply_to: "1951591243328135279"
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- Author: NOTimothyLottes (@NOTimothyLottes)
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- Posted: 2025-08-02 13:36:07
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## Thread
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## Branch
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**1/**
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@onatt0 @EskilSteenberg @olson_dan So far the plan is to have the data read/write from the GPU, but still use the CPU to do the SPIR-V generation from said data.
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## Related
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- Spine: [[archive/threads/NOTimothyLottes/2025-07-31-been-on-the-fence-on-writing-shader-interfaces-in]]
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+58
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---
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title: "Been on the fence on writing shader interfaces in GLSL vs something else that translates to SPIR-V."
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type: archive
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source: twitter
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source_url: "https://x.com/NOTimothyLottes/status/1950935464149483683"
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author: "NOTimothyLottes"
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handle: NOTimothyLottes
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post_id: "1950935464149483683"
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date: 2025-07-31
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archived: 2026-08-25
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draft: false
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tags:
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- archive
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- twitter
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- NOTimothyLottes
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description: "Been on the fence on writing shader interfaces in GLSL vs something else that translates to SPIR-V."
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in_reply_to: ""
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---
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## Source
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- URL: https://x.com/NOTimothyLottes/status/1950935464149483683
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- Author: NOTimothyLottes (@NOTimothyLottes)
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- Posted: 2025-07-31 15:03:55
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## Thread
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**1/**
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Been on the fence on writing shader interfaces in GLSL vs something else that translates to SPIR-V. Most GLSL mixed with defines can just direct port to other platforms. However these days I have hundreds of lines of macros to transform GLSL closer to assembly.
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Branches: [[archive/threads/NOTimothyLottes/2025-07-31-been-on-the-fence-on-writing-shader-interfaces-in/2025-07-31-AgileJebrim-spir-v-ive-given-up-on-trying-to-massage-frontend]], [[archive/threads/NOTimothyLottes/2025-07-31-been-on-the-fence-on-writing-shader-interfaces-in/2025-08-01-olson_dan-whats-the-top-something-else-ive-been-out-of-the]]
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**2/**
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Meaning I write using macros that are mostly a 1:1 mapping to AMDs GCN/RDNA ISA. With workarounds for missing stuff. SPIR-V output is an intimidating level of complex verbosity. More so when navigating frequent type bit aliasing (float, int, packed 16-bit float and int).
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**3/**
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@NOTimothyLottes Sounds like an RDNA->SPIRV asm converter tool would be the way to go
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**4/**
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@JBrooksBSI I part tried to GLSL once. Using a global uint4 array as registers. But the wrapping of bit aliasing typecasts around operations is loaded with compiler perf bugs. Esp with packed 16-bit. So making it usable in practice is quite hard.
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**5/**
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@NOTimothyLottes What I do for console dev is write RDNA2 asm on PS5 (via wrapped shader intrinsics).
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On Xbox I have the wrappers implement C versions of the intrinsics (or HLSL intrinsics where available).
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This is a technique I have been using since 2006, for PS3 SPU coding:
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**6/**
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@JBrooksBSI Eventually I ended up the same way (writing via instruction defines). Originally when I did FXAA it was a 1:1 line mapping to NV ISA. But without factoring through a define. But it's really the custom register allocation that I wish was universally expressible today.
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@@ -51,9 +51,9 @@ tags:
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- [[archive/threads/NOTimothyLottes/2025-04-30-3-i-got-side-tracked-by-building-a-language-that]]
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- [[archive/threads/NOTimothyLottes/2025-04-30-i-laugh-when-people-say-c-is-like-assembly-they]]
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- [[archive/threads/NOTimothyLottes/2025-07-23-nobody-self-includes-with-defines-to-reorder-c]]
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- [[archive/threads/NOTimothyLottes/2025-07-31-been-on-the-fence-on-writing-shader-interfaces-in]]
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- [[archive/threads/NOTimothyLottes/2025-07-31-people-claim-assembly-is-hard]]
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- [[archive/threads/NOTimothyLottes/2025-08-01-at-least-for-my-next-at-home-project-i-think-the]]
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- [[archive/threads/NOTimothyLottes/2025-08-02-so-far-the-plan-is-to-have-the-data-read-write]]
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- [[archive/threads/NOTimothyLottes/2025-10-10-thread-about-this-from-rfleury-https-www-rfleury]]
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- [[archive/threads/NOTimothyLottes/2025-10-13-short-talk-on-how-i-do-cpu-side-debugging-without]]
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- [[archive/threads/NOTimothyLottes/2025-11-17-i-wish-everyone-would-just-adopt-reversed-with]]
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