1870345628531999121
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title: "@NOTimothyLottes Have you tried using the Intel cache controls extension I shared earlier to see if they work on AMD?"
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type: archive
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source: twitter
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source_url: "https://x.com/AgileJebrim/status/1870345628531999121"
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author: "Jebrim"
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handle: AgileJebrim
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post_id: "1870345628531999121"
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date: 2024-12-21
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archived: 2026-08-24
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draft: false
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tags:
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- archive
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- twitter
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- NOTimothyLottes
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description: "@NOTimothyLottes Have you tried using the Intel cache controls extension I shared earlier to see if they work on AMD?"
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in_reply_to: ""
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parent_post_id: "1870343645926224197"
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---
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## Source
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- URL: https://x.com/AgileJebrim/status/1870345628531999121
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- Author: Jebrim (@AgileJebrim)
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- Posted: 2024-12-21 05:48:41
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## Branch
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**1/**
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@NOTimothyLottes Have you tried using the Intel cache controls extension I shared earlier to see if they work on AMD?
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**2/**
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@AgileJebrim Not enough free time. Given that AMD's compiler has some serious correctness bugs ignoring memory qualifiers, I doubt they implemented the Intel extension.
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**3/**
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@AgileJebrim Will say though that if they ever implement a WMMA access extension (I don't know if they did or didn't yet), and they don't have streaming memory qualifier support they are just shooting their own AI stock$$$ gold rush foot off.
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## Related
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- Spine: [[archive/threads/NOTimothyLottes/2024-12-21-not-sure-if-this-is-the-end-of-this-story-yet-but]]
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@@ -44,6 +44,8 @@ A ... coherent (atomics)
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E ... streaming readonly (aka [E]xclusive)
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F ... streaming writeonly (aka [F]inal)
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Branches: [[archive/threads/NOTimothyLottes/2024-12-21-not-sure-if-this-is-the-end-of-this-story-yet-but/2024-12-21-AgileJebrim-have-you-tried-using-the-intel-cache-controls]]
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**4/**
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