1870345628531999121

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---
title: "@NOTimothyLottes Have you tried using the Intel cache controls extension I shared earlier to see if they work on AMD?"
type: archive
source: twitter
source_url: "https://x.com/AgileJebrim/status/1870345628531999121"
author: "Jebrim"
handle: AgileJebrim
post_id: "1870345628531999121"
date: 2024-12-21
archived: 2026-08-24
draft: false
tags:
- archive
- twitter
- NOTimothyLottes
description: "@NOTimothyLottes Have you tried using the Intel cache controls extension I shared earlier to see if they work on AMD?"
in_reply_to: ""
parent_post_id: "1870343645926224197"
---
## Source
- URL: https://x.com/AgileJebrim/status/1870345628531999121
- Author: Jebrim (@AgileJebrim)
- Posted: 2024-12-21 05:48:41
## Branch
**1/**
@NOTimothyLottes Have you tried using the Intel cache controls extension I shared earlier to see if they work on AMD?
**2/**
@AgileJebrim Not enough free time. Given that AMD's compiler has some serious correctness bugs ignoring memory qualifiers, I doubt they implemented the Intel extension.
**3/**
@AgileJebrim Will say though that if they ever implement a WMMA access extension (I don't know if they did or didn't yet), and they don't have streaming memory qualifier support they are just shooting their own AI stock$$$ gold rush foot off.
## Related
- Spine: [[archive/threads/NOTimothyLottes/2024-12-21-not-sure-if-this-is-the-end-of-this-story-yet-but]]
@@ -44,6 +44,8 @@ A ... coherent (atomics)
E ... streaming readonly (aka [E]xclusive)
F ... streaming writeonly (aka [F]inal)
Branches: [[archive/threads/NOTimothyLottes/2024-12-21-not-sure-if-this-is-the-end-of-this-story-yet-but/2024-12-21-AgileJebrim-have-you-tried-using-the-intel-cache-controls]]
**4/**