spinlock thread

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---
title: "@SebAaltonen @stewartmoss , nice code up above."
type: archive
source: twitter
source_url: "https://x.com/AndrewJacksonZA/status/1125101399258353665"
author: "Andrew Jackson"
handle: AndrewJacksonZA
post_id: "1125101399258353665"
date: 2019-05-05
archived: 2026-08-27
draft: false
tags:
- archive
- twitter
- SebAaltonen
description: "@SebAaltonen @stewartmoss , nice code up above."
in_reply_to: ""
parent_post_id: "1125067183476944896"
---
## Source
- URL: https://x.com/AndrewJacksonZA/status/1125101399258353665
- Author: Andrew Jackson (@AndrewJacksonZA)
- Posted: 2019-05-05 18:14:11
## Branch
**1/** **@AndrewJacksonZA** ^1125101399258353665
**@SebAaltonen** **@stewartmoss**
, nice code up above.
Also: https://x.com/SebAaltonen/status/1125075962524262403
/CC @STEMsubsistence and @KeithPlaysPC , because exposure to/learning cool out-of-one's-depth stuff is sometimes extremely valuable. :-)
## Related
- Spine: [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two]]
@@ -0,0 +1,37 @@
---
title: "@SebAaltonen Interesting."
type: archive
source: twitter
source_url: "https://x.com/ArvidGerstmann/status/1125124392319582214"
author: "Arvid Gerstmann"
handle: ArvidGerstmann
post_id: "1125124392319582214"
date: 2019-05-05
archived: 2026-08-27
draft: false
tags:
- archive
- twitter
- SebAaltonen
description: "@SebAaltonen Interesting."
in_reply_to: ""
parent_post_id: "1125064645637738496"
---
## Source
- URL: https://x.com/ArvidGerstmann/status/1125124392319582214
- Author: Arvid Gerstmann (@ArvidGerstmann)
- Posted: 2019-05-05 19:45:33
## Branch
**1/** **@ArvidGerstmann** ^1125124392319582214
**@SebAaltonen**
Interesting. I've been using xchg over cmpxchg for ages, but according to the Intel manual, the performance of both is equivalent. This must be related to AMDs architecture.
## Related
- Spine: [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two]]
@@ -0,0 +1,41 @@
---
title: "Don’t use spinlock for waits."
type: archive
source: twitter
source_url: "https://x.com/SebAaltonen/status/1125065316650889217"
author: "Sebastian Aaltonen"
handle: SebAaltonen
post_id: "1125065316650889217"
date: 2019-05-05
archived: 2026-08-27
draft: false
tags:
- archive
- twitter
- SebAaltonen
description: "Don’t use spinlock for waits."
in_reply_to: ""
parent_post_id: "1125064645637738496"
---
## Source
- URL: https://x.com/SebAaltonen/status/1125065316650889217
- Author: Sebastian Aaltonen (@SebAaltonen)
- Posted: 2019-05-05 15:50:48
## Branch
**1/** **@SebAaltonen** ^1125065316650889217
Don’t use spinlock for waits. Use spinlock only to guard something that is guaranteed to return quickly. If you have an operation that is often fast but sometimes slow, use two stage spinlock with internal OS mutex.
**2/** **@SebAaltonen** ^1125067183476944896
Naive (bad) vs optimized (good) performance. See above post for code.
![](https://pbs.twimg.com/media/D50Ko4mXoAAR97L?format=jpg&name=orig)
## Related
- Spine: [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two]]
@@ -1,37 +0,0 @@
---
title: "@SebAaltonen It's missing exponential backoff for mm_pause though"
type: archive
source: twitter
source_url: "https://x.com/lectem/status/1125076786520514563"
author: "Clément Grégoire"
handle: lectem
post_id: "1125076786520514563"
date: 2019-05-05
archived: 2026-08-27
draft: false
tags:
- archive
- twitter
- SebAaltonen
description: "@SebAaltonen It's missing exponential backoff for mm_pause though"
in_reply_to: ""
parent_post_id: "1125067183476944896"
---
## Source
- URL: https://x.com/lectem/status/1125076786520514563
- Author: Clément Grégoire (@lectem)
- Posted: 2019-05-05 16:36:23
## Branch
**1/** **@lectem** ^1125076786520514563
**@SebAaltonen**
It's missing exponential backoff for mm_pause though
## Related
- Spine: [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two]]
@@ -0,0 +1,43 @@
---
title: "@SebAaltonen @septagh I would love to see a comparison to ARM64, from what I know its pretty similar but would be anyways interesting."
type: archive
source: twitter
source_url: "https://x.com/pATjako/status/1125117731198648320"
author: "Peter Jakobs"
handle: pATjako
post_id: "1125117731198648320"
date: 2019-05-05
archived: 2026-08-27
draft: false
tags:
- archive
- twitter
- SebAaltonen
description: "@SebAaltonen @septagh I would love to see a comparison to ARM64, from what I know its pretty similar but would be anyways interesting."
in_reply_to: ""
parent_post_id: "1125064645637738496"
---
## Source
- URL: https://x.com/pATjako/status/1125117731198648320
- Author: Peter Jakobs (@pATjako)
- Posted: 2019-05-05 19:19:05
## Branch
**1/** **@pATjako** ^1125117731198648320
**@SebAaltonen** **@septagh**
I would love to see a comparison to ARM64, from what I know its pretty similar but would be anyways interesting.
**2/** **@SebAaltonen** ^1125125629022752770
**@pATjako** **@septagh**
ARM64 needs different code. Use atomic load to get correct codegwn for both (will compile to standard load on x64).
## Related
- Spine: [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two]]
@@ -0,0 +1,43 @@
---
title: "@SebAaltonen Got a link to the slide deck?"
type: archive
source: twitter
source_url: "https://x.com/romzr/status/1125071110314254341"
author: "Romain Dura"
handle: romzr
post_id: "1125071110314254341"
date: 2019-05-05
archived: 2026-08-27
draft: false
tags:
- archive
- twitter
- SebAaltonen
description: "@SebAaltonen Got a link to the slide deck?"
in_reply_to: ""
parent_post_id: "1125064645637738496"
---
## Source
- URL: https://x.com/romzr/status/1125071110314254341
- Author: Romain Dura (@romzr)
- Posted: 2019-05-05 16:13:50
## Branch
**1/** **@romzr** ^1125071110314254341
**@SebAaltonen**
Got a link to the slide deck?
**2/** **@SebAaltonen** ^1125075962524262403
**@romzr**
https://gpuopen.com/gdc-presentations/2019/gdc-2019-s2-amd-ryzen-processor-software-optimization.pdf
## Related
- Spine: [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two]]
@@ -0,0 +1,49 @@
---
title: "@SebAaltonen TATAS (read-only inner-loop) is a much better pattern for a multicore system with multiple caches (https://github.com/concurrencykit/ck/blob/master/include/spinlock/fas.h#L77)."
type: archive
source: twitter
source_url: "https://x.com/0xF390/status/1125432870510759937"
author: "Samy Al Bahra"
handle: 0xF390
post_id: "1125432870510759937"
date: 2019-05-06
archived: 2026-08-27
draft: false
tags:
- archive
- twitter
- SebAaltonen
description: "@SebAaltonen TATAS (read-only inner-loop) is a much better pattern for a multicore system with multiple caches (https://github.com/concurrencykit/ck/blob/master/include/spinlock/fas.h#L77)."
in_reply_to: ""
parent_post_id: "1125064645637738496"
---
## Source
- URL: https://x.com/0xF390/status/1125432870510759937
- Author: Samy Al Bahra (@0xF390)
- Posted: 2019-05-06 16:11:20
## Branch
**1/** **@0xF390** ^1125432870510759937
**@SebAaltonen**
TATAS (read-only inner-loop) is a much better pattern for a multicore system with multiple caches (https://github.com/concurrencykit/ck/blob/master/include/spinlock/fas.h#L77).
**2/** **@SebAaltonen** ^1125617029438947328
**@0xF390**
This is TATAS too. It does standard read until read returns unlocked (|| is short circuited -> exchange doesn’t run when outer test succeeds). Your code has extra CAS outer case. Not needed. Just makes fast path (no lock) slower.
**3/** **@0xF390** ^1125624687663427584
**@SebAaltonen**
Edits. You're right! I read the wrong block. Regarding the Concurrency Kit code, which CAS outer-case are you referring to? There is none, FAS = xchg.
## Related
- Spine: [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two]]
@@ -0,0 +1,37 @@
---
title: "@SebAaltonen You can find many implementations here, including fair and scalable locks: https://github.com/concurrencykit/ck/blob/master/include/spinlock/fas.h"
type: archive
source: twitter
source_url: "https://x.com/0xF390/status/1125428859367776256"
author: "Samy Al Bahra"
handle: 0xF390
post_id: "1125428859367776256"
date: 2019-05-06
archived: 2026-08-27
draft: false
tags:
- archive
- twitter
- SebAaltonen
description: "@SebAaltonen You can find many implementations here, including fair and scalable locks: https://github.com/concurrencykit/ck/blob/master/include/spinlock/fas.h"
in_reply_to: ""
parent_post_id: "1125064645637738496"
---
## Source
- URL: https://x.com/0xF390/status/1125428859367776256
- Author: Samy Al Bahra (@0xF390)
- Posted: 2019-05-06 15:55:24
## Branch
**1/** **@0xF390** ^1125428859367776256
**@SebAaltonen**
You can find many implementations here, including fair and scalable locks: https://github.com/concurrencykit/ck/blob/master/include/spinlock/fas.h
## Related
- Spine: [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two]]
@@ -0,0 +1,37 @@
---
title: "@SebAaltonen I have one suggestion: 1st stage you measure how long pause takes."
type: archive
source: twitter
source_url: "https://x.com/matiasgoldberg/status/1125410054725881859"
author: "Matías N. Goldberg"
handle: matiasgoldberg
post_id: "1125410054725881859"
date: 2019-05-06
archived: 2026-08-27
draft: false
tags:
- archive
- twitter
- SebAaltonen
description: "@SebAaltonen I have one suggestion: 1st stage you measure how long pause takes."
in_reply_to: ""
parent_post_id: "1125064645637738496"
---
## Source
- URL: https://x.com/matiasgoldberg/status/1125410054725881859
- Author: Matías N. Goldberg (@matiasgoldberg)
- Posted: 2019-05-06 14:40:40
## Branch
**1/** **@matiasgoldberg** ^1125410054725881859
**@SebAaltonen**
I have one suggestion: 1st stage you measure how long pause takes. In second step you issue pause every N iterations (or N pause per iteration) https://aloiskraus.wordpress.com/2018/06/16/why-skylakex-cpus-are-sometimes-50-slower-how-intel-has-broken-existing-code/
## Related
- Spine: [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two]]
@@ -0,0 +1,43 @@
---
title: "@SebAaltonen @kenpex Its a shame there is no mm_pause in the BAD case - it’s not obvious how much of the win comes from not using CAS vs pausing."
type: archive
source: twitter
source_url: "https://x.com/morfar/status/1125272627868852225"
author: "Jonas Meyer"
handle: morfar
post_id: "1125272627868852225"
date: 2019-05-06
archived: 2026-08-27
draft: false
tags:
- archive
- twitter
- SebAaltonen
description: "@SebAaltonen @kenpex Its a shame there is no mm_pause in the BAD case - it’s not obvious how much of the win comes from not using CAS vs pausing."
in_reply_to: ""
parent_post_id: "1125064645637738496"
---
## Source
- URL: https://x.com/morfar/status/1125272627868852225
- Author: Jonas Meyer (@morfar)
- Posted: 2019-05-06 05:34:35
## Branch
**1/** **@morfar** ^1125272627868852225
**@SebAaltonen** **@kenpex**
Its a shame there is no mm_pause in the BAD case - it’s not obvious how much of the win comes from not using CAS vs pausing.
**2/** **@SebAaltonen** ^1125275721449050112
**@morfar** **@kenpex**
Yeah. Should definitely have 3 benchmarks cases. Bad, better, best.
## Related
- Spine: [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two]]
@@ -31,14 +31,12 @@ This is how you write a good x64 spinlock: Use two stage construct. Outer test i
![](https://pbs.twimg.com/media/D50IVH0W0AALQ0y?format=jpg&name=orig)
**2/** **@SebAaltonen** ^1125065316650889217
Branches: [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two/2019-05-05-SebAaltonen-dont-use-spinlock-for-waits-use-spinlock-only-to]], [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two/2019-05-05-romzr-got-a-link-to-the-slide-deck]], [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two/2019-05-05-pATjako-i-would-love-to-see-a-comparison-to-arm64-from]], [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two/2019-05-05-ArvidGerstmann-interesting-ive-been-using-xchg-over-cmpxchg-for]], [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two/2019-05-06-morfar-its-a-shame-there-is-no-mm-pause-in-the-bad-case]], [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two/2019-05-06-matiasgoldberg-i-have-one-suggestion-1st-stage-you-measure-how]], [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two/2019-05-06-0xF390-you-can-find-many-implementations-here-including]], [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two/2019-05-06-0xF390-tatas-read-only-inner-loop-is-a-much-better]]
Don’t use spinlock for waits. Use spinlock only to guard something that is guaranteed to return quickly. If you have an operation that is often fast but sometimes slow, use two stage spinlock with internal OS mutex.
**2/** **@SebAaltonen** ^1125622264819605504
**3/** **@SebAaltonen** ^1125067183476944896
Important clarification: Using basic load works only on x86/64. Better use atomic load. It will result in the exactly same compiled code on x64 and work also on ARM64. Also gives compiler more info to avoid unwanted optimizations.
Naive (bad) vs optimized (good) performance. See above post for code.
**3/** **@SebAaltonen** ^1125622526250508289
![](https://pbs.twimg.com/media/D50Ko4mXoAAR97L?format=jpg&name=orig)
Branches: [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two/2019-05-05-lectem-its-missing-exponential-backoff-for-mm-pause]], [[archive/threads/SebAaltonen/2019-05-05-this-is-how-you-write-a-good-x64-spinlock-use-two/2019-05-05-AndrewJacksonZA-nice-code-up-above-also-https-x-com-sebaaltonen]]
For more info watch this: https://x.com/sebaaltonen/status/1125084734365872129?s=21