1604260386659880961

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---
title: "@NOTimothyLottes cool!"
type: archive
source: twitter
source_url: "https://x.com/abductee_org/status/1604899144786620416"
author: "Michael Sänger (💉 3/2)"
handle: abductee_org
post_id: "1604899144786620416"
date: 2022-12-19
archived: 2026-08-26
draft: false
tags:
- archive
- twitter
- NOTimothyLottes
description: "@NOTimothyLottes cool!"
in_reply_to: ""
parent_post_id: "1604260386659880961"
---
## Source
- URL: https://x.com/abductee_org/status/1604899144786620416
- Author: Michael Sänger (💉 3/2) (@abductee_org)
- Posted: 2022-12-19 17:59:08
## Branch
**1/** **@abductee_org** ^1604899144786620416
**@NOTimothyLottes**
cool!
any similar comments on cuda12/ptx/sass? ;)
**2/** **@NOTimothyLottes** ^1605588165384814592
**@abductee_org**
https://x.com/NOTimothyLottes/status/1596096198758244352 and https://x.com/NOTimothyLottes/status/1596094389641965570
## Related
- Spine: [[archive/threads/NOTimothyLottes/2022-12-17-rdna3-isa-guide-comments]]
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---
title: "RDNA3 ISA Guide Comments"
type: archive
source: twitter
source_url: "https://x.com/NOTimothyLottes/status/1604260386659880961"
author: "NOTimothyLottes"
handle: NOTimothyLottes
post_id: "1604260386659880961"
date: 2022-12-17
archived: 2026-08-26
draft: false
tags:
- archive
- twitter
- NOTimothyLottes
description: "RDNA3 ISA Guide Comments"
in_reply_to: ""
---
## Source
- URL: https://x.com/NOTimothyLottes/status/1604260386659880961
- Author: NOTimothyLottes (@NOTimothyLottes)
- Posted: 2022-12-17 23:40:56
## Thread
**1/** **@NOTimothyLottes** ^1604260386659880961
RDNA3 ISA Guide Comments
(1.) Driver: Instead of padding 256 bytes with S_CODE_END, how about putting the next shader in there (looking at you post process passes, with consistent temporal ordering).
Branches: [[archive/threads/NOTimothyLottes/2022-12-17-rdna3-isa-guide-comments/2022-12-19-abductee_org-cool-any-similar-comments-on-cuda12-ptx-sass]]
**2/** **@NOTimothyLottes** ^1604263778106892292
(2.) VGPR increase: Traditionally with 8 VGPR allocation granularity the target would be 64 VGPRs/wave or under. Now with 12 granularity a compiler can likely miss the 64 VGPR target and get to 96 without seeing a problem in those cases.
**3/** **@NOTimothyLottes** ^1604265437281271809
(3.) S_MEMREALTIME went to S_SENDMSG_RTN+S_WAITCNT (side effect, more opcode space), these would include a code motion barrier anyway. Would like a VK extension to query the "typically 100 MHz" fixed frequency amount: lots of nice things you can do with a real shader wallclock!
**4/** **@NOTimothyLottes** ^1604267130299596803
(4.) Really nice cache control via {SRD llc_noalloc, opcode DLC/SLC/GLC}. Wish there was a way to access using layout qualifier aliasing in VK. Esp 'STREAM' on loads, to avoid cache pollution when no reuse is known by the developer.
**5/** **@NOTimothyLottes** ^1604268044464930817
(5.) "Dealloc VGPRs" - CS waves need to wait until all pending stores return "finished" before the wave exits. But now the VGPRs can be returned before waiting (to be used by a new workgroup). However, persistent or semi-persistent waves is still the way to go IMO.
**6/** **@NOTimothyLottes** ^1604485986234388481
(6.) V_PERMLANE64 - Likely no more V_READLANE waterfall for dynamic index shuffle in Wave64 mode (don't have a RDNA3 to dump disassembly), but will LDS still be faster than the complex sequence of {PERMLANE16, PERMLANEX16, PERMLANE64} related logic?
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@@ -14,6 +14,7 @@ tags:
- [[archive/threads/NOTimothyLottes/2022-11-08-example-of-bind-everything-once-layout-aliasing]]
- [[archive/threads/NOTimothyLottes/2022-11-09-if-only-pc-vendors-with-open-isas]]
- [[archive/threads/NOTimothyLottes/2022-11-13-my-prefered-method-of-managing-application-data]]
- [[archive/threads/NOTimothyLottes/2022-12-17-rdna3-isa-guide-comments]]
- [[archive/threads/NOTimothyLottes/2023-04-28-https-gpuopen-com-learn-rgp-1-15-enhanced-isa]]
- [[archive/threads/NOTimothyLottes/2023-05-03-found-some-of-my-old-blogs-thread-looking-back-an]]
- [[archive/threads/NOTimothyLottes/2023-06-20-how-about-a-mega-thread-on-the-mechanics-of-cpu]]