1682066496304955393

archive/threads/MissQuickstep/2023-07-20-cache-hit-rate-ps-runs-in-hardware-order-probably/2023-07-21-kenpex-not-only-on-lots-of-hw-the-rop-caches-can-be.md

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+---
+title: "@MissQuickstep Not only."
+type: archive
+source: twitter
+source_url: "https://x.com/kenpex/status/1682284648704143361"
+author: "c0de517e/AngeloPesce"
+handle: kenpex
+post_id: "1682284648704143361"
+date: 2023-07-21
+archived: 2026-08-26
+draft: false
+tags:
+  - archive
+  - twitter
+  - MissQuickstep
+description: "@MissQuickstep Not only."
+in_reply_to: ""
+parent_post_id: "1682066496304955393"
+---
+
+## Source
+
+- URL: https://x.com/kenpex/status/1682284648704143361
+- Author: c0de517e/AngeloPesce (@kenpex)
+- Posted: 2023-07-21 07:01:30
+
+## Branch
+
+**1/** **@kenpex** ^1682284648704143361
+
+**@MissQuickstep**
+
+Not only. On lots of hw the rop caches can be faster/async. That said 10/15x is a lot, way too much. Something is wrong in the setup.
+
+**2/** **@MissQuickstep** ^1682285342177611777
+
+**@kenpex**
+
+Yup - so much that my brain interpreted as %, not x! Seems like it was a shader compiler issue not compiling much of the code to actually execute for the PS:
+https://x.com/MissQuickstep/status/1682272580726673408?t=ckSOFGzItS7VY6tnHLUeBA&s=19
+
+## Related
+
+- Spine: [[archive/threads/MissQuickstep/2023-07-20-cache-hit-rate-ps-runs-in-hardware-order-probably]]

archive/threads/MissQuickstep/2023-07-20-cache-hit-rate-ps-runs-in-hardware-order-probably/2023-07-21-sopyer-could-be-but-with-linear-order-and-linear-layour.md

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+---
+title: "@MissQuickstep Could be, but with linear order and linear layour cs should have coalesced writes and no obvious problems."
+type: archive
+source: twitter
+source_url: "https://x.com/sopyer/status/1682267107675783168"
+author: "Mykhailo Parfeniuk"
+handle: sopyer
+post_id: "1682267107675783168"
+date: 2023-07-21
+archived: 2026-08-26
+draft: false
+tags:
+  - archive
+  - twitter
+  - MissQuickstep
+description: "@MissQuickstep Could be, but with linear order and linear layour cs should have coalesced writes and no obvious problems."
+in_reply_to: ""
+parent_post_id: "1682066496304955393"
+---
+
+## Source
+
+- URL: https://x.com/sopyer/status/1682267107675783168
+- Author: Mykhailo Parfeniuk (@sopyer)
+- Posted: 2023-07-21 05:51:48
+
+## Branch
+
+**1/** **@sopyer** ^1682267107675783168
+
+**@MissQuickstep**
+
+Could be, but with linear order and linear layour cs should have coalesced writes and no obvious problems. I assume buffer swizzling is uncommon. Also PS usage for buffer should have one more hidden cs run for layout change, unless there was memory aliasing.
+
+## Related
+
+- Spine: [[archive/threads/MissQuickstep/2023-07-20-cache-hit-rate-ps-runs-in-hardware-order-probably]]

archive/threads/MissQuickstep/2023-07-20-cache-hit-rate-ps-runs-in-hardware-order-probably/index.md

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+---
+title: "Cache hit rate - PS runs in hardware order (probably Morton Z-Order), CS runs in linear order."
+type: archive
+source: twitter
+source_url: "https://x.com/MissQuickstep/status/1682066496304955393"
+author: "Layla Mah @missquickstep@mastodon.gamedev.place"
+handle: MissQuickstep
+post_id: "1682066496304955393"
+date: 2023-07-20
+archived: 2026-08-26
+draft: false
+tags:
+  - archive
+  - twitter
+  - MissQuickstep
+description: "Cache hit rate - PS runs in hardware order (probably Morton Z-Order), CS runs in linear order."
+in_reply_to: ""
+---
+
+## Source
+
+- URL: https://x.com/MissQuickstep/status/1682066496304955393
+- Author: Layla Mah @missquickstep@mastodon.gamedev.place (@MissQuickstep)
+- Posted: 2023-07-20 16:34:38
+
+## Thread
+
+**1/** **@MissQuickstep** ^1682066496304955393
+
+Cache hit rate - PS runs in hardware order (probably Morton Z-Order), CS runs in linear order.
+
+Branches: [[archive/threads/MissQuickstep/2023-07-20-cache-hit-rate-ps-runs-in-hardware-order-probably/2023-07-21-sopyer-could-be-but-with-linear-order-and-linear-layour]], [[archive/threads/MissQuickstep/2023-07-20-cache-hit-rate-ps-runs-in-hardware-order-probably/2023-07-21-kenpex-not-only-on-lots-of-hw-the-rop-caches-can-be]]
+
+**2/** **@vassvik** ^1682134652050452488
+
+**@MissQuickstep**
+
+Shouldn't make a big difference in practice.  A compute shader has spatial grouping where most waves/warps will sample adjacent memory and hit relatively high bandwidth and cache utilization even in the naive implementations. 
+
+No way 512x512 is BW/cache bound, though
+
+**3/** **@NOTimothyLottes** ^1682136826553745408
+
+**@vassvik** **@MissQuickstep**
+
+You can look at what I did for CAS/FSR1/etc: Simplified {64,1,1} to {8x8} lane remapping (so 4x1 lanes map to a 2x2), semi-persistent waves to avoid wait on store complete for wave relaunch and get better L0$2work mapping, etc. Have to make sure DCC matches (PS vs CS paths). Etc.

archive/threads/MissQuickstep/index.md

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+---
+title: MissQuickstep
+type: note
+draft: false
+description: Archived threads by MissQuickstep.
+tags:
+  - archive
+  - twitter
+  - MissQuickstep
+---
+
+- [[archive/threads/MissQuickstep/2023-07-20-cache-hit-rate-ps-runs-in-hardware-order-probably]]

archive/threads/index.md

@@ -22,6 +22,7 @@ Example of the note shape (single spine, no branches): [[archive/threads/How to
 - [[archive/threads/JohannesVuorine]]
 - [[archive/threads/Jonathan_Blow]]
 - [[archive/threads/KostasAAA]]
+- [[archive/threads/MissQuickstep]]
 - [[archive/threads/MyNameIsMJP]]
 - [[archive/threads/NOTimothyLottes]]
 - [[archive/threads/SebAaltonen]]