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sync atomics "wrapper" procedures
This commit is contained in:
gingerBill
@@ -1,101 +0,0 @@
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package atomics
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// TODO(bill): Use assembly instead here to implement atomics
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// Inline vs external file?
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import "core:sys/win32"
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yield_thread :: proc() { win32.mm_pause(); }
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mfence :: proc() { win32.read_write_barrier(); }
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sfence :: proc() { win32.write_barrier(); }
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lfence :: proc() { win32.read_barrier(); }
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load_i32 :: proc(a: ^i32) -> i32 {
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return a^;
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}
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store_i32 :: proc(a: ^i32, value: i32) {
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a^ = value;
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}
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compare_exchange_i32 :: proc(a: ^i32, expected, desired: i32) -> i32 {
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return win32.interlocked_compare_exchange(a, desired, expected);
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}
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exchanged_i32 :: proc(a: ^i32, desired: i32) -> i32 {
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return win32.interlocked_exchange(a, desired);
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}
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fetch_add_i32 :: proc(a: ^i32, operand: i32) -> i32 {
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return win32.interlocked_exchange_add(a, operand);
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}
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fetch_and_i32 :: proc(a: ^i32, operand: i32) -> i32 {
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return win32.interlocked_and(a, operand);
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}
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fetch_or_i32 :: proc(a: ^i32, operand: i32) -> i32 {
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return win32.interlocked_or(a, operand);
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}
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spin_lock_i32 :: proc(a: ^i32, time_out: int) -> bool { // NOTE(bill) time_out = -1 as default
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old_value := compare_exchange_i32(a, 1, 0);
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counter := 0;
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for old_value != 0 && (time_out < 0 || counter < time_out) {
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counter += 1;
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yield_thread();
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old_value = compare_exchange_i32(a, 1, 0);
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mfence();
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}
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return old_value == 0;
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}
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spin_unlock_i32 :: proc(a: ^i32) {
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store_i32(a, 0);
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mfence();
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}
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try_acquire_lock_i32 :: proc(a: ^i32) -> bool {
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yield_thread();
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old_value := compare_exchange_i32(a, 1, 0);
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mfence();
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return old_value == 0;
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}
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load_i64 :: proc(a: ^i64) -> i64 {
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return a^;
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}
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store_i64 :: proc(a: ^i64, value: i64) {
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a^ = value;
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}
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compare_exchange_i64 :: proc(a: ^i64, expected, desired: i64) -> i64 {
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return win32.interlocked_compare_exchange64(a, desired, expected);
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}
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exchanged_i64 :: proc(a: ^i64, desired: i64) -> i64 {
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return win32.interlocked_exchange64(a, desired);
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}
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fetch_add_i64 :: proc(a: ^i64, operand: i64) -> i64 {
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return win32.interlocked_exchange_add64(a, operand);
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}
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fetch_and_i64 :: proc(a: ^i64, operand: i64) -> i64 {
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return win32.interlocked_and64(a, operand);
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}
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fetch_or_i64 :: proc(a: ^i64, operand: i64) -> i64 {
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return win32.interlocked_or64(a, operand);
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}
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spin_lock_i64 :: proc(a: ^i64, time_out: int) -> bool { // NOTE(bill) time_out = -1 as default
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old_value := compare_exchange_i64(a, 1, 0);
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counter := 0;
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for old_value != 0 && (time_out < 0 || counter < time_out) {
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counter += 1;
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yield_thread();
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old_value = compare_exchange_i64(a, 1, 0);
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mfence();
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}
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return old_value == 0;
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}
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spin_unlock_i64 :: proc(a: ^i64) {
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store_i64(a, 0);
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mfence();
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}
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try_acquire_lock_i64 :: proc(a: ^i64) -> bool {
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yield_thread();
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old_value := compare_exchange_i64(a, 1, 0);
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mfence();
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return old_value == 0;
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}
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@@ -0,0 +1,185 @@
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package sync
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Ordering :: enum {
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Relaxed, // Monotonic
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Release,
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Acquire,
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Acquire_Release,
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Sequentially_Consistent,
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}
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strongest_failure_ordering :: inline proc "contextless" (order: Ordering) -> Ordering {
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using Ordering;
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#complete switch order {
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case Relaxed: return Relaxed;
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case Release: return Relaxed;
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case Acquire: return Acquire;
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case Acquire_Release: return Acquire;
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case Sequentially_Consistent: return Sequentially_Consistent;
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}
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return Relaxed;
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}
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fence :: proc "contextless" (order: Ordering) {
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using Ordering;
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#complete switch order {
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case Relaxed: panic("there is no such thing as a relaxed fence");
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case Release: __atomic_fence_rel();
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case Acquire: __atomic_fence_acq();
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case Acquire_Release: __atomic_fence_acqrel();
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case Sequentially_Consistent: __atomic_fence();
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case: panic("unknown order");
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}
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}
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atomic_store :: proc "contextless" (dst: ^$T, val: T, order: Ordering) {
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using Ordering;
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#complete switch order {
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case Relaxed: __atomic_store_relaxed(dst, val);
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case Release: __atomic_store_rel(dst, val);
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case Sequentially_Consistent: __atomic_store(dst, val);
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case Acquire: panic("there is not such thing as an acquire store");
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case Acquire_Release: panic("there is not such thing as an acquire/release store");
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case: panic("unknown order");
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}
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}
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atomic_load :: proc "contextless" (dst: ^$T, order: Ordering) -> T {
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using Ordering;
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#complete switch order {
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case Relaxed: return __atomic_load_relaxed(dst);
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case Acquire: return __atomic_load_acq(dst);
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case Sequentially_Consistent: return __atomic_load(dst);
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case Release: panic("there is no such thing as a release load");
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case Acquire_Release: panic("there is no such thing as an acquire/release load");
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}
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panic("unknown order");
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return T{};
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}
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atomic_swap :: proc "contextless" (dst: ^$T, val: T, order: Ordering) -> T {
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using Ordering;
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#complete switch order {
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case Relaxed: return __atomic_xchg_relaxed(dst, val);
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case Release: return __atomic_xchg_rel(dst, val);
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case Acquire: return __atomic_xchg_acq(dst, val);
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case Acquire_Release: return __atomic_xchg_acqrel(dst, val);
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case Sequentially_Consistent: return __atomic_xchg(dst, val);
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}
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panic("unknown order");
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return T{};
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}
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atomic_compare_exchange :: proc "contextless" (dst: ^$T, old, new: T, success, failure: Ordering) -> (val: T, ok: bool) {
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using Ordering;
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switch failure {
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case Relaxed:
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switch success {
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case Release: return __atomic_cxchg_rel_failrelaxed(dst, old, new);
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case Relaxed: return __atomic_cxchg_relaxed(dst, old, new);
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case Acquire: return __atomic_cxchg_acq_failrelaxed(dst, old, new);
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case Acquire_Release: return __atomic_cxchg_acqrel_failrelaxed(dst, old, new);
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case Sequentially_Consistent: return __atomic_cxchg_failrelaxed(dst, old, new);
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case: panic("an unknown ordering combination");
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}
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case Acquire:
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switch success {
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case Acquire: return __atomic_cxchg_acq(dst, old, new);
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case Acquire_Release: return __atomic_cxchg_acqrel_failacq(dst, old, new);
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case Sequentially_Consistent: return __atomic_acqrel_failacq(dst, old, new);
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case: panic("an unknown ordering combination");
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}
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case Sequentially_Consistent:
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switch success {
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case Sequentially_Consistent: return __atomic_cxchg(dst, old, new);
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case: panic("an unknown ordering combination");
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}
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case Acquire_Release:
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panic("there is not such thing as an acquire/release failure ordering");
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case Release:
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panic("there is not such thing as an release failure ordering");
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}
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return T{}, false;
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}
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atomic_add :: proc "contextless" (dst: ^$T, val: T, order: Ordering) -> T {
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using Ordering;
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#complete switch order {
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case Relaxed: return __atomic_add_relaxed(dst, val);
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case Release: return __atomic_add_rel(dst, val);
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case Acquire: return __atomic_add_acq(dst, val);
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case Acquire_Release: return __atomic_add_acqrel(dst, val);
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case Sequentially_Consistent: return __atomic_add(dst, val);
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}
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panic("unknown order");
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return T{};
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}
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atomic_sub :: proc "contextless" (dst: ^$T, val: T, order: Ordering) -> T {
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using Ordering;
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#complete switch order {
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case Relaxed: return __atomic_sub_relaxed(dst, val);
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case Release: return __atomic_sub_rel(dst, val);
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case Acquire: return __atomic_sub_acq(dst, val);
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case Acquire_Release: return __atomic_sub_acqrel(dst, val);
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case Sequentially_Consistent: return __atomic_sub(dst, val);
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}
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panic("unknown order");
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return T{};
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}
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atomic_and :: proc "contextless" (dst: ^$T, val: T, order: Ordering) -> T {
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using Ordering;
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#complete switch order {
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case Relaxed: return __atomic_and_relaxed(dst, val);
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case Release: return __atomic_and_rel(dst, val);
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case Acquire: return __atomic_and_acq(dst, val);
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case Acquire_Release: return __atomic_and_acqrel(dst, val);
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case Sequentially_Consistent: return __atomic_and(dst, val);
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}
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panic("unknown order");
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return T{};
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}
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atomic_nand :: proc "contextless" (dst: ^$T, val: T, order: Ordering) -> T {
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using Ordering;
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#complete switch order {
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case Relaxed: return __atomic_nand_relaxed(dst, val);
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case Release: return __atomic_nand_rel(dst, val);
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case Acquire: return __atomic_nand_acq(dst, val);
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case Acquire_Release: return __atomic_nand_acqrel(dst, val);
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case Sequentially_Consistent: return __atomic_nand(dst, val);
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}
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panic("unknown order");
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return T{};
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}
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atomic_or :: proc "contextless" (dst: ^$T, val: T, order: Ordering) -> T {
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using Ordering;
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#complete switch order {
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case Relaxed: return __atomic_or_relaxed(dst, val);
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case Release: return __atomic_or_rel(dst, val);
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case Acquire: return __atomic_or_acq(dst, val);
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case Acquire_Release: return __atomic_or_acqrel(dst, val);
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case Sequentially_Consistent: return __atomic_or(dst, val);
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}
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panic("unknown order");
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return T{};
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}
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atomic_xor :: proc "contextless" (dst: ^$T, val: T, order: Ordering) -> T {
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using Ordering;
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#complete switch order {
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case Relaxed: return __atomic_xor_relaxed(dst, val);
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case Release: return __atomic_xor_rel(dst, val);
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case Acquire: return __atomic_xor_acq(dst, val);
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case Acquire_Release: return __atomic_xor_acqrel(dst, val);
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case Sequentially_Consistent: return __atomic_xor(dst, val);
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}
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panic("unknown order");
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return T{};
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}
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@@ -1,7 +1,6 @@
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package sync
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import "core:sys/win32"
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import "core:atomics"
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Semaphore :: struct {
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_handle: win32.Handle,
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@@ -17,7 +17,6 @@ import "core:c"
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import "core:runtime"
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when os.OS == "windows" {
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import "core:atomics"
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import "core:sync"
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import "core:thread"
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import "core:sys/win32"
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