// Copyright (c) Epic Games Tools
// Licensed under the MIT license (https://opensource.org/license/mit/)

////////////////////////////////
//~ rjf: X64 Tables

@table(name size usage)
REGS_RegTableX64:
{
  {rax                            64   Normal}
  {rcx                            64   Normal}
  {rdx                            64   Normal}
  {rbx                            64   Normal}
  {rsp                            64   Normal}
  {rbp                            64   Normal}
  {rsi                            64   Normal}
  {rdi                            64   Normal}
  {r8                             64   Normal}
  {r9                             64   Normal}
  {r10                            64   Normal}
  {r11                            64   Normal}
  {r12                            64   Normal}
  {r13                            64   Normal}
  {r14                            64   Normal}
  {r15                            64   Normal}
  {fsbase                         64   Normal}
  {gsbase                         64   Normal}
  {rip                            64   Normal}
  {rflags                         64   Normal}
  {dr0                            64   Normal}
  {dr1                            64   Normal}
  {dr2                            64   Normal}
  {dr3                            64   Normal}
  {dr4                            64   Normal}
  {dr5                            64   Normal}
  {dr6                            64   Normal}
  {dr7                            64   Normal}
  {st0                            80   Normal}
  {st1                            80   Normal}
  {st2                            80   Normal}
  {st3                            80   Normal}
  {st4                            80   Normal}
  {st5                            80   Normal}
  {st6                            80   Normal}
  {st7                            80   Normal}
  {fcw                            16   Normal}
  {fsw                            16   Normal}
  {ftw                            8    Normal}
  {fop                            16   Normal}
  {fip                            64   Normal}
  {fdp                            64   Normal}
  {mxcsr                          32   Normal}
  {mxcsr_mask                     32   Normal}
  {ss                             16   Normal}
  {cs                             16   Normal}
  {ds                             16   Normal}
  {es                             16   Normal}
  {fs                             16   Normal}
  {gs                             16   Normal}
  {zmm0                           512  Vector}
  {zmm1                           512  Vector}
  {zmm2                           512  Vector}
  {zmm3                           512  Vector}
  {zmm4                           512  Vector}
  {zmm5                           512  Vector}
  {zmm6                           512  Vector}
  {zmm7                           512  Vector}
  {zmm8                           512  Vector}
  {zmm9                           512  Vector}
  {zmm10                          512  Vector}
  {zmm11                          512  Vector}
  {zmm12                          512  Vector}
  {zmm13                          512  Vector}
  {zmm14                          512  Vector}
  {zmm15                          512  Vector}
  {zmm16                          512  Vector}
  {zmm17                          512  Vector}
  {zmm18                          512  Vector}
  {zmm19                          512  Vector}
  {zmm20                          512  Vector}
  {zmm21                          512  Vector}
  {zmm22                          512  Vector}
  {zmm23                          512  Vector}
  {zmm24                          512  Vector}
  {zmm25                          512  Vector}
  {zmm26                          512  Vector}
  {zmm27                          512  Vector}
  {zmm28                          512  Vector}
  {zmm29                          512  Vector}
  {zmm30                          512  Vector}
  {zmm31                          512  Vector}
  {k0                             64   Normal}
  {k1                             64   Normal}
  {k2                             64   Normal}
  {k3                             64   Normal}
  {k4                             64   Normal}
  {k5                             64   Normal}
  {k6                             64   Normal}
  {k7                             64   Normal}
  {cetmsr                         64   Normal}
  {cetssp                         64   Normal}
}

@table(name base off size usage)
REGS_AliasTableX64:
{
  {eax             rax    0      32     Normal}
  {ecx             rcx    0      32     Normal}
  {edx             rdx    0      32     Normal}
  {ebx             rbx    0      32     Normal}
  {esp             rsp    0      32     Normal}
  {ebp             rbp    0      32     Normal}
  {esi             rsi    0      32     Normal}
  {edi             rdi    0      32     Normal}
  {r8d             r8     0      32     Normal}
  {r9d             r9     0      32     Normal}
  {r10d            r10    0      32     Normal}
  {r11d            r11    0      32     Normal}
  {r12d            r12    0      32     Normal}
  {r13d            r13    0      32     Normal}
  {r14d            r14    0      32     Normal}
  {r15d            r15    0      32     Normal}
  {eflags          rflags 0      32     Normal}
  {ax              rax    0      16     Normal}
  {cx              rcx    0      16     Normal}
  {dx              rdx    0      16     Normal}
  {bx              rbx    0      16     Normal}
  {si              rsi    0      16     Normal}
  {di              rdi    0      16     Normal}
  {sp              rsp    0      16     Normal}
  {bp              rbp    0      16     Normal}
  {ip              rip    0      16     Normal}
  {r8w             r8     0      16     Normal}
  {r9w             r9     0      16     Normal}
  {r10w            r10    0      16     Normal}
  {r11w            r11    0      16     Normal}
  {r12w            r12    0      16     Normal}
  {r13w            r13    0      16     Normal}
  {r14w            r14    0      16     Normal}
  {r15w            r15    0      16     Normal}
  {al              rax    0      8      Normal}
  {cl              rcx    0      8      Normal}
  {dl              rdx    0      8      Normal}
  {bl              rbx    0      8      Normal}
  {sil             rsi    0      8      Normal}
  {dil             rdi    0      8      Normal}
  {bpl             rbp    0      8      Normal}
  {spl             rsp    0      8      Normal}
  {r8b             r8     0      8      Normal}
  {r9b             r9     0      8      Normal}
  {r10b            r10    0      8      Normal}
  {r11b            r11    0      8      Normal}
  {r12b            r12    0      8      Normal}
  {r13b            r13    0      8      Normal}
  {r14b            r14    0      8      Normal}
  {r15b            r15    0      8      Normal}
  {ah              rax    8      8      Normal}
  {ch              rcx    8      8      Normal}
  {dh              rdx    8      8      Normal}
  {bh              rbx    8      8      Normal}
  {xmm0            zmm0   0      128    Vector}
  {xmm1            zmm1   0      128    Vector}
  {xmm2            zmm2   0      128    Vector}
  {xmm3            zmm3   0      128    Vector}
  {xmm4            zmm4   0      128    Vector}
  {xmm5            zmm5   0      128    Vector}
  {xmm6            zmm6   0      128    Vector}
  {xmm7            zmm7   0      128    Vector}
  {xmm8            zmm8   0      128    Vector}
  {xmm9            zmm9   0      128    Vector}
  {xmm10           zmm10  0      128    Vector}
  {xmm11           zmm11  0      128    Vector}
  {xmm12           zmm12  0      128    Vector}
  {xmm13           zmm13  0      128    Vector}
  {xmm14           zmm14  0      128    Vector}
  {xmm15           zmm15  0      128    Vector}
  {ymm0            zmm0   0      256    Vector}
  {ymm1            zmm1   0      256    Vector}
  {ymm2            zmm2   0      256    Vector}
  {ymm3            zmm3   0      256    Vector}
  {ymm4            zmm4   0      256    Vector}
  {ymm5            zmm5   0      256    Vector}
  {ymm6            zmm6   0      256    Vector}
  {ymm7            zmm7   0      256    Vector}
  {ymm8            zmm8   0      256    Vector}
  {ymm9            zmm9   0      256    Vector}
  {ymm10           zmm10  0      256    Vector}
  {ymm11           zmm11  0      256    Vector}
  {ymm12           zmm12  0      256    Vector}
  {ymm13           zmm13  0      256    Vector}
  {ymm14           zmm14  0      256    Vector}
  {ymm15           zmm15  0      256    Vector}
  {mm0             st0    0      64     Vector}
  {mm1             st1    0      64     Vector}
  {mm2             st2    0      64     Vector}
  {mm3             st3    0      64     Vector}
  {mm4             st4    0      64     Vector}
  {mm5             st5    0      64     Vector}
  {mm6             st6    0      64     Vector}
  {mm7             st7    0      64     Vector}
}

////////////////////////////////
//~ rjf: Architecture Tables

@table(name, name_lower)
REGS_ArchTable:
{
  {X64 x64}
}

////////////////////////////////
//~ rjf: X64 Generators

@enum REGS_RegCodeX64:
{
  NULL,
  @expand(REGS_RegTableX64 a) `$(a.name)`,
  COUNT,
}

@enum REGS_AliasCodeX64:
{
  NULL,
  @expand(REGS_AliasTableX64 a) `$(a.name)`,
  COUNT,
}

@struct REGS_RegBlockX64:
{
  @expand(REGS_RegTableX64 a) `REGS_Reg$(a.size) $(a.name)`,
}

@data(REGS_UsageKind) regs_g_reg_code_x64_usage_kind_table:
{
  `REGS_UsageKind_Normal`;
  @expand(REGS_RegTableX64 a) `REGS_UsageKind_$(a.usage)`;
}

@data(REGS_UsageKind)
regs_g_alias_code_x64_usage_kind_table:
{
  `REGS_UsageKind_Normal`;
  @expand(REGS_AliasTableX64 a) `REGS_UsageKind_$(a.usage)`;
}

@data(String8) regs_g_reg_code_x64_string_table:
{
  `str8_lit_comp("")`;
  @expand(REGS_RegTableX64 a) `str8_lit_comp("$(a.name)")`;
}

@data(String8) regs_g_alias_code_x64_string_table:
{
  `str8_lit_comp("")`;
  @expand(REGS_AliasTableX64 a) `str8_lit_comp("$(a.name)")`;
}

@data(REGS_Rng) regs_g_reg_code_x64_rng_table:
{
  `{0}`;
  @expand(REGS_RegTableX64 a) `{(U16)OffsetOf(REGS_RegBlockX64, $(a.name)), $(a.size/8)}`,
}

@data(REGS_Slice) regs_g_alias_code_x64_slice_table:
{
  `{0}`;
  @expand(REGS_AliasTableX64 a) `{REGS_RegCodeX64_$(a.base), $(a.off/8), $(a.size/8)}`,
}

////////////////////////////////
//~ rjf: Architecture-Dynamic Helper Implementation Generators

@c_file @gen
{
  `internal U64 regs_block_size_from_arch(Arch arch)`;
  `{`;
    `U64 result = 8;`;
    `switch(arch)`;
    `{`;
      `default:{}break;`;
      @expand(REGS_ArchTable a) `case Arch_$(a.name_lower):{result = sizeof(REGS_RegBlock$(a.name));}break;`;
      `}`;
    `return result;`;
    `}`;
}

@c_file @gen
{
  `internal U64 regs_reg_code_count_from_arch(Arch arch)`;
  `{`;
    `U64 result = 0;`;
    `switch(arch)`;
    `{`;
      `default:{}break;`;
      @expand(REGS_ArchTable a) `case Arch_$(a.name_lower):{result = REGS_RegCode$(a.name)_COUNT;}break;`;
      `}`;
    `return result;`;
    `}`;
}

@c_file @gen
{
  `internal U64 regs_alias_code_count_from_arch(Arch arch)`;
  `{`;
    `U64 result = 0;`;
    `switch(arch)`;
    `{`;
      `default:{}break;`;
      @expand(REGS_ArchTable a) `case Arch_$(a.name_lower):{result = REGS_AliasCode$(a.name)_COUNT;}break;`;
      `}`;
    `return result;`;
    `}`;
}

@c_file @gen
{
  `internal String8 *regs_reg_code_string_table_from_arch(Arch arch)`;
  `{`;
    `String8 *result = 0;`;
    `switch(arch)`;
    `{`;
      `default:{}break;`;
      @expand(REGS_ArchTable a) `case Arch_$(a.name_lower):{result = regs_g_reg_code_$(a.name_lower)_string_table;}break;`;
      `}`;
    `return result;`;
    `}`;
}

@c_file @gen
{
  `internal String8 *regs_alias_code_string_table_from_arch(Arch arch)`;
  `{`;
    `String8 *result = 0;`;
    `switch(arch)`;
    `{`;
      `default:{}break;`;
      @expand(REGS_ArchTable a) `case Arch_$(a.name_lower):{result = regs_g_alias_code_$(a.name_lower)_string_table;}break;`;
      `}`;
    `return result;`;
    `}`;
}

@c_file @gen
{
  `internal REGS_Rng *regs_reg_code_rng_table_from_arch(Arch arch)`;
  `{`;
    `REGS_Rng *result = 0;`;
    `switch(arch)`;
    `{`;
      `default:{}break;`;
      @expand(REGS_ArchTable a) `case Arch_$(a.name_lower):{result = regs_g_reg_code_$(a.name_lower)_rng_table;}break;`;
      `}`;
    `return result;`;
    `}`;
}

@c_file @gen
{
  `internal REGS_Slice *regs_alias_code_slice_table_from_arch(Arch arch)`;
  `{`;
    `REGS_Slice *result = 0;`;
    `switch(arch)`;
    `{`;
      `default:{}break;`;
      @expand(REGS_ArchTable a) `case Arch_$(a.name_lower):{result = regs_g_alias_code_$(a.name_lower)_slice_table;}break;`;
      `}`;
    `return result;`;
    `}`;
}

@c_file @gen
{
  `internal REGS_UsageKind *regs_reg_code_usage_kind_table_from_arch(Arch arch)`;
  `{`;
    `REGS_UsageKind *result = 0;`;
    `switch(arch)`;
    `{`;
      `default:{}break;`;
      @expand(REGS_ArchTable a) `case Arch_$(a.name_lower):{result = regs_g_reg_code_$(a.name_lower)_usage_kind_table;}break;`;
      `}`;
    `return result;`;
    `}`;
}

@c_file @gen
{
  `internal REGS_UsageKind *regs_alias_code_usage_kind_table_from_arch(Arch arch)`;
  `{`;
    `REGS_UsageKind *result = 0;`;
    `switch(arch)`;
    `{`;
      `default:{}break;`;
      @expand(REGS_ArchTable a) `case Arch_$(a.name_lower):{result = regs_g_alias_code_$(a.name_lower)_usage_kind_table;}break;`;
      `}`;
    `return result;`;
    `}`;
}