ed/raddebugger
1
0
Fork 0
mirror of https://github.com/Ed94/raddebugger.git synced 2026-08-14 17:28:07 +00:00
Code Issues Packages Projects Releases Wiki Activity

add TR and LDTR registers

Browse Source
This commit is contained in:
Nikita Smith
2025-11-07 14:39:45 -08:00
committed by Ryan Fleury
parent 88b79b2b6a
commit ecbce1efdf
7 changed files with 63 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/dwarf/dwarf.h
+7 -7
View File
@@ -1635,8 +1635,8 @@ X(Ss, 42, ss, 0, 2) \
X(Ds, 43, ds, 0, 2) \
X(Fs, 44, fs, 0, 2) \
X(Gs, 45, gs, 0, 2) \
X(Tr, 48, nil, 0, 0) \
X(Ldtr, 49, nil, 0, 0)
X(Tr, 48, tr, 0, 0) \
X(Ldtr, 49, ldtr, 0, 0)
#define DW_Regs_X64_XList(X) \
X(Rax, 0, rax, 0, 8) \
@@ -1711,10 +1711,10 @@ X(Ss, 52, ss, 0, 2) \
X(Ds, 53, ds, 0, 2) \
X(Fs, 54, fs, 0, 2) \
X(Gs, 55, gs, 0, 2) \
X(FsBase, 58, nil, 0, 0) \
X(GsBase, 59, nil, 0, 0) \
X(Tr, 62, nil, 0, 0) \
X(Ldtr, 63, nil, 0, 0)
X(FsBase, 58, fsbase, 0, 0) \
X(GsBase, 59, gsbase, 0, 0) \
X(Tr, 62, tr, 0, 0) \
X(Ldtr, 63, ldtr, 0, 0)
typedef U32 DW_Reg;
@@ -1744,8 +1744,8 @@ internal U64 dw_reg_size_from_code_x64(DW_Reg reg_code);
internal U64 dw_reg_pos_from_code_x64(DW_Reg reg_code);
internal U64 dw_reg_size_from_code(Arch arch, DW_Reg reg_code);
internal U64 dw_reg_pos_from_code(Arch arch, DW_Reg reg_code);
internal U64 dw_reg_max_size_from_arch(Arch arch);
internal U64 dw_reg_count_from_arch(Arch arch);
internal U64 dw_reg_max_size_from_arch(Arch arch);
//- Attrib Class Encodings
src/lib_rdi/rdi.h
+8
View File
@@ -206,6 +206,8 @@ RDI_RegCodeX86_ymm4 = 57,
RDI_RegCodeX86_ymm5 = 58,
RDI_RegCodeX86_ymm6 = 59,
RDI_RegCodeX86_ymm7 = 60,
RDI_RegCodeX86_tr = 61,
RDI_RegCodeX86_ldtr = 62,
} RDI_RegCodeX86Enum;
typedef RDI_U8 RDI_RegCodeX64;
@@ -314,6 +316,8 @@ RDI_RegCodeX64_fdp = 99,
RDI_RegCodeX64_mxcsr_mask = 100,
RDI_RegCodeX64_cetmsr = 101,
RDI_RegCodeX64_cetssp = 102,
RDI_RegCodeX64_tr = 103,
RDI_RegCodeX64_ldtr = 104,
} RDI_RegCodeX64Enum;
typedef RDI_U32 RDI_BinarySectionFlags;
@@ -699,6 +703,8 @@ X(ymm4, 57)\
X(ymm5, 58)\
X(ymm6, 59)\
X(ymm7, 60)\
X(tr, 61)\
X(ldtr, 62)\
#define RDI_RegCodeX64_XList \
X(nil, 0)\
@@ -804,6 +810,8 @@ X(fdp, 99)\
X(mxcsr_mask, 100)\
X(cetmsr, 101)\
X(cetssp, 102)\
X(tr, 103)\
X(ldtr, 104)\
#define RDI_TopLevelInfo_XList \
X(RDI_Arch, arch)\
src/rdi/rdi.mdesk
+4
View File
@@ -346,6 +346,8 @@ RDI_RegCodeX86Table:
{ymm5 58}
{ymm6 59}
{ymm7 60}
{tr 61}
{ldtr 62}
}
@table(name value)
@@ -454,6 +456,8 @@ RDI_RegCodeX64Table:
{mxcsr_mask 100}
{cetmsr 101}
{cetssp 102}
{tr 103}
{ldtr 104}
}
@enum(RDI_U32) RDI_Arch:
src/regs/generated/regs.meta.c
+18 -6
View File
@@ -103,7 +103,7 @@ case Arch_x86:{result = regs_g_alias_code_x86_usage_kind_table;}break;
return result;
}
C_LINKAGE_BEGIN
REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[103] =
REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[105] =
{
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
@@ -208,6 +208,8 @@ REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
};
REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[96] =
@@ -310,7 +312,7 @@ REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
};
String8 regs_g_reg_code_x64_string_table[103] =
String8 regs_g_reg_code_x64_string_table[105] =
{
str8_lit_comp(""),
str8_lit_comp("rax"),
@@ -415,6 +417,8 @@ str8_lit_comp("k6"),
str8_lit_comp("k7"),
str8_lit_comp("cetmsr"),
str8_lit_comp("cetssp"),
str8_lit_comp("tr"),
str8_lit_comp("ldtr"),
};
String8 regs_g_alias_code_x64_string_table[96] =
@@ -517,7 +521,7 @@ str8_lit_comp("mm6"),
str8_lit_comp("mm7"),
};
REGS_Rng regs_g_reg_code_x64_rng_table[103] =
REGS_Rng regs_g_reg_code_x64_rng_table[105] =
{
{0},
{(U16)OffsetOf(REGS_RegBlockX64, rax), 8},
@@ -622,6 +626,8 @@ REGS_Rng regs_g_reg_code_x64_rng_table[103] =
{(U16)OffsetOf(REGS_RegBlockX64, k7), 8},
{(U16)OffsetOf(REGS_RegBlockX64, cetmsr), 8},
{(U16)OffsetOf(REGS_RegBlockX64, cetssp), 8},
{(U16)OffsetOf(REGS_RegBlockX64, tr), 2},
{(U16)OffsetOf(REGS_RegBlockX64, ldtr), 2},
};
REGS_Slice regs_g_alias_code_x64_slice_table[96] =
@@ -724,7 +730,7 @@ REGS_Slice regs_g_alias_code_x64_slice_table[96] =
{REGS_RegCodeX64_fpr7, 0, 8},
};
REGS_UsageKind regs_g_reg_code_x86_usage_kind_table[61] =
REGS_UsageKind regs_g_reg_code_x86_usage_kind_table[63] =
{
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
@@ -779,6 +785,8 @@ REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Normal,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
@@ -829,7 +837,7 @@ REGS_UsageKind_Vector,
REGS_UsageKind_Vector,
};
String8 regs_g_reg_code_x86_string_table[61] =
String8 regs_g_reg_code_x86_string_table[63] =
{
str8_lit_comp(""),
str8_lit_comp("eax"),
@@ -884,6 +892,8 @@ str8_lit_comp("ds"),
str8_lit_comp("es"),
str8_lit_comp("fs"),
str8_lit_comp("gs"),
str8_lit_comp("tr"),
str8_lit_comp("ldtr"),
str8_lit_comp("ymm0"),
str8_lit_comp("ymm1"),
str8_lit_comp("ymm2"),
@@ -934,7 +944,7 @@ str8_lit_comp("mm6"),
str8_lit_comp("mm7"),
};
REGS_Rng regs_g_reg_code_x86_rng_table[61] =
REGS_Rng regs_g_reg_code_x86_rng_table[63] =
{
{0},
{(U16)OffsetOf(REGS_RegBlockX86, eax), 4},
@@ -989,6 +999,8 @@ REGS_Rng regs_g_reg_code_x86_rng_table[61] =
{(U16)OffsetOf(REGS_RegBlockX86, es), 2},
{(U16)OffsetOf(REGS_RegBlockX86, fs), 2},
{(U16)OffsetOf(REGS_RegBlockX86, gs), 2},
{(U16)OffsetOf(REGS_RegBlockX86, tr), 2},
{(U16)OffsetOf(REGS_RegBlockX86, ldtr), 2},
{(U16)OffsetOf(REGS_RegBlockX86, ymm0), 32},
{(U16)OffsetOf(REGS_RegBlockX86, ymm1), 32},
{(U16)OffsetOf(REGS_RegBlockX86, ymm2), 32},
src/regs/generated/regs.meta.h
+14 -6
View File
@@ -111,6 +111,8 @@ REGS_RegCodeX64_k6,
REGS_RegCodeX64_k7,
REGS_RegCodeX64_cetmsr,
REGS_RegCodeX64_cetssp,
REGS_RegCodeX64_tr,
REGS_RegCodeX64_ldtr,
REGS_RegCodeX64_COUNT,
} REGS_RegCodeX64;
@@ -270,6 +272,8 @@ REGS_RegCodeX86_ds,
REGS_RegCodeX86_es,
REGS_RegCodeX86_fs,
REGS_RegCodeX86_gs,
REGS_RegCodeX86_tr,
REGS_RegCodeX86_ldtr,
REGS_RegCodeX86_ymm0,
REGS_RegCodeX86_ymm1,
REGS_RegCodeX86_ymm2,
@@ -427,6 +431,8 @@ REGS_Reg64 k6;
REGS_Reg64 k7;
REGS_Reg64 cetmsr;
REGS_Reg64 cetssp;
REGS_Reg16 tr;
REGS_Reg16 ldtr;
};
typedef struct REGS_RegBlockX86 REGS_RegBlockX86;
@@ -484,6 +490,8 @@ REGS_Reg16 ds;
REGS_Reg16 es;
REGS_Reg16 fs;
REGS_Reg16 gs;
REGS_Reg16 tr;
REGS_Reg16 ldtr;
REGS_Reg256 ymm0;
REGS_Reg256 ymm1;
REGS_Reg256 ymm2;
@@ -495,17 +503,17 @@ REGS_Reg256 ymm7;
};
C_LINKAGE_BEGIN
extern REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[103];
extern REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[105];
extern REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[96];
extern String8 regs_g_reg_code_x64_string_table[103];
extern String8 regs_g_reg_code_x64_string_table[105];
extern String8 regs_g_alias_code_x64_string_table[96];
extern REGS_Rng regs_g_reg_code_x64_rng_table[103];
extern REGS_Rng regs_g_reg_code_x64_rng_table[105];
extern REGS_Slice regs_g_alias_code_x64_slice_table[96];
extern REGS_UsageKind regs_g_reg_code_x86_usage_kind_table[61];
extern REGS_UsageKind regs_g_reg_code_x86_usage_kind_table[63];
extern REGS_UsageKind regs_g_alias_code_x86_usage_kind_table[36];
extern String8 regs_g_reg_code_x86_string_table[61];
extern String8 regs_g_reg_code_x86_string_table[63];
extern String8 regs_g_alias_code_x86_string_table[36];
extern REGS_Rng regs_g_reg_code_x86_rng_table[61];
extern REGS_Rng regs_g_reg_code_x86_rng_table[63];
extern REGS_Slice regs_g_alias_code_x86_slice_table[36];
C_LINKAGE_END
src/regs/rdi/generated/regs_rdi.meta.c
+8
View File
@@ -116,6 +116,8 @@ case REGS_RegCodeX64_k6:{result = RDI_RegCodeX64_k6;}break;
case REGS_RegCodeX64_k7:{result = RDI_RegCodeX64_k7;}break;
case REGS_RegCodeX64_cetmsr:{result = RDI_RegCodeX64_cetmsr;}break;
case REGS_RegCodeX64_cetssp:{result = RDI_RegCodeX64_cetssp;}break;
case REGS_RegCodeX64_tr:{result = RDI_RegCodeX64_tr;}break;
case REGS_RegCodeX64_ldtr:{result = RDI_RegCodeX64_ldtr;}break;
}
}break;
case Arch_x86:
@@ -175,6 +177,8 @@ case REGS_RegCodeX86_ds:{result = RDI_RegCodeX86_ds;}break;
case REGS_RegCodeX86_es:{result = RDI_RegCodeX86_es;}break;
case REGS_RegCodeX86_fs:{result = RDI_RegCodeX86_fs;}break;
case REGS_RegCodeX86_gs:{result = RDI_RegCodeX86_gs;}break;
case REGS_RegCodeX86_tr:{result = RDI_RegCodeX86_tr;}break;
case REGS_RegCodeX86_ldtr:{result = RDI_RegCodeX86_ldtr;}break;
case REGS_RegCodeX86_ymm0:{result = RDI_RegCodeX86_ymm0;}break;
case REGS_RegCodeX86_ymm1:{result = RDI_RegCodeX86_ymm1;}break;
case REGS_RegCodeX86_ymm2:{result = RDI_RegCodeX86_ymm2;}break;
@@ -301,6 +305,8 @@ case RDI_RegCodeX64_k6:{result = REGS_RegCodeX64_k6;}break;
case RDI_RegCodeX64_k7:{result = REGS_RegCodeX64_k7;}break;
case RDI_RegCodeX64_cetmsr:{result = REGS_RegCodeX64_cetmsr;}break;
case RDI_RegCodeX64_cetssp:{result = REGS_RegCodeX64_cetssp;}break;
case RDI_RegCodeX64_tr:{result = REGS_RegCodeX64_tr;}break;
case RDI_RegCodeX64_ldtr:{result = REGS_RegCodeX64_ldtr;}break;
}
}break;
case Arch_x86:
@@ -360,6 +366,8 @@ case RDI_RegCodeX86_ds:{result = REGS_RegCodeX86_ds;}break;
case RDI_RegCodeX86_es:{result = REGS_RegCodeX86_es;}break;
case RDI_RegCodeX86_fs:{result = REGS_RegCodeX86_fs;}break;
case RDI_RegCodeX86_gs:{result = REGS_RegCodeX86_gs;}break;
case RDI_RegCodeX86_tr:{result = REGS_RegCodeX86_tr;}break;
case RDI_RegCodeX86_ldtr:{result = REGS_RegCodeX86_ldtr;}break;
case RDI_RegCodeX86_ymm0:{result = REGS_RegCodeX86_ymm0;}break;
case RDI_RegCodeX86_ymm1:{result = REGS_RegCodeX86_ymm1;}break;
case RDI_RegCodeX86_ymm2:{result = REGS_RegCodeX86_ymm2;}break;
src/regs/regs.mdesk
+4
View File
@@ -109,6 +109,8 @@ REGS_RegTableX64:
{k7 64 Normal}
{cetmsr 64 Normal}
{cetssp 64 Normal}
{tr 16 Normal}
{ldtr 16 Normal}
}
@table(name base off size usage)
@@ -277,6 +279,8 @@ REGS_RegTableX86:
{es 16 Normal}
{fs 16 Normal}
{gs 16 Normal}
{tr 16 Normal}
{ldtr 16 Normal}
// SIMD REGISTERS
{ymm0 256 Vector}
{ymm1 256 Vector}