mirror of
https://github.com/Ed94/raddebugger.git
synced 2026-08-05 13:28:40 +00:00
avx512 registers & fixes for getting & setting x64 context
This commit is contained in:
committed by
Ryan Fleury
parent
14759e49e9
commit
ce7c8d5244
@@ -74,22 +74,46 @@ case REGS_RegCodeX64_ds:{result = RDI_RegCodeX64_ds;}break;
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case REGS_RegCodeX64_es:{result = RDI_RegCodeX64_es;}break;
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case REGS_RegCodeX64_fs:{result = RDI_RegCodeX64_fs;}break;
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case REGS_RegCodeX64_gs:{result = RDI_RegCodeX64_gs;}break;
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case REGS_RegCodeX64_ymm0:{result = RDI_RegCodeX64_ymm0;}break;
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case REGS_RegCodeX64_ymm1:{result = RDI_RegCodeX64_ymm1;}break;
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case REGS_RegCodeX64_ymm2:{result = RDI_RegCodeX64_ymm2;}break;
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case REGS_RegCodeX64_ymm3:{result = RDI_RegCodeX64_ymm3;}break;
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case REGS_RegCodeX64_ymm4:{result = RDI_RegCodeX64_ymm4;}break;
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case REGS_RegCodeX64_ymm5:{result = RDI_RegCodeX64_ymm5;}break;
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case REGS_RegCodeX64_ymm6:{result = RDI_RegCodeX64_ymm6;}break;
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case REGS_RegCodeX64_ymm7:{result = RDI_RegCodeX64_ymm7;}break;
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case REGS_RegCodeX64_ymm8:{result = RDI_RegCodeX64_ymm8;}break;
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case REGS_RegCodeX64_ymm9:{result = RDI_RegCodeX64_ymm9;}break;
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case REGS_RegCodeX64_ymm10:{result = RDI_RegCodeX64_ymm10;}break;
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case REGS_RegCodeX64_ymm11:{result = RDI_RegCodeX64_ymm11;}break;
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case REGS_RegCodeX64_ymm12:{result = RDI_RegCodeX64_ymm12;}break;
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case REGS_RegCodeX64_ymm13:{result = RDI_RegCodeX64_ymm13;}break;
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case REGS_RegCodeX64_ymm14:{result = RDI_RegCodeX64_ymm14;}break;
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case REGS_RegCodeX64_ymm15:{result = RDI_RegCodeX64_ymm15;}break;
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case REGS_RegCodeX64_zmm0:{result = RDI_RegCodeX64_zmm0;}break;
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case REGS_RegCodeX64_zmm1:{result = RDI_RegCodeX64_zmm1;}break;
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case REGS_RegCodeX64_zmm2:{result = RDI_RegCodeX64_zmm2;}break;
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case REGS_RegCodeX64_zmm3:{result = RDI_RegCodeX64_zmm3;}break;
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case REGS_RegCodeX64_zmm4:{result = RDI_RegCodeX64_zmm4;}break;
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case REGS_RegCodeX64_zmm5:{result = RDI_RegCodeX64_zmm5;}break;
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case REGS_RegCodeX64_zmm6:{result = RDI_RegCodeX64_zmm6;}break;
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case REGS_RegCodeX64_zmm7:{result = RDI_RegCodeX64_zmm7;}break;
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case REGS_RegCodeX64_zmm8:{result = RDI_RegCodeX64_zmm8;}break;
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case REGS_RegCodeX64_zmm9:{result = RDI_RegCodeX64_zmm9;}break;
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case REGS_RegCodeX64_zmm10:{result = RDI_RegCodeX64_zmm10;}break;
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case REGS_RegCodeX64_zmm11:{result = RDI_RegCodeX64_zmm11;}break;
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case REGS_RegCodeX64_zmm12:{result = RDI_RegCodeX64_zmm12;}break;
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case REGS_RegCodeX64_zmm13:{result = RDI_RegCodeX64_zmm13;}break;
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case REGS_RegCodeX64_zmm14:{result = RDI_RegCodeX64_zmm14;}break;
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case REGS_RegCodeX64_zmm15:{result = RDI_RegCodeX64_zmm15;}break;
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case REGS_RegCodeX64_zmm16:{result = RDI_RegCodeX64_zmm16;}break;
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case REGS_RegCodeX64_zmm17:{result = RDI_RegCodeX64_zmm17;}break;
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case REGS_RegCodeX64_zmm18:{result = RDI_RegCodeX64_zmm18;}break;
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case REGS_RegCodeX64_zmm19:{result = RDI_RegCodeX64_zmm19;}break;
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case REGS_RegCodeX64_zmm20:{result = RDI_RegCodeX64_zmm20;}break;
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case REGS_RegCodeX64_zmm21:{result = RDI_RegCodeX64_zmm21;}break;
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case REGS_RegCodeX64_zmm22:{result = RDI_RegCodeX64_zmm22;}break;
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case REGS_RegCodeX64_zmm23:{result = RDI_RegCodeX64_zmm23;}break;
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case REGS_RegCodeX64_zmm24:{result = RDI_RegCodeX64_zmm24;}break;
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case REGS_RegCodeX64_zmm25:{result = RDI_RegCodeX64_zmm25;}break;
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case REGS_RegCodeX64_zmm26:{result = RDI_RegCodeX64_zmm26;}break;
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case REGS_RegCodeX64_zmm27:{result = RDI_RegCodeX64_zmm27;}break;
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case REGS_RegCodeX64_zmm28:{result = RDI_RegCodeX64_zmm28;}break;
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case REGS_RegCodeX64_zmm29:{result = RDI_RegCodeX64_zmm29;}break;
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case REGS_RegCodeX64_zmm30:{result = RDI_RegCodeX64_zmm30;}break;
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case REGS_RegCodeX64_zmm31:{result = RDI_RegCodeX64_zmm31;}break;
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case REGS_RegCodeX64_k0:{result = RDI_RegCodeX64_k0;}break;
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case REGS_RegCodeX64_k1:{result = RDI_RegCodeX64_k1;}break;
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case REGS_RegCodeX64_k2:{result = RDI_RegCodeX64_k2;}break;
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case REGS_RegCodeX64_k3:{result = RDI_RegCodeX64_k3;}break;
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case REGS_RegCodeX64_k4:{result = RDI_RegCodeX64_k4;}break;
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case REGS_RegCodeX64_k5:{result = RDI_RegCodeX64_k5;}break;
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case REGS_RegCodeX64_k6:{result = RDI_RegCodeX64_k6;}break;
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case REGS_RegCodeX64_k7:{result = RDI_RegCodeX64_k7;}break;
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}
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}break;
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case Architecture_x86:
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@@ -233,22 +257,46 @@ case RDI_RegCodeX64_ds:{result = REGS_RegCodeX64_ds;}break;
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case RDI_RegCodeX64_es:{result = REGS_RegCodeX64_es;}break;
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case RDI_RegCodeX64_fs:{result = REGS_RegCodeX64_fs;}break;
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case RDI_RegCodeX64_gs:{result = REGS_RegCodeX64_gs;}break;
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case RDI_RegCodeX64_ymm0:{result = REGS_RegCodeX64_ymm0;}break;
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case RDI_RegCodeX64_ymm1:{result = REGS_RegCodeX64_ymm1;}break;
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case RDI_RegCodeX64_ymm2:{result = REGS_RegCodeX64_ymm2;}break;
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case RDI_RegCodeX64_ymm3:{result = REGS_RegCodeX64_ymm3;}break;
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case RDI_RegCodeX64_ymm4:{result = REGS_RegCodeX64_ymm4;}break;
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case RDI_RegCodeX64_ymm5:{result = REGS_RegCodeX64_ymm5;}break;
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case RDI_RegCodeX64_ymm6:{result = REGS_RegCodeX64_ymm6;}break;
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case RDI_RegCodeX64_ymm7:{result = REGS_RegCodeX64_ymm7;}break;
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case RDI_RegCodeX64_ymm8:{result = REGS_RegCodeX64_ymm8;}break;
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case RDI_RegCodeX64_ymm9:{result = REGS_RegCodeX64_ymm9;}break;
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case RDI_RegCodeX64_ymm10:{result = REGS_RegCodeX64_ymm10;}break;
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case RDI_RegCodeX64_ymm11:{result = REGS_RegCodeX64_ymm11;}break;
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case RDI_RegCodeX64_ymm12:{result = REGS_RegCodeX64_ymm12;}break;
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case RDI_RegCodeX64_ymm13:{result = REGS_RegCodeX64_ymm13;}break;
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case RDI_RegCodeX64_ymm14:{result = REGS_RegCodeX64_ymm14;}break;
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case RDI_RegCodeX64_ymm15:{result = REGS_RegCodeX64_ymm15;}break;
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case RDI_RegCodeX64_zmm0:{result = REGS_RegCodeX64_zmm0;}break;
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case RDI_RegCodeX64_zmm1:{result = REGS_RegCodeX64_zmm1;}break;
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case RDI_RegCodeX64_zmm2:{result = REGS_RegCodeX64_zmm2;}break;
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case RDI_RegCodeX64_zmm3:{result = REGS_RegCodeX64_zmm3;}break;
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case RDI_RegCodeX64_zmm4:{result = REGS_RegCodeX64_zmm4;}break;
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case RDI_RegCodeX64_zmm5:{result = REGS_RegCodeX64_zmm5;}break;
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case RDI_RegCodeX64_zmm6:{result = REGS_RegCodeX64_zmm6;}break;
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case RDI_RegCodeX64_zmm7:{result = REGS_RegCodeX64_zmm7;}break;
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case RDI_RegCodeX64_zmm8:{result = REGS_RegCodeX64_zmm8;}break;
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case RDI_RegCodeX64_zmm9:{result = REGS_RegCodeX64_zmm9;}break;
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case RDI_RegCodeX64_zmm10:{result = REGS_RegCodeX64_zmm10;}break;
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case RDI_RegCodeX64_zmm11:{result = REGS_RegCodeX64_zmm11;}break;
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case RDI_RegCodeX64_zmm12:{result = REGS_RegCodeX64_zmm12;}break;
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case RDI_RegCodeX64_zmm13:{result = REGS_RegCodeX64_zmm13;}break;
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case RDI_RegCodeX64_zmm14:{result = REGS_RegCodeX64_zmm14;}break;
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case RDI_RegCodeX64_zmm15:{result = REGS_RegCodeX64_zmm15;}break;
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case RDI_RegCodeX64_zmm16:{result = REGS_RegCodeX64_zmm16;}break;
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case RDI_RegCodeX64_zmm17:{result = REGS_RegCodeX64_zmm17;}break;
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case RDI_RegCodeX64_zmm18:{result = REGS_RegCodeX64_zmm18;}break;
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case RDI_RegCodeX64_zmm19:{result = REGS_RegCodeX64_zmm19;}break;
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case RDI_RegCodeX64_zmm20:{result = REGS_RegCodeX64_zmm20;}break;
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case RDI_RegCodeX64_zmm21:{result = REGS_RegCodeX64_zmm21;}break;
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case RDI_RegCodeX64_zmm22:{result = REGS_RegCodeX64_zmm22;}break;
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case RDI_RegCodeX64_zmm23:{result = REGS_RegCodeX64_zmm23;}break;
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case RDI_RegCodeX64_zmm24:{result = REGS_RegCodeX64_zmm24;}break;
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case RDI_RegCodeX64_zmm25:{result = REGS_RegCodeX64_zmm25;}break;
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case RDI_RegCodeX64_zmm26:{result = REGS_RegCodeX64_zmm26;}break;
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case RDI_RegCodeX64_zmm27:{result = REGS_RegCodeX64_zmm27;}break;
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case RDI_RegCodeX64_zmm28:{result = REGS_RegCodeX64_zmm28;}break;
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case RDI_RegCodeX64_zmm29:{result = REGS_RegCodeX64_zmm29;}break;
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case RDI_RegCodeX64_zmm30:{result = REGS_RegCodeX64_zmm30;}break;
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case RDI_RegCodeX64_zmm31:{result = REGS_RegCodeX64_zmm31;}break;
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case RDI_RegCodeX64_k0:{result = REGS_RegCodeX64_k0;}break;
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case RDI_RegCodeX64_k1:{result = REGS_RegCodeX64_k1;}break;
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case RDI_RegCodeX64_k2:{result = REGS_RegCodeX64_k2;}break;
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case RDI_RegCodeX64_k3:{result = REGS_RegCodeX64_k3;}break;
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case RDI_RegCodeX64_k4:{result = REGS_RegCodeX64_k4;}break;
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case RDI_RegCodeX64_k5:{result = REGS_RegCodeX64_k5;}break;
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case RDI_RegCodeX64_k6:{result = REGS_RegCodeX64_k6;}break;
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case RDI_RegCodeX64_k7:{result = REGS_RegCodeX64_k7;}break;
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}
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}break;
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case Architecture_x86:
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