mirror of
https://github.com/Ed94/raddebugger.git
synced 2026-08-02 03:58:11 +00:00
avx512 registers & fixes for getting & setting x64 context
This commit is contained in:
Martins Mozeiko
committed by
Ryan Fleury
Ryan Fleury
parent
14759e49e9
commit
ce7c8d5244
+233
-113
@@ -103,7 +103,7 @@ case Architecture_x86:{result = regs_g_alias_code_x86_usage_kind_table;}break;
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return result;
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}
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C_LINKAGE_BEGIN
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REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[77] =
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REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[101] =
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{
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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@@ -182,66 +182,6 @@ REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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};
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REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[80] =
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{
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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@@ -268,7 +208,107 @@ REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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};
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String8 regs_g_reg_code_x64_string_table[77] =
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REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[96] =
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{
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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REGS_UsageKind_Normal,
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};
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String8 regs_g_reg_code_x64_string_table[101] =
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{
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str8_lit_comp(""),
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str8_lit_comp("rax"),
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@@ -331,25 +371,49 @@ str8_lit_comp("ds"),
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str8_lit_comp("es"),
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str8_lit_comp("fs"),
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str8_lit_comp("gs"),
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str8_lit_comp("ymm0"),
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str8_lit_comp("ymm1"),
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str8_lit_comp("ymm2"),
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str8_lit_comp("ymm3"),
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str8_lit_comp("ymm4"),
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str8_lit_comp("ymm5"),
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str8_lit_comp("ymm6"),
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str8_lit_comp("ymm7"),
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str8_lit_comp("ymm8"),
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str8_lit_comp("ymm9"),
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str8_lit_comp("ymm10"),
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str8_lit_comp("ymm11"),
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str8_lit_comp("ymm12"),
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str8_lit_comp("ymm13"),
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str8_lit_comp("ymm14"),
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str8_lit_comp("ymm15"),
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str8_lit_comp("zmm0"),
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str8_lit_comp("zmm1"),
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str8_lit_comp("zmm2"),
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str8_lit_comp("zmm3"),
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str8_lit_comp("zmm4"),
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str8_lit_comp("zmm5"),
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str8_lit_comp("zmm6"),
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str8_lit_comp("zmm7"),
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str8_lit_comp("zmm8"),
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str8_lit_comp("zmm9"),
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str8_lit_comp("zmm10"),
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str8_lit_comp("zmm11"),
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str8_lit_comp("zmm12"),
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str8_lit_comp("zmm13"),
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str8_lit_comp("zmm14"),
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str8_lit_comp("zmm15"),
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str8_lit_comp("zmm16"),
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str8_lit_comp("zmm17"),
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str8_lit_comp("zmm18"),
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str8_lit_comp("zmm19"),
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str8_lit_comp("zmm20"),
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str8_lit_comp("zmm21"),
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str8_lit_comp("zmm22"),
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str8_lit_comp("zmm23"),
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str8_lit_comp("zmm24"),
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str8_lit_comp("zmm25"),
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str8_lit_comp("zmm26"),
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str8_lit_comp("zmm27"),
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str8_lit_comp("zmm28"),
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str8_lit_comp("zmm29"),
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str8_lit_comp("zmm30"),
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str8_lit_comp("zmm31"),
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str8_lit_comp("k0"),
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str8_lit_comp("k1"),
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str8_lit_comp("k2"),
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str8_lit_comp("k3"),
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str8_lit_comp("k4"),
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str8_lit_comp("k5"),
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str8_lit_comp("k6"),
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str8_lit_comp("k7"),
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};
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String8 regs_g_alias_code_x64_string_table[80] =
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String8 regs_g_alias_code_x64_string_table[96] =
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{
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str8_lit_comp(""),
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str8_lit_comp("eax"),
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@@ -423,6 +487,22 @@ str8_lit_comp("xmm12"),
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str8_lit_comp("xmm13"),
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str8_lit_comp("xmm14"),
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str8_lit_comp("xmm15"),
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str8_lit_comp("ymm0"),
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str8_lit_comp("ymm1"),
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str8_lit_comp("ymm2"),
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str8_lit_comp("ymm3"),
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str8_lit_comp("ymm4"),
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str8_lit_comp("ymm5"),
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str8_lit_comp("ymm6"),
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str8_lit_comp("ymm7"),
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str8_lit_comp("ymm8"),
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str8_lit_comp("ymm9"),
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str8_lit_comp("ymm10"),
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str8_lit_comp("ymm11"),
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str8_lit_comp("ymm12"),
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str8_lit_comp("ymm13"),
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str8_lit_comp("ymm14"),
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str8_lit_comp("ymm15"),
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str8_lit_comp("mm0"),
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str8_lit_comp("mm1"),
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str8_lit_comp("mm2"),
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@@ -433,7 +513,7 @@ str8_lit_comp("mm6"),
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str8_lit_comp("mm7"),
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};
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REGS_Rng regs_g_reg_code_x64_rng_table[77] =
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REGS_Rng regs_g_reg_code_x64_rng_table[101] =
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{
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{0},
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{(U16)OffsetOf(REGS_RegBlockX64, rax), 8},
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@@ -496,25 +576,49 @@ REGS_Rng regs_g_reg_code_x64_rng_table[77] =
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{(U16)OffsetOf(REGS_RegBlockX64, es), 2},
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{(U16)OffsetOf(REGS_RegBlockX64, fs), 2},
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{(U16)OffsetOf(REGS_RegBlockX64, gs), 2},
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{(U16)OffsetOf(REGS_RegBlockX64, ymm0), 32},
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{(U16)OffsetOf(REGS_RegBlockX64, ymm1), 32},
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{(U16)OffsetOf(REGS_RegBlockX64, ymm2), 32},
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{(U16)OffsetOf(REGS_RegBlockX64, ymm3), 32},
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{(U16)OffsetOf(REGS_RegBlockX64, ymm4), 32},
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{(U16)OffsetOf(REGS_RegBlockX64, ymm5), 32},
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{(U16)OffsetOf(REGS_RegBlockX64, ymm6), 32},
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{(U16)OffsetOf(REGS_RegBlockX64, ymm7), 32},
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{(U16)OffsetOf(REGS_RegBlockX64, ymm8), 32},
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{(U16)OffsetOf(REGS_RegBlockX64, ymm9), 32},
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{(U16)OffsetOf(REGS_RegBlockX64, ymm10), 32},
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{(U16)OffsetOf(REGS_RegBlockX64, ymm11), 32},
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{(U16)OffsetOf(REGS_RegBlockX64, ymm12), 32},
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{(U16)OffsetOf(REGS_RegBlockX64, ymm13), 32},
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{(U16)OffsetOf(REGS_RegBlockX64, ymm14), 32},
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{(U16)OffsetOf(REGS_RegBlockX64, ymm15), 32},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm0), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm1), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm2), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm3), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm4), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm5), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm6), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm7), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm8), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm9), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm10), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm11), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm12), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm13), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm14), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm15), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm16), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm17), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm18), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm19), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm20), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm21), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm22), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm23), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm24), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm25), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm26), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm27), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm28), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm29), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm30), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, zmm31), 64},
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{(U16)OffsetOf(REGS_RegBlockX64, k0), 8},
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{(U16)OffsetOf(REGS_RegBlockX64, k1), 8},
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{(U16)OffsetOf(REGS_RegBlockX64, k2), 8},
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{(U16)OffsetOf(REGS_RegBlockX64, k3), 8},
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{(U16)OffsetOf(REGS_RegBlockX64, k4), 8},
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{(U16)OffsetOf(REGS_RegBlockX64, k5), 8},
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{(U16)OffsetOf(REGS_RegBlockX64, k6), 8},
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{(U16)OffsetOf(REGS_RegBlockX64, k7), 8},
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};
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REGS_Slice regs_g_alias_code_x64_slice_table[80] =
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REGS_Slice regs_g_alias_code_x64_slice_table[96] =
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{
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{0},
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{REGS_RegCodeX64_rax, 0, 4},
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@@ -572,22 +676,38 @@ REGS_Slice regs_g_alias_code_x64_slice_table[80] =
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{REGS_RegCodeX64_rcx, 1, 1},
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{REGS_RegCodeX64_rdx, 1, 1},
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{REGS_RegCodeX64_rbx, 1, 1},
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{REGS_RegCodeX64_ymm0, 0, 16},
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{REGS_RegCodeX64_ymm1, 0, 16},
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{REGS_RegCodeX64_ymm2, 0, 16},
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{REGS_RegCodeX64_ymm3, 0, 16},
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{REGS_RegCodeX64_ymm4, 0, 16},
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{REGS_RegCodeX64_ymm5, 0, 16},
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{REGS_RegCodeX64_ymm6, 0, 16},
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{REGS_RegCodeX64_ymm7, 0, 16},
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{REGS_RegCodeX64_ymm8, 0, 16},
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{REGS_RegCodeX64_ymm9, 0, 16},
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{REGS_RegCodeX64_ymm10, 0, 16},
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{REGS_RegCodeX64_ymm11, 0, 16},
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{REGS_RegCodeX64_ymm12, 0, 16},
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{REGS_RegCodeX64_ymm13, 0, 16},
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{REGS_RegCodeX64_ymm14, 0, 16},
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{REGS_RegCodeX64_ymm15, 0, 16},
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{REGS_RegCodeX64_zmm0, 0, 16},
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{REGS_RegCodeX64_zmm1, 0, 16},
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{REGS_RegCodeX64_zmm2, 0, 16},
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{REGS_RegCodeX64_zmm3, 0, 16},
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{REGS_RegCodeX64_zmm4, 0, 16},
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{REGS_RegCodeX64_zmm5, 0, 16},
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{REGS_RegCodeX64_zmm6, 0, 16},
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{REGS_RegCodeX64_zmm7, 0, 16},
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{REGS_RegCodeX64_zmm8, 0, 16},
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{REGS_RegCodeX64_zmm9, 0, 16},
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{REGS_RegCodeX64_zmm10, 0, 16},
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{REGS_RegCodeX64_zmm11, 0, 16},
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{REGS_RegCodeX64_zmm12, 0, 16},
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{REGS_RegCodeX64_zmm13, 0, 16},
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{REGS_RegCodeX64_zmm14, 0, 16},
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{REGS_RegCodeX64_zmm15, 0, 16},
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{REGS_RegCodeX64_zmm0, 0, 32},
|
||||
{REGS_RegCodeX64_zmm1, 0, 32},
|
||||
{REGS_RegCodeX64_zmm2, 0, 32},
|
||||
{REGS_RegCodeX64_zmm3, 0, 32},
|
||||
{REGS_RegCodeX64_zmm4, 0, 32},
|
||||
{REGS_RegCodeX64_zmm5, 0, 32},
|
||||
{REGS_RegCodeX64_zmm6, 0, 32},
|
||||
{REGS_RegCodeX64_zmm7, 0, 32},
|
||||
{REGS_RegCodeX64_zmm8, 0, 32},
|
||||
{REGS_RegCodeX64_zmm9, 0, 32},
|
||||
{REGS_RegCodeX64_zmm10, 0, 32},
|
||||
{REGS_RegCodeX64_zmm11, 0, 32},
|
||||
{REGS_RegCodeX64_zmm12, 0, 32},
|
||||
{REGS_RegCodeX64_zmm13, 0, 32},
|
||||
{REGS_RegCodeX64_zmm14, 0, 32},
|
||||
{REGS_RegCodeX64_zmm15, 0, 32},
|
||||
{REGS_RegCodeX64_fpr0, 0, 8},
|
||||
{REGS_RegCodeX64_fpr1, 0, 8},
|
||||
{REGS_RegCodeX64_fpr2, 0, 8},
|
||||
|
||||
+102
-38
@@ -69,22 +69,46 @@ REGS_RegCodeX64_ds,
|
||||
REGS_RegCodeX64_es,
|
||||
REGS_RegCodeX64_fs,
|
||||
REGS_RegCodeX64_gs,
|
||||
REGS_RegCodeX64_ymm0,
|
||||
REGS_RegCodeX64_ymm1,
|
||||
REGS_RegCodeX64_ymm2,
|
||||
REGS_RegCodeX64_ymm3,
|
||||
REGS_RegCodeX64_ymm4,
|
||||
REGS_RegCodeX64_ymm5,
|
||||
REGS_RegCodeX64_ymm6,
|
||||
REGS_RegCodeX64_ymm7,
|
||||
REGS_RegCodeX64_ymm8,
|
||||
REGS_RegCodeX64_ymm9,
|
||||
REGS_RegCodeX64_ymm10,
|
||||
REGS_RegCodeX64_ymm11,
|
||||
REGS_RegCodeX64_ymm12,
|
||||
REGS_RegCodeX64_ymm13,
|
||||
REGS_RegCodeX64_ymm14,
|
||||
REGS_RegCodeX64_ymm15,
|
||||
REGS_RegCodeX64_zmm0,
|
||||
REGS_RegCodeX64_zmm1,
|
||||
REGS_RegCodeX64_zmm2,
|
||||
REGS_RegCodeX64_zmm3,
|
||||
REGS_RegCodeX64_zmm4,
|
||||
REGS_RegCodeX64_zmm5,
|
||||
REGS_RegCodeX64_zmm6,
|
||||
REGS_RegCodeX64_zmm7,
|
||||
REGS_RegCodeX64_zmm8,
|
||||
REGS_RegCodeX64_zmm9,
|
||||
REGS_RegCodeX64_zmm10,
|
||||
REGS_RegCodeX64_zmm11,
|
||||
REGS_RegCodeX64_zmm12,
|
||||
REGS_RegCodeX64_zmm13,
|
||||
REGS_RegCodeX64_zmm14,
|
||||
REGS_RegCodeX64_zmm15,
|
||||
REGS_RegCodeX64_zmm16,
|
||||
REGS_RegCodeX64_zmm17,
|
||||
REGS_RegCodeX64_zmm18,
|
||||
REGS_RegCodeX64_zmm19,
|
||||
REGS_RegCodeX64_zmm20,
|
||||
REGS_RegCodeX64_zmm21,
|
||||
REGS_RegCodeX64_zmm22,
|
||||
REGS_RegCodeX64_zmm23,
|
||||
REGS_RegCodeX64_zmm24,
|
||||
REGS_RegCodeX64_zmm25,
|
||||
REGS_RegCodeX64_zmm26,
|
||||
REGS_RegCodeX64_zmm27,
|
||||
REGS_RegCodeX64_zmm28,
|
||||
REGS_RegCodeX64_zmm29,
|
||||
REGS_RegCodeX64_zmm30,
|
||||
REGS_RegCodeX64_zmm31,
|
||||
REGS_RegCodeX64_k0,
|
||||
REGS_RegCodeX64_k1,
|
||||
REGS_RegCodeX64_k2,
|
||||
REGS_RegCodeX64_k3,
|
||||
REGS_RegCodeX64_k4,
|
||||
REGS_RegCodeX64_k5,
|
||||
REGS_RegCodeX64_k6,
|
||||
REGS_RegCodeX64_k7,
|
||||
REGS_RegCodeX64_COUNT,
|
||||
} REGS_RegCodeX64;
|
||||
|
||||
@@ -162,6 +186,22 @@ REGS_AliasCodeX64_xmm12,
|
||||
REGS_AliasCodeX64_xmm13,
|
||||
REGS_AliasCodeX64_xmm14,
|
||||
REGS_AliasCodeX64_xmm15,
|
||||
REGS_AliasCodeX64_ymm0,
|
||||
REGS_AliasCodeX64_ymm1,
|
||||
REGS_AliasCodeX64_ymm2,
|
||||
REGS_AliasCodeX64_ymm3,
|
||||
REGS_AliasCodeX64_ymm4,
|
||||
REGS_AliasCodeX64_ymm5,
|
||||
REGS_AliasCodeX64_ymm6,
|
||||
REGS_AliasCodeX64_ymm7,
|
||||
REGS_AliasCodeX64_ymm8,
|
||||
REGS_AliasCodeX64_ymm9,
|
||||
REGS_AliasCodeX64_ymm10,
|
||||
REGS_AliasCodeX64_ymm11,
|
||||
REGS_AliasCodeX64_ymm12,
|
||||
REGS_AliasCodeX64_ymm13,
|
||||
REGS_AliasCodeX64_ymm14,
|
||||
REGS_AliasCodeX64_ymm15,
|
||||
REGS_AliasCodeX64_mm0,
|
||||
REGS_AliasCodeX64_mm1,
|
||||
REGS_AliasCodeX64_mm2,
|
||||
@@ -343,22 +383,46 @@ REGS_Reg16 ds;
|
||||
REGS_Reg16 es;
|
||||
REGS_Reg16 fs;
|
||||
REGS_Reg16 gs;
|
||||
REGS_Reg256 ymm0;
|
||||
REGS_Reg256 ymm1;
|
||||
REGS_Reg256 ymm2;
|
||||
REGS_Reg256 ymm3;
|
||||
REGS_Reg256 ymm4;
|
||||
REGS_Reg256 ymm5;
|
||||
REGS_Reg256 ymm6;
|
||||
REGS_Reg256 ymm7;
|
||||
REGS_Reg256 ymm8;
|
||||
REGS_Reg256 ymm9;
|
||||
REGS_Reg256 ymm10;
|
||||
REGS_Reg256 ymm11;
|
||||
REGS_Reg256 ymm12;
|
||||
REGS_Reg256 ymm13;
|
||||
REGS_Reg256 ymm14;
|
||||
REGS_Reg256 ymm15;
|
||||
REGS_Reg512 zmm0;
|
||||
REGS_Reg512 zmm1;
|
||||
REGS_Reg512 zmm2;
|
||||
REGS_Reg512 zmm3;
|
||||
REGS_Reg512 zmm4;
|
||||
REGS_Reg512 zmm5;
|
||||
REGS_Reg512 zmm6;
|
||||
REGS_Reg512 zmm7;
|
||||
REGS_Reg512 zmm8;
|
||||
REGS_Reg512 zmm9;
|
||||
REGS_Reg512 zmm10;
|
||||
REGS_Reg512 zmm11;
|
||||
REGS_Reg512 zmm12;
|
||||
REGS_Reg512 zmm13;
|
||||
REGS_Reg512 zmm14;
|
||||
REGS_Reg512 zmm15;
|
||||
REGS_Reg512 zmm16;
|
||||
REGS_Reg512 zmm17;
|
||||
REGS_Reg512 zmm18;
|
||||
REGS_Reg512 zmm19;
|
||||
REGS_Reg512 zmm20;
|
||||
REGS_Reg512 zmm21;
|
||||
REGS_Reg512 zmm22;
|
||||
REGS_Reg512 zmm23;
|
||||
REGS_Reg512 zmm24;
|
||||
REGS_Reg512 zmm25;
|
||||
REGS_Reg512 zmm26;
|
||||
REGS_Reg512 zmm27;
|
||||
REGS_Reg512 zmm28;
|
||||
REGS_Reg512 zmm29;
|
||||
REGS_Reg512 zmm30;
|
||||
REGS_Reg512 zmm31;
|
||||
REGS_Reg64 k0;
|
||||
REGS_Reg64 k1;
|
||||
REGS_Reg64 k2;
|
||||
REGS_Reg64 k3;
|
||||
REGS_Reg64 k4;
|
||||
REGS_Reg64 k5;
|
||||
REGS_Reg64 k6;
|
||||
REGS_Reg64 k7;
|
||||
};
|
||||
|
||||
typedef struct REGS_RegBlockX86 REGS_RegBlockX86;
|
||||
@@ -427,12 +491,12 @@ REGS_Reg256 ymm7;
|
||||
};
|
||||
|
||||
C_LINKAGE_BEGIN
|
||||
extern REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[77];
|
||||
extern REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[80];
|
||||
extern String8 regs_g_reg_code_x64_string_table[77];
|
||||
extern String8 regs_g_alias_code_x64_string_table[80];
|
||||
extern REGS_Rng regs_g_reg_code_x64_rng_table[77];
|
||||
extern REGS_Slice regs_g_alias_code_x64_slice_table[80];
|
||||
extern REGS_UsageKind regs_g_reg_code_x64_usage_kind_table[101];
|
||||
extern REGS_UsageKind regs_g_alias_code_x64_usage_kind_table[96];
|
||||
extern String8 regs_g_reg_code_x64_string_table[101];
|
||||
extern String8 regs_g_alias_code_x64_string_table[96];
|
||||
extern REGS_Rng regs_g_reg_code_x64_rng_table[101];
|
||||
extern REGS_Slice regs_g_alias_code_x64_slice_table[96];
|
||||
extern REGS_UsageKind regs_g_reg_code_x86_usage_kind_table[61];
|
||||
extern REGS_UsageKind regs_g_alias_code_x86_usage_kind_table[36];
|
||||
extern String8 regs_g_reg_code_x86_string_table[61];
|
||||
|
||||
@@ -74,22 +74,46 @@ case REGS_RegCodeX64_ds:{result = RDI_RegCodeX64_ds;}break;
|
||||
case REGS_RegCodeX64_es:{result = RDI_RegCodeX64_es;}break;
|
||||
case REGS_RegCodeX64_fs:{result = RDI_RegCodeX64_fs;}break;
|
||||
case REGS_RegCodeX64_gs:{result = RDI_RegCodeX64_gs;}break;
|
||||
case REGS_RegCodeX64_ymm0:{result = RDI_RegCodeX64_ymm0;}break;
|
||||
case REGS_RegCodeX64_ymm1:{result = RDI_RegCodeX64_ymm1;}break;
|
||||
case REGS_RegCodeX64_ymm2:{result = RDI_RegCodeX64_ymm2;}break;
|
||||
case REGS_RegCodeX64_ymm3:{result = RDI_RegCodeX64_ymm3;}break;
|
||||
case REGS_RegCodeX64_ymm4:{result = RDI_RegCodeX64_ymm4;}break;
|
||||
case REGS_RegCodeX64_ymm5:{result = RDI_RegCodeX64_ymm5;}break;
|
||||
case REGS_RegCodeX64_ymm6:{result = RDI_RegCodeX64_ymm6;}break;
|
||||
case REGS_RegCodeX64_ymm7:{result = RDI_RegCodeX64_ymm7;}break;
|
||||
case REGS_RegCodeX64_ymm8:{result = RDI_RegCodeX64_ymm8;}break;
|
||||
case REGS_RegCodeX64_ymm9:{result = RDI_RegCodeX64_ymm9;}break;
|
||||
case REGS_RegCodeX64_ymm10:{result = RDI_RegCodeX64_ymm10;}break;
|
||||
case REGS_RegCodeX64_ymm11:{result = RDI_RegCodeX64_ymm11;}break;
|
||||
case REGS_RegCodeX64_ymm12:{result = RDI_RegCodeX64_ymm12;}break;
|
||||
case REGS_RegCodeX64_ymm13:{result = RDI_RegCodeX64_ymm13;}break;
|
||||
case REGS_RegCodeX64_ymm14:{result = RDI_RegCodeX64_ymm14;}break;
|
||||
case REGS_RegCodeX64_ymm15:{result = RDI_RegCodeX64_ymm15;}break;
|
||||
case REGS_RegCodeX64_zmm0:{result = RDI_RegCodeX64_zmm0;}break;
|
||||
case REGS_RegCodeX64_zmm1:{result = RDI_RegCodeX64_zmm1;}break;
|
||||
case REGS_RegCodeX64_zmm2:{result = RDI_RegCodeX64_zmm2;}break;
|
||||
case REGS_RegCodeX64_zmm3:{result = RDI_RegCodeX64_zmm3;}break;
|
||||
case REGS_RegCodeX64_zmm4:{result = RDI_RegCodeX64_zmm4;}break;
|
||||
case REGS_RegCodeX64_zmm5:{result = RDI_RegCodeX64_zmm5;}break;
|
||||
case REGS_RegCodeX64_zmm6:{result = RDI_RegCodeX64_zmm6;}break;
|
||||
case REGS_RegCodeX64_zmm7:{result = RDI_RegCodeX64_zmm7;}break;
|
||||
case REGS_RegCodeX64_zmm8:{result = RDI_RegCodeX64_zmm8;}break;
|
||||
case REGS_RegCodeX64_zmm9:{result = RDI_RegCodeX64_zmm9;}break;
|
||||
case REGS_RegCodeX64_zmm10:{result = RDI_RegCodeX64_zmm10;}break;
|
||||
case REGS_RegCodeX64_zmm11:{result = RDI_RegCodeX64_zmm11;}break;
|
||||
case REGS_RegCodeX64_zmm12:{result = RDI_RegCodeX64_zmm12;}break;
|
||||
case REGS_RegCodeX64_zmm13:{result = RDI_RegCodeX64_zmm13;}break;
|
||||
case REGS_RegCodeX64_zmm14:{result = RDI_RegCodeX64_zmm14;}break;
|
||||
case REGS_RegCodeX64_zmm15:{result = RDI_RegCodeX64_zmm15;}break;
|
||||
case REGS_RegCodeX64_zmm16:{result = RDI_RegCodeX64_zmm16;}break;
|
||||
case REGS_RegCodeX64_zmm17:{result = RDI_RegCodeX64_zmm17;}break;
|
||||
case REGS_RegCodeX64_zmm18:{result = RDI_RegCodeX64_zmm18;}break;
|
||||
case REGS_RegCodeX64_zmm19:{result = RDI_RegCodeX64_zmm19;}break;
|
||||
case REGS_RegCodeX64_zmm20:{result = RDI_RegCodeX64_zmm20;}break;
|
||||
case REGS_RegCodeX64_zmm21:{result = RDI_RegCodeX64_zmm21;}break;
|
||||
case REGS_RegCodeX64_zmm22:{result = RDI_RegCodeX64_zmm22;}break;
|
||||
case REGS_RegCodeX64_zmm23:{result = RDI_RegCodeX64_zmm23;}break;
|
||||
case REGS_RegCodeX64_zmm24:{result = RDI_RegCodeX64_zmm24;}break;
|
||||
case REGS_RegCodeX64_zmm25:{result = RDI_RegCodeX64_zmm25;}break;
|
||||
case REGS_RegCodeX64_zmm26:{result = RDI_RegCodeX64_zmm26;}break;
|
||||
case REGS_RegCodeX64_zmm27:{result = RDI_RegCodeX64_zmm27;}break;
|
||||
case REGS_RegCodeX64_zmm28:{result = RDI_RegCodeX64_zmm28;}break;
|
||||
case REGS_RegCodeX64_zmm29:{result = RDI_RegCodeX64_zmm29;}break;
|
||||
case REGS_RegCodeX64_zmm30:{result = RDI_RegCodeX64_zmm30;}break;
|
||||
case REGS_RegCodeX64_zmm31:{result = RDI_RegCodeX64_zmm31;}break;
|
||||
case REGS_RegCodeX64_k0:{result = RDI_RegCodeX64_k0;}break;
|
||||
case REGS_RegCodeX64_k1:{result = RDI_RegCodeX64_k1;}break;
|
||||
case REGS_RegCodeX64_k2:{result = RDI_RegCodeX64_k2;}break;
|
||||
case REGS_RegCodeX64_k3:{result = RDI_RegCodeX64_k3;}break;
|
||||
case REGS_RegCodeX64_k4:{result = RDI_RegCodeX64_k4;}break;
|
||||
case REGS_RegCodeX64_k5:{result = RDI_RegCodeX64_k5;}break;
|
||||
case REGS_RegCodeX64_k6:{result = RDI_RegCodeX64_k6;}break;
|
||||
case REGS_RegCodeX64_k7:{result = RDI_RegCodeX64_k7;}break;
|
||||
}
|
||||
}break;
|
||||
case Architecture_x86:
|
||||
@@ -233,22 +257,46 @@ case RDI_RegCodeX64_ds:{result = REGS_RegCodeX64_ds;}break;
|
||||
case RDI_RegCodeX64_es:{result = REGS_RegCodeX64_es;}break;
|
||||
case RDI_RegCodeX64_fs:{result = REGS_RegCodeX64_fs;}break;
|
||||
case RDI_RegCodeX64_gs:{result = REGS_RegCodeX64_gs;}break;
|
||||
case RDI_RegCodeX64_ymm0:{result = REGS_RegCodeX64_ymm0;}break;
|
||||
case RDI_RegCodeX64_ymm1:{result = REGS_RegCodeX64_ymm1;}break;
|
||||
case RDI_RegCodeX64_ymm2:{result = REGS_RegCodeX64_ymm2;}break;
|
||||
case RDI_RegCodeX64_ymm3:{result = REGS_RegCodeX64_ymm3;}break;
|
||||
case RDI_RegCodeX64_ymm4:{result = REGS_RegCodeX64_ymm4;}break;
|
||||
case RDI_RegCodeX64_ymm5:{result = REGS_RegCodeX64_ymm5;}break;
|
||||
case RDI_RegCodeX64_ymm6:{result = REGS_RegCodeX64_ymm6;}break;
|
||||
case RDI_RegCodeX64_ymm7:{result = REGS_RegCodeX64_ymm7;}break;
|
||||
case RDI_RegCodeX64_ymm8:{result = REGS_RegCodeX64_ymm8;}break;
|
||||
case RDI_RegCodeX64_ymm9:{result = REGS_RegCodeX64_ymm9;}break;
|
||||
case RDI_RegCodeX64_ymm10:{result = REGS_RegCodeX64_ymm10;}break;
|
||||
case RDI_RegCodeX64_ymm11:{result = REGS_RegCodeX64_ymm11;}break;
|
||||
case RDI_RegCodeX64_ymm12:{result = REGS_RegCodeX64_ymm12;}break;
|
||||
case RDI_RegCodeX64_ymm13:{result = REGS_RegCodeX64_ymm13;}break;
|
||||
case RDI_RegCodeX64_ymm14:{result = REGS_RegCodeX64_ymm14;}break;
|
||||
case RDI_RegCodeX64_ymm15:{result = REGS_RegCodeX64_ymm15;}break;
|
||||
case RDI_RegCodeX64_zmm0:{result = REGS_RegCodeX64_zmm0;}break;
|
||||
case RDI_RegCodeX64_zmm1:{result = REGS_RegCodeX64_zmm1;}break;
|
||||
case RDI_RegCodeX64_zmm2:{result = REGS_RegCodeX64_zmm2;}break;
|
||||
case RDI_RegCodeX64_zmm3:{result = REGS_RegCodeX64_zmm3;}break;
|
||||
case RDI_RegCodeX64_zmm4:{result = REGS_RegCodeX64_zmm4;}break;
|
||||
case RDI_RegCodeX64_zmm5:{result = REGS_RegCodeX64_zmm5;}break;
|
||||
case RDI_RegCodeX64_zmm6:{result = REGS_RegCodeX64_zmm6;}break;
|
||||
case RDI_RegCodeX64_zmm7:{result = REGS_RegCodeX64_zmm7;}break;
|
||||
case RDI_RegCodeX64_zmm8:{result = REGS_RegCodeX64_zmm8;}break;
|
||||
case RDI_RegCodeX64_zmm9:{result = REGS_RegCodeX64_zmm9;}break;
|
||||
case RDI_RegCodeX64_zmm10:{result = REGS_RegCodeX64_zmm10;}break;
|
||||
case RDI_RegCodeX64_zmm11:{result = REGS_RegCodeX64_zmm11;}break;
|
||||
case RDI_RegCodeX64_zmm12:{result = REGS_RegCodeX64_zmm12;}break;
|
||||
case RDI_RegCodeX64_zmm13:{result = REGS_RegCodeX64_zmm13;}break;
|
||||
case RDI_RegCodeX64_zmm14:{result = REGS_RegCodeX64_zmm14;}break;
|
||||
case RDI_RegCodeX64_zmm15:{result = REGS_RegCodeX64_zmm15;}break;
|
||||
case RDI_RegCodeX64_zmm16:{result = REGS_RegCodeX64_zmm16;}break;
|
||||
case RDI_RegCodeX64_zmm17:{result = REGS_RegCodeX64_zmm17;}break;
|
||||
case RDI_RegCodeX64_zmm18:{result = REGS_RegCodeX64_zmm18;}break;
|
||||
case RDI_RegCodeX64_zmm19:{result = REGS_RegCodeX64_zmm19;}break;
|
||||
case RDI_RegCodeX64_zmm20:{result = REGS_RegCodeX64_zmm20;}break;
|
||||
case RDI_RegCodeX64_zmm21:{result = REGS_RegCodeX64_zmm21;}break;
|
||||
case RDI_RegCodeX64_zmm22:{result = REGS_RegCodeX64_zmm22;}break;
|
||||
case RDI_RegCodeX64_zmm23:{result = REGS_RegCodeX64_zmm23;}break;
|
||||
case RDI_RegCodeX64_zmm24:{result = REGS_RegCodeX64_zmm24;}break;
|
||||
case RDI_RegCodeX64_zmm25:{result = REGS_RegCodeX64_zmm25;}break;
|
||||
case RDI_RegCodeX64_zmm26:{result = REGS_RegCodeX64_zmm26;}break;
|
||||
case RDI_RegCodeX64_zmm27:{result = REGS_RegCodeX64_zmm27;}break;
|
||||
case RDI_RegCodeX64_zmm28:{result = REGS_RegCodeX64_zmm28;}break;
|
||||
case RDI_RegCodeX64_zmm29:{result = REGS_RegCodeX64_zmm29;}break;
|
||||
case RDI_RegCodeX64_zmm30:{result = REGS_RegCodeX64_zmm30;}break;
|
||||
case RDI_RegCodeX64_zmm31:{result = REGS_RegCodeX64_zmm31;}break;
|
||||
case RDI_RegCodeX64_k0:{result = REGS_RegCodeX64_k0;}break;
|
||||
case RDI_RegCodeX64_k1:{result = REGS_RegCodeX64_k1;}break;
|
||||
case RDI_RegCodeX64_k2:{result = REGS_RegCodeX64_k2;}break;
|
||||
case RDI_RegCodeX64_k3:{result = REGS_RegCodeX64_k3;}break;
|
||||
case RDI_RegCodeX64_k4:{result = REGS_RegCodeX64_k4;}break;
|
||||
case RDI_RegCodeX64_k5:{result = REGS_RegCodeX64_k5;}break;
|
||||
case RDI_RegCodeX64_k6:{result = REGS_RegCodeX64_k6;}break;
|
||||
case RDI_RegCodeX64_k7:{result = REGS_RegCodeX64_k7;}break;
|
||||
}
|
||||
}break;
|
||||
case Architecture_x86:
|
||||
|
||||
@@ -72,6 +72,16 @@ union REGS_Reg256
|
||||
F64 f64[4];
|
||||
};
|
||||
|
||||
typedef union REGS_Reg512 REGS_Reg512;
|
||||
union REGS_Reg512
|
||||
{
|
||||
U8 v[64];
|
||||
U32 u32[16];
|
||||
F32 f32[16];
|
||||
U64 u64[8];
|
||||
F64 f64[8];
|
||||
};
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: Register Slicing Types
|
||||
|
||||
|
||||
+72
-32
@@ -67,22 +67,46 @@ REGS_RegTableX64:
|
||||
{es 16 Normal}
|
||||
{fs 16 Normal}
|
||||
{gs 16 Normal}
|
||||
{ymm0 256 Normal}
|
||||
{ymm1 256 Normal}
|
||||
{ymm2 256 Normal}
|
||||
{ymm3 256 Normal}
|
||||
{ymm4 256 Normal}
|
||||
{ymm5 256 Normal}
|
||||
{ymm6 256 Normal}
|
||||
{ymm7 256 Normal}
|
||||
{ymm8 256 Normal}
|
||||
{ymm9 256 Normal}
|
||||
{ymm10 256 Normal}
|
||||
{ymm11 256 Normal}
|
||||
{ymm12 256 Normal}
|
||||
{ymm13 256 Normal}
|
||||
{ymm14 256 Normal}
|
||||
{ymm15 256 Normal}
|
||||
{zmm0 512 Normal}
|
||||
{zmm1 512 Normal}
|
||||
{zmm2 512 Normal}
|
||||
{zmm3 512 Normal}
|
||||
{zmm4 512 Normal}
|
||||
{zmm5 512 Normal}
|
||||
{zmm6 512 Normal}
|
||||
{zmm7 512 Normal}
|
||||
{zmm8 512 Normal}
|
||||
{zmm9 512 Normal}
|
||||
{zmm10 512 Normal}
|
||||
{zmm11 512 Normal}
|
||||
{zmm12 512 Normal}
|
||||
{zmm13 512 Normal}
|
||||
{zmm14 512 Normal}
|
||||
{zmm15 512 Normal}
|
||||
{zmm16 512 Normal}
|
||||
{zmm17 512 Normal}
|
||||
{zmm18 512 Normal}
|
||||
{zmm19 512 Normal}
|
||||
{zmm20 512 Normal}
|
||||
{zmm21 512 Normal}
|
||||
{zmm22 512 Normal}
|
||||
{zmm23 512 Normal}
|
||||
{zmm24 512 Normal}
|
||||
{zmm25 512 Normal}
|
||||
{zmm26 512 Normal}
|
||||
{zmm27 512 Normal}
|
||||
{zmm28 512 Normal}
|
||||
{zmm29 512 Normal}
|
||||
{zmm30 512 Normal}
|
||||
{zmm31 512 Normal}
|
||||
{k0 64 Normal}
|
||||
{k1 64 Normal}
|
||||
{k2 64 Normal}
|
||||
{k3 64 Normal}
|
||||
{k4 64 Normal}
|
||||
{k5 64 Normal}
|
||||
{k6 64 Normal}
|
||||
{k7 64 Normal}
|
||||
}
|
||||
|
||||
@table(name base off size usage)
|
||||
@@ -146,22 +170,38 @@ REGS_AliasTableX64:
|
||||
{ch rcx 8 8 Normal}
|
||||
{dh rdx 8 8 Normal}
|
||||
{bh rbx 8 8 Normal}
|
||||
{xmm0 ymm0 0 128 Normal}
|
||||
{xmm1 ymm1 0 128 Normal}
|
||||
{xmm2 ymm2 0 128 Normal}
|
||||
{xmm3 ymm3 0 128 Normal}
|
||||
{xmm4 ymm4 0 128 Normal}
|
||||
{xmm5 ymm5 0 128 Normal}
|
||||
{xmm6 ymm6 0 128 Normal}
|
||||
{xmm7 ymm7 0 128 Normal}
|
||||
{xmm8 ymm8 0 128 Normal}
|
||||
{xmm9 ymm9 0 128 Normal}
|
||||
{xmm10 ymm10 0 128 Normal}
|
||||
{xmm11 ymm11 0 128 Normal}
|
||||
{xmm12 ymm12 0 128 Normal}
|
||||
{xmm13 ymm13 0 128 Normal}
|
||||
{xmm14 ymm14 0 128 Normal}
|
||||
{xmm15 ymm15 0 128 Normal}
|
||||
{xmm0 zmm0 0 128 Normal}
|
||||
{xmm1 zmm1 0 128 Normal}
|
||||
{xmm2 zmm2 0 128 Normal}
|
||||
{xmm3 zmm3 0 128 Normal}
|
||||
{xmm4 zmm4 0 128 Normal}
|
||||
{xmm5 zmm5 0 128 Normal}
|
||||
{xmm6 zmm6 0 128 Normal}
|
||||
{xmm7 zmm7 0 128 Normal}
|
||||
{xmm8 zmm8 0 128 Normal}
|
||||
{xmm9 zmm9 0 128 Normal}
|
||||
{xmm10 zmm10 0 128 Normal}
|
||||
{xmm11 zmm11 0 128 Normal}
|
||||
{xmm12 zmm12 0 128 Normal}
|
||||
{xmm13 zmm13 0 128 Normal}
|
||||
{xmm14 zmm14 0 128 Normal}
|
||||
{xmm15 zmm15 0 128 Normal}
|
||||
{ymm0 zmm0 0 256 Normal}
|
||||
{ymm1 zmm1 0 256 Normal}
|
||||
{ymm2 zmm2 0 256 Normal}
|
||||
{ymm3 zmm3 0 256 Normal}
|
||||
{ymm4 zmm4 0 256 Normal}
|
||||
{ymm5 zmm5 0 256 Normal}
|
||||
{ymm6 zmm6 0 256 Normal}
|
||||
{ymm7 zmm7 0 256 Normal}
|
||||
{ymm8 zmm8 0 256 Normal}
|
||||
{ymm9 zmm9 0 256 Normal}
|
||||
{ymm10 zmm10 0 256 Normal}
|
||||
{ymm11 zmm11 0 256 Normal}
|
||||
{ymm12 zmm12 0 256 Normal}
|
||||
{ymm13 zmm13 0 256 Normal}
|
||||
{ymm14 zmm14 0 256 Normal}
|
||||
{ymm15 zmm15 0 256 Normal}
|
||||
{mm0 fpr0 0 64 Normal}
|
||||
{mm1 fpr1 0 64 Normal}
|
||||
{mm2 fpr2 0 64 Normal}
|
||||
|
||||
Reference in New Issue
Block a user