mirror of
https://github.com/Ed94/raddebugger.git
synced 2026-07-30 19:10:01 +00:00
avx512 registers & fixes for getting & setting x64 context
This commit is contained in:
Martins Mozeiko
committed by
Ryan Fleury
Ryan Fleury
parent
14759e49e9
commit
ce7c8d5244
@@ -686,15 +686,11 @@ dmn_w32_thread_read_reg_block(Architecture arch, HANDLE thread, void *reg_block)
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//- rjf: unpack info about available features
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U32 feature_mask = GetEnabledXStateFeatures();
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B32 avx_enabled = !!(feature_mask & XSTATE_MASK_AVX);
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B32 xstate_enabled = (feature_mask & (XSTATE_MASK_AVX | XSTATE_MASK_AVX512)) != 0;
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//- rjf: set up context
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CONTEXT *ctx = 0;
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U32 ctx_flags = DMN_W32_CTX_X64_ALL;
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if(avx_enabled)
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{
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ctx_flags |= DMN_W32_CTX_INTEL_XSTATE;
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}
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U32 ctx_flags = DMN_W32_CTX_X64_ALL | (xstate_enabled ? DMN_W32_CTX_INTEL_XSTATE : 0);
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DWORD size = 0;
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InitializeContext(0, ctx_flags, 0, &size);
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if(GetLastError() == ERROR_INSUFFICIENT_BUFFER)
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@@ -707,18 +703,9 @@ dmn_w32_thread_read_reg_block(Architecture arch, HANDLE thread, void *reg_block)
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}
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//- rjf: unpack features available on this context
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B32 avx_available = 0;
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if(ctx != 0)
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if (xstate_enabled)
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{
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if(avx_enabled)
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{
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SetXStateFeaturesMask(ctx, XSTATE_MASK_AVX);
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}
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DWORD64 xstate_flags = 0;
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if(GetXStateFeaturesMask(ctx, &xstate_flags))
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{
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avx_available = !!(xstate_flags & XSTATE_MASK_AVX);
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}
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SetXStateFeaturesMask(ctx, XSTATE_MASK_AVX | XSTATE_MASK_AVX512);
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}
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//- rjf: get thread context
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@@ -733,6 +720,9 @@ dmn_w32_thread_read_reg_block(Architecture arch, HANDLE thread, void *reg_block)
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break;
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}
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result = 1;
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DWORD64 xstate_mask = 0;
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GetXStateFeaturesMask(ctx, &xstate_mask);
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//- rjf: convert context -> REGS_RegBlockX64
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XSAVE_FORMAT *xsave = &ctx->FltSave;
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@@ -786,35 +776,93 @@ dmn_w32_thread_read_reg_block(Architecture arch, HANDLE thread, void *reg_block)
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MemoryCopy(float_d, float_s, sizeof(*float_d));
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}
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}
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if(!avx_available)
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// SSE registers are always available in x64
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{
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M128A *xmm_s = xsave->XmmRegisters;
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REGS_Reg256 *xmm_d = &dst->ymm0;
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for(U32 n = 0; n < 16; n += 1, xmm_s += 1, xmm_d += 1)
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REGS_Reg512 *zmm_d = &dst->zmm0;
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for(U32 n = 0; n < 16; n += 1, xmm_s += 1, zmm_d += 1)
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{
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MemoryCopy(xmm_d, xmm_s, sizeof(*xmm_s));
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MemoryCopy(zmm_d, xmm_s, sizeof(*xmm_s));
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}
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}
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if(avx_available)
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// AVX
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if(xstate_mask & XSTATE_MASK_AVX)
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{
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DWORD part0_length = 0;
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M128A *part0 = (M128A*)LocateXStateFeature(ctx, XSTATE_LEGACY_SSE, &part0_length);
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DWORD part1_length = 0;
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M128A *part1 = (M128A*)LocateXStateFeature(ctx, XSTATE_AVX, &part1_length);
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Assert(part0_length == part1_length);
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DWORD count = part0_length/sizeof(part0[0]);
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count = ClampTop(count, 16);
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REGS_Reg256 *ymm_d = &dst->ymm0;
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for (DWORD i = 0; i < count; i += 1, part0 += 1, part1 += 1, ymm_d += 1)
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DWORD avx_length = 0;
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U8* avx_s = (U8*)LocateXStateFeature(ctx, XSTATE_AVX, &avx_length);
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Assert(avx_length == 16 * sizeof(REGS_Reg128));
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REGS_Reg512 *zmm_d = &dst->zmm0;
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for(U32 n = 0; n < 16; n += 1, avx_s += sizeof(REGS_Reg128), zmm_d += 1)
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{
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// TODO(rjf): confirm ordering of writes
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ymm_d->u64[3] = part0->Low;
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ymm_d->u64[2] = part0->High;
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ymm_d->u64[1] = part1->Low;
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ymm_d->u64[0] = part1->High;
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MemoryCopy(&zmm_d->v[16], avx_s, sizeof(REGS_Reg128));
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}
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}
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else
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{
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REGS_Reg512 *zmm_d = &dst->zmm0;
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for(U32 n = 0; n < 16; n += 1, zmm_d += 1)
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{
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MemoryZero(&zmm_d->v[16], sizeof(REGS_Reg128));
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}
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}
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// AVX-512
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if(xstate_mask & XSTATE_MASK_AVX512)
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{
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DWORD kmask_length = 0;
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U64* kmask_s = (U64*)LocateXStateFeature(ctx, XSTATE_AVX512_KMASK, &kmask_length);
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Assert(kmask_length == 8 * sizeof(U64));
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REGS_Reg64 *kmask_d = &dst->k0;
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for(U32 n = 0; n < 8; n += 1, kmask_s += 1, kmask_d += 1)
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{
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MemoryCopy(kmask_d, kmask_s, sizeof(*kmask_s));
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}
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DWORD avx512h_length = 0;
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U8* avx512h_s = (U8*)LocateXStateFeature(ctx, XSTATE_AVX512_ZMM_H, &avx512h_length);
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Assert(avx512h_length == 16 * sizeof(REGS_Reg256));
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REGS_Reg512 *zmmh_d = &dst->zmm0;
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for(U32 n = 0; n < 16; n += 1, avx512h_s += sizeof(REGS_Reg256), zmmh_d += 1)
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{
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MemoryCopy(&zmmh_d->v[32], avx512h_s, sizeof(REGS_Reg256));
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}
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DWORD avx512_length = 0;
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U8* avx512_s = (U8*)LocateXStateFeature(ctx, XSTATE_AVX512_ZMM, &avx512_length);
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Assert(avx512_length == 16 * sizeof(REGS_Reg512));
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REGS_Reg512 *zmm_d = &dst->zmm16;
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for(U32 n = 0; n < 16; n += 1, avx512_s += sizeof(REGS_Reg512), zmm_d += 1)
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{
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MemoryCopy(zmm_d, avx512_s, sizeof(REGS_Reg512));
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}
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}
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else
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{
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REGS_Reg64 *kmask_d = &dst->k0;
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for(U32 n = 0; n < 8; n += 1, kmask_d += 1)
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{
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MemoryZero(kmask_d, sizeof(*kmask_d));
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}
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REGS_Reg512 *zmmh_d = &dst->zmm0;
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for(U32 n = 0; n < 16; n += 1, zmmh_d += 1)
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{
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MemoryZero(&zmmh_d->v[32], sizeof(REGS_Reg256));
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}
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REGS_Reg512 *zmm_d = &dst->zmm16;
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for(U32 n = 0; n < 16; n += 1, zmm_d += 1)
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{
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MemoryZero(zmm_d, sizeof(*zmm_d));
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}
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}
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scratch_end(scratch);
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}break;
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}
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@@ -917,15 +965,11 @@ dmn_w32_thread_write_reg_block(Architecture arch, HANDLE thread, void *reg_block
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//- rjf: unpack info about available features
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U32 feature_mask = GetEnabledXStateFeatures();
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B32 avx_enabled = !!(feature_mask & XSTATE_MASK_AVX);
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B32 xstate_enabled = (feature_mask & (XSTATE_MASK_AVX | XSTATE_MASK_AVX512)) != 0;
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//- rjf: set up context
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CONTEXT *ctx = 0;
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U32 ctx_flags = DMN_W32_CTX_X64_ALL;
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if(avx_enabled)
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{
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ctx_flags |= DMN_W32_CTX_INTEL_XSTATE;
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}
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U32 ctx_flags = DMN_W32_CTX_X64_ALL | (xstate_enabled ? DMN_W32_CTX_INTEL_XSTATE : 0);
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DWORD size = 0;
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InitializeContext(0, ctx_flags, 0, &size);
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if(GetLastError() == ERROR_INSUFFICIENT_BUFFER)
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@@ -938,30 +982,14 @@ dmn_w32_thread_write_reg_block(Architecture arch, HANDLE thread, void *reg_block
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}
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//- rjf: unpack features available on this context
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B32 avx_available = 0;
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if(ctx != 0)
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if (xstate_enabled)
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{
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if(avx_enabled)
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{
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SetXStateFeaturesMask(ctx, XSTATE_MASK_AVX);
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}
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DWORD64 xstate_flags = 0;
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if(GetXStateFeaturesMask(ctx, &xstate_flags))
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{
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avx_available = !!(xstate_flags & XSTATE_MASK_AVX);
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}
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SetXStateFeaturesMask(ctx, XSTATE_MASK_AVX | XSTATE_MASK_AVX512);
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}
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//- rjf: get thread context
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if(!GetThreadContext(thread, ctx))
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{
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ctx = 0;
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}
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//- rjf: bad context -> abort
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if(ctx == 0)
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{
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DWORD error = GetLastError();
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break;
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}
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@@ -1015,35 +1043,65 @@ dmn_w32_thread_write_reg_block(Architecture arch, HANDLE thread, void *reg_block
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MemoryCopy(float_d, float_s, 10);
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}
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}
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if(!avx_available)
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// SSE registers are always available in x64
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{
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M128A *xmm_d = fxsave->XmmRegisters;
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REGS_Reg256 *xmm_s = &src->ymm0;
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for(U32 n = 0; n < 8; n += 1, xmm_d += 1, xmm_s += 1)
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REGS_Reg512 *zmm_s = &src->zmm0;
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for(U32 n = 0; n < 16; n += 1, xmm_d += 1, zmm_s += 1)
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{
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MemoryCopy(xmm_d, xmm_s, sizeof(*xmm_d));
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MemoryCopy(xmm_d, zmm_s, sizeof(*xmm_d));
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}
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}
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if(avx_available)
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// AVX
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if(feature_mask & XSTATE_MASK_AVX)
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{
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DWORD part0_length = 0;
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M128A *part0 = (M128A*)LocateXStateFeature(ctx, XSTATE_LEGACY_SSE, &part0_length);
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DWORD part1_length = 0;
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M128A *part1 = (M128A*)LocateXStateFeature(ctx, XSTATE_AVX, &part1_length);
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Assert(part0_length == part1_length);
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DWORD count = part0_length/sizeof(part0[0]);
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count = ClampTop(count, 16);
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REGS_Reg256 *ymm_d = &src->ymm0;
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for(DWORD i = 0; i < count; i += 1, part0 += 1, part1 += 1, ymm_d += 1)
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DWORD avx_length = 0;
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U8* avx_d = (U8*)LocateXStateFeature(ctx, XSTATE_AVX, &avx_length);
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Assert(avx_length == 16 * sizeof(REGS_Reg128));
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REGS_Reg512 *zmm_s = &src->zmm0;
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for(U32 n = 0; n < 16; n += 1, avx_d += sizeof(REGS_Reg128), zmm_s += 1)
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{
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// TODO(allen): Are we writing these out in the right order? Seems weird right?
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part0->Low = ymm_d->u64[3];
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part0->High = ymm_d->u64[2];
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part1->Low = ymm_d->u64[1];
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part1->High = ymm_d->u64[0];
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MemoryCopy(avx_d, &zmm_s->v[16], sizeof(REGS_Reg128));
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}
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}
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// AVX-512
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if(feature_mask & XSTATE_MASK_AVX512)
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{
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DWORD kmask_length = 0;
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U64* kmask_d = (U64*)LocateXStateFeature(ctx, XSTATE_AVX512_KMASK, &kmask_length);
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Assert(kmask_length == 8 * sizeof(*kmask_d));
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REGS_Reg64 *kmask_s = &src->k0;
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for(U32 n = 0; n < 8; n += 1, kmask_s += 1, kmask_d += 1)
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{
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MemoryCopy(kmask_d, kmask_s, sizeof(*kmask_d));
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}
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DWORD avx512h_length = 0;
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U8* avx512h_d = (U8*)LocateXStateFeature(ctx, XSTATE_AVX512_ZMM_H, &avx512h_length);
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Assert(avx512h_length == 16 * sizeof(REGS_Reg256));
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REGS_Reg512 *zmmh_s = &src->zmm0;
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for(U32 n = 0; n < 16; n += 1, avx512h_d += sizeof(REGS_Reg256), zmmh_s += 1)
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{
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MemoryCopy(avx512h_d, &zmmh_s->v[32], sizeof(REGS_Reg256));
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}
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DWORD avx512_length = 0;
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U8* avx512_d = (U8*)LocateXStateFeature(ctx, XSTATE_AVX512_ZMM, &avx512_length);
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Assert(avx512_length == 16 * sizeof(REGS_Reg512));
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REGS_Reg512 *zmm_s = &src->zmm16;
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for(U32 n = 0; n < 16; n += 1, avx512_d += sizeof(REGS_Reg512), zmm_s += 1)
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{
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MemoryCopy(avx512_d, zmm_s, sizeof(REGS_Reg512));
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}
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}
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//- rjf: set thread context
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if(SetThreadContext(thread, ctx))
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{
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