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https://github.com/Ed94/raddebugger.git
synced 2026-07-17 23:01:25 -07:00
define synchronization primitive interface in base layer, implement using os layer; convert all usage -> base layer; use base sync primitives in lane tctx info
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@@ -21,7 +21,7 @@ tctx_alloc(void)
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TCTX *tctx = push_array(arena, TCTX, 1);
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tctx->arenas[0] = arena;
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tctx->arenas[1] = arena_alloc();
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tctx->lane_count = 1;
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tctx->lane_ctx.lane_count = 1;
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return tctx;
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}
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@@ -76,27 +76,23 @@ tctx_get_scratch(Arena **conflicts, U64 count)
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//- rjf: lane metadata
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internal void
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tctx_set_lane_info(U64 lane_idx, U64 lane_count)
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tctx_set_lane_ctx(LaneCtx lane_ctx)
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{
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TCTX *tctx = tctx_selected();
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OS_Handle barrier = os_barrier_alloc(lane_count);
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tctx->lane_idx = lane_idx;
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tctx->lane_count = lane_count;
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tctx->lane_barrier_id = barrier.u64[0];
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tctx->lane_ctx = lane_ctx;
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}
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internal void
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tctx_lane_barrier_wait(void)
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{
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TCTX *tctx = tctx_selected();
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OS_Handle barrier = {tctx->lane_barrier_id};
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os_barrier_wait(barrier);
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os_barrier_wait(tctx->lane_ctx.barrier);
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}
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internal Rng1U64
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tctx_lane_idx_range_from_count(U64 count)
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{
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U64 idxes_per_lane = count/lane_count();
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U64 idxes_per_lane = (count + lane_count()-1) / lane_count();
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U64 lane_base_idx = lane_idx()*idxes_per_lane;
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U64 lane_opl_idx = lane_base_idx + idxes_per_lane;
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U64 lane_opl_idx__clamped = Min(lane_opl_idx, count);
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