mirror of
https://github.com/Ed94/raddebugger.git
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eliminate os_core, move into base; eliminate regs, move into arch abstraction layer, define x64 regs in x64 layer; move win32 backend for os core (now base) functionality to top-level win32 layer
This commit is contained in:
Ryan Fleury
@@ -0,0 +1,780 @@
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// Copyright (c) Epic Games Tools
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// Licensed under the MIT license (https://opensource.org/license/mit/)
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//- GENERATED CODE
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C_LINKAGE_BEGIN
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B8 x64_reg_code_is_vector_table[189] =
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{
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0,
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0,
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0,
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0,
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0,
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1,
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1,
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1,
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1,
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1,
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0,
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1,
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1,
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1,
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1,
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};
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String8 x64_reg_code_name_table[189] =
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{
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str8_lit_comp("nil"),
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str8_lit_comp("rax"),
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str8_lit_comp("rcx"),
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str8_lit_comp("rdx"),
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str8_lit_comp("rbx"),
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str8_lit_comp("rsp"),
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str8_lit_comp("rbp"),
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str8_lit_comp("rsi"),
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str8_lit_comp("rdi"),
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str8_lit_comp("r8"),
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str8_lit_comp("r9"),
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str8_lit_comp("r10"),
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str8_lit_comp("r11"),
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str8_lit_comp("r12"),
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str8_lit_comp("r13"),
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str8_lit_comp("r14"),
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str8_lit_comp("r15"),
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str8_lit_comp("fsbase"),
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str8_lit_comp("gsbase"),
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str8_lit_comp("rip"),
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str8_lit_comp("rflags"),
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str8_lit_comp("dr0"),
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str8_lit_comp("dr1"),
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str8_lit_comp("dr2"),
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str8_lit_comp("dr3"),
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str8_lit_comp("dr4"),
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str8_lit_comp("dr5"),
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str8_lit_comp("dr6"),
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str8_lit_comp("dr7"),
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str8_lit_comp("st0"),
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str8_lit_comp("st1"),
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str8_lit_comp("st2"),
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str8_lit_comp("st3"),
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str8_lit_comp("st4"),
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str8_lit_comp("st5"),
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str8_lit_comp("st6"),
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str8_lit_comp("st7"),
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str8_lit_comp("fcw"),
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str8_lit_comp("fsw"),
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str8_lit_comp("ftw"),
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str8_lit_comp("fop"),
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str8_lit_comp("fcs"),
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str8_lit_comp("fds"),
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str8_lit_comp("fip"),
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str8_lit_comp("fdp"),
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str8_lit_comp("mxcsr"),
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str8_lit_comp("mxcsr_mask"),
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str8_lit_comp("ss"),
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str8_lit_comp("cs"),
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str8_lit_comp("ds"),
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str8_lit_comp("es"),
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str8_lit_comp("fs"),
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str8_lit_comp("gs"),
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str8_lit_comp("zmm0"),
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str8_lit_comp("zmm1"),
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str8_lit_comp("zmm2"),
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str8_lit_comp("zmm3"),
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str8_lit_comp("zmm4"),
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str8_lit_comp("zmm5"),
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str8_lit_comp("zmm6"),
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str8_lit_comp("zmm7"),
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str8_lit_comp("zmm8"),
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str8_lit_comp("zmm9"),
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str8_lit_comp("zmm10"),
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str8_lit_comp("zmm11"),
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str8_lit_comp("zmm12"),
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str8_lit_comp("zmm13"),
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str8_lit_comp("zmm14"),
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str8_lit_comp("zmm15"),
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str8_lit_comp("zmm16"),
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str8_lit_comp("zmm17"),
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str8_lit_comp("zmm18"),
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str8_lit_comp("zmm19"),
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str8_lit_comp("zmm20"),
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str8_lit_comp("zmm21"),
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str8_lit_comp("zmm22"),
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str8_lit_comp("zmm23"),
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str8_lit_comp("zmm24"),
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str8_lit_comp("zmm25"),
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str8_lit_comp("zmm26"),
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str8_lit_comp("zmm27"),
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str8_lit_comp("zmm28"),
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str8_lit_comp("zmm29"),
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str8_lit_comp("zmm30"),
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str8_lit_comp("zmm31"),
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str8_lit_comp("k0"),
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str8_lit_comp("k1"),
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str8_lit_comp("k2"),
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str8_lit_comp("k3"),
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str8_lit_comp("k4"),
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str8_lit_comp("k5"),
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str8_lit_comp("k6"),
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str8_lit_comp("k7"),
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str8_lit_comp("cetmsr"),
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str8_lit_comp("cetssp"),
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str8_lit_comp("eax"),
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str8_lit_comp("ecx"),
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str8_lit_comp("edx"),
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str8_lit_comp("ebx"),
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str8_lit_comp("esp"),
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str8_lit_comp("ebp"),
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str8_lit_comp("esi"),
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str8_lit_comp("edi"),
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str8_lit_comp("r8d"),
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str8_lit_comp("r9d"),
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str8_lit_comp("r10d"),
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str8_lit_comp("r11d"),
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str8_lit_comp("r12d"),
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str8_lit_comp("r13d"),
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str8_lit_comp("r14d"),
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str8_lit_comp("r15d"),
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str8_lit_comp("eflags"),
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str8_lit_comp("ax"),
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str8_lit_comp("cx"),
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str8_lit_comp("dx"),
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str8_lit_comp("bx"),
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str8_lit_comp("si"),
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str8_lit_comp("di"),
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str8_lit_comp("sp"),
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str8_lit_comp("bp"),
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str8_lit_comp("ip"),
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str8_lit_comp("r8w"),
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str8_lit_comp("r9w"),
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str8_lit_comp("r10w"),
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str8_lit_comp("r11w"),
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str8_lit_comp("r12w"),
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str8_lit_comp("r13w"),
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str8_lit_comp("r14w"),
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str8_lit_comp("r15w"),
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str8_lit_comp("al"),
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str8_lit_comp("cl"),
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str8_lit_comp("dl"),
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str8_lit_comp("bl"),
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str8_lit_comp("sil"),
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str8_lit_comp("dil"),
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str8_lit_comp("bpl"),
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str8_lit_comp("spl"),
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str8_lit_comp("r8b"),
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str8_lit_comp("r9b"),
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str8_lit_comp("r10b"),
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str8_lit_comp("r11b"),
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str8_lit_comp("r12b"),
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str8_lit_comp("r13b"),
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str8_lit_comp("r14b"),
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str8_lit_comp("r15b"),
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str8_lit_comp("ah"),
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str8_lit_comp("ch"),
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str8_lit_comp("dh"),
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str8_lit_comp("bh"),
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str8_lit_comp("xmm0"),
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str8_lit_comp("xmm1"),
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str8_lit_comp("xmm2"),
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str8_lit_comp("xmm3"),
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str8_lit_comp("xmm4"),
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str8_lit_comp("xmm5"),
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str8_lit_comp("xmm6"),
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str8_lit_comp("xmm7"),
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str8_lit_comp("xmm8"),
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str8_lit_comp("xmm9"),
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str8_lit_comp("xmm10"),
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str8_lit_comp("xmm11"),
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str8_lit_comp("xmm12"),
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str8_lit_comp("xmm13"),
|
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str8_lit_comp("xmm14"),
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str8_lit_comp("xmm15"),
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str8_lit_comp("ymm0"),
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str8_lit_comp("ymm1"),
|
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str8_lit_comp("ymm2"),
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str8_lit_comp("ymm3"),
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str8_lit_comp("ymm4"),
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str8_lit_comp("ymm5"),
|
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str8_lit_comp("ymm6"),
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str8_lit_comp("ymm7"),
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str8_lit_comp("ymm8"),
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str8_lit_comp("ymm9"),
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str8_lit_comp("ymm10"),
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str8_lit_comp("ymm11"),
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str8_lit_comp("ymm12"),
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str8_lit_comp("ymm13"),
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str8_lit_comp("ymm14"),
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str8_lit_comp("ymm15"),
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str8_lit_comp("mm0"),
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str8_lit_comp("mm1"),
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str8_lit_comp("mm2"),
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str8_lit_comp("mm3"),
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str8_lit_comp("mm4"),
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str8_lit_comp("mm5"),
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||||
str8_lit_comp("mm6"),
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||||
str8_lit_comp("mm7"),
|
||||
};
|
||||
|
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U8 x64_reg_code_base_table[189] =
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||||
{
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||||
0,
|
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0,
|
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0,
|
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0,
|
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0,
|
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
|
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0,
|
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0,
|
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0,
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0,
|
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|
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0,
|
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0,
|
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0,
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|
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|
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|
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|
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|
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|
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|
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|
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|
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0,
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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0,
|
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0,
|
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0,
|
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0,
|
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|
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0,
|
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0,
|
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0,
|
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0,
|
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0,
|
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0,
|
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0,
|
||||
0,
|
||||
X64_RegCode_rax,
|
||||
X64_RegCode_rcx,
|
||||
X64_RegCode_rdx,
|
||||
X64_RegCode_rbx,
|
||||
X64_RegCode_rsp,
|
||||
X64_RegCode_rbp,
|
||||
X64_RegCode_rsi,
|
||||
X64_RegCode_rdi,
|
||||
X64_RegCode_r8,
|
||||
X64_RegCode_r9,
|
||||
X64_RegCode_r10,
|
||||
X64_RegCode_r11,
|
||||
X64_RegCode_r12,
|
||||
X64_RegCode_r13,
|
||||
X64_RegCode_r14,
|
||||
X64_RegCode_r15,
|
||||
X64_RegCode_rflags,
|
||||
X64_RegCode_rax,
|
||||
X64_RegCode_rcx,
|
||||
X64_RegCode_rdx,
|
||||
X64_RegCode_rbx,
|
||||
X64_RegCode_rsi,
|
||||
X64_RegCode_rdi,
|
||||
X64_RegCode_rsp,
|
||||
X64_RegCode_rbp,
|
||||
X64_RegCode_rip,
|
||||
X64_RegCode_r8,
|
||||
X64_RegCode_r9,
|
||||
X64_RegCode_r10,
|
||||
X64_RegCode_r11,
|
||||
X64_RegCode_r12,
|
||||
X64_RegCode_r13,
|
||||
X64_RegCode_r14,
|
||||
X64_RegCode_r15,
|
||||
X64_RegCode_rax,
|
||||
X64_RegCode_rcx,
|
||||
X64_RegCode_rdx,
|
||||
X64_RegCode_rbx,
|
||||
X64_RegCode_rsi,
|
||||
X64_RegCode_rdi,
|
||||
X64_RegCode_rbp,
|
||||
X64_RegCode_rsp,
|
||||
X64_RegCode_r8,
|
||||
X64_RegCode_r9,
|
||||
X64_RegCode_r10,
|
||||
X64_RegCode_r11,
|
||||
X64_RegCode_r12,
|
||||
X64_RegCode_r13,
|
||||
X64_RegCode_r14,
|
||||
X64_RegCode_r15,
|
||||
X64_RegCode_rax,
|
||||
X64_RegCode_rcx,
|
||||
X64_RegCode_rdx,
|
||||
X64_RegCode_rbx,
|
||||
X64_RegCode_zmm0,
|
||||
X64_RegCode_zmm1,
|
||||
X64_RegCode_zmm2,
|
||||
X64_RegCode_zmm3,
|
||||
X64_RegCode_zmm4,
|
||||
X64_RegCode_zmm5,
|
||||
X64_RegCode_zmm6,
|
||||
X64_RegCode_zmm7,
|
||||
X64_RegCode_zmm8,
|
||||
X64_RegCode_zmm9,
|
||||
X64_RegCode_zmm10,
|
||||
X64_RegCode_zmm11,
|
||||
X64_RegCode_zmm12,
|
||||
X64_RegCode_zmm13,
|
||||
X64_RegCode_zmm14,
|
||||
X64_RegCode_zmm15,
|
||||
X64_RegCode_zmm0,
|
||||
X64_RegCode_zmm1,
|
||||
X64_RegCode_zmm2,
|
||||
X64_RegCode_zmm3,
|
||||
X64_RegCode_zmm4,
|
||||
X64_RegCode_zmm5,
|
||||
X64_RegCode_zmm6,
|
||||
X64_RegCode_zmm7,
|
||||
X64_RegCode_zmm8,
|
||||
X64_RegCode_zmm9,
|
||||
X64_RegCode_zmm10,
|
||||
X64_RegCode_zmm11,
|
||||
X64_RegCode_zmm12,
|
||||
X64_RegCode_zmm13,
|
||||
X64_RegCode_zmm14,
|
||||
X64_RegCode_zmm15,
|
||||
X64_RegCode_st0,
|
||||
X64_RegCode_st1,
|
||||
X64_RegCode_st2,
|
||||
X64_RegCode_st3,
|
||||
X64_RegCode_st4,
|
||||
X64_RegCode_st5,
|
||||
X64_RegCode_st6,
|
||||
X64_RegCode_st7,
|
||||
};
|
||||
|
||||
Rng1U16 x64_reg_code_rng_table[189] =
|
||||
{
|
||||
{0},
|
||||
{(U16)OffsetOf(X64_RegBlock, rax), (U16)OffsetOf(X64_RegBlock, rax) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, rcx), (U16)OffsetOf(X64_RegBlock, rcx) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, rdx), (U16)OffsetOf(X64_RegBlock, rdx) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, rbx), (U16)OffsetOf(X64_RegBlock, rbx) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, rsp), (U16)OffsetOf(X64_RegBlock, rsp) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, rbp), (U16)OffsetOf(X64_RegBlock, rbp) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, rsi), (U16)OffsetOf(X64_RegBlock, rsi) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, rdi), (U16)OffsetOf(X64_RegBlock, rdi) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, r8), (U16)OffsetOf(X64_RegBlock, r8) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, r9), (U16)OffsetOf(X64_RegBlock, r9) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, r10), (U16)OffsetOf(X64_RegBlock, r10) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, r11), (U16)OffsetOf(X64_RegBlock, r11) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, r12), (U16)OffsetOf(X64_RegBlock, r12) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, r13), (U16)OffsetOf(X64_RegBlock, r13) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, r14), (U16)OffsetOf(X64_RegBlock, r14) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, r15), (U16)OffsetOf(X64_RegBlock, r15) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, fsbase), (U16)OffsetOf(X64_RegBlock, fsbase) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, gsbase), (U16)OffsetOf(X64_RegBlock, gsbase) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, rip), (U16)OffsetOf(X64_RegBlock, rip) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, rflags), (U16)OffsetOf(X64_RegBlock, rflags) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, dr0), (U16)OffsetOf(X64_RegBlock, dr0) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, dr1), (U16)OffsetOf(X64_RegBlock, dr1) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, dr2), (U16)OffsetOf(X64_RegBlock, dr2) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, dr3), (U16)OffsetOf(X64_RegBlock, dr3) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, dr4), (U16)OffsetOf(X64_RegBlock, dr4) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, dr5), (U16)OffsetOf(X64_RegBlock, dr5) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, dr6), (U16)OffsetOf(X64_RegBlock, dr6) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, dr7), (U16)OffsetOf(X64_RegBlock, dr7) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, st0), (U16)OffsetOf(X64_RegBlock, st0) + 10},
|
||||
{(U16)OffsetOf(X64_RegBlock, st1), (U16)OffsetOf(X64_RegBlock, st1) + 10},
|
||||
{(U16)OffsetOf(X64_RegBlock, st2), (U16)OffsetOf(X64_RegBlock, st2) + 10},
|
||||
{(U16)OffsetOf(X64_RegBlock, st3), (U16)OffsetOf(X64_RegBlock, st3) + 10},
|
||||
{(U16)OffsetOf(X64_RegBlock, st4), (U16)OffsetOf(X64_RegBlock, st4) + 10},
|
||||
{(U16)OffsetOf(X64_RegBlock, st5), (U16)OffsetOf(X64_RegBlock, st5) + 10},
|
||||
{(U16)OffsetOf(X64_RegBlock, st6), (U16)OffsetOf(X64_RegBlock, st6) + 10},
|
||||
{(U16)OffsetOf(X64_RegBlock, st7), (U16)OffsetOf(X64_RegBlock, st7) + 10},
|
||||
{(U16)OffsetOf(X64_RegBlock, fcw), (U16)OffsetOf(X64_RegBlock, fcw) + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, fsw), (U16)OffsetOf(X64_RegBlock, fsw) + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, ftw), (U16)OffsetOf(X64_RegBlock, ftw) + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, fop), (U16)OffsetOf(X64_RegBlock, fop) + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, fcs), (U16)OffsetOf(X64_RegBlock, fcs) + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, fds), (U16)OffsetOf(X64_RegBlock, fds) + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, fip), (U16)OffsetOf(X64_RegBlock, fip) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, fdp), (U16)OffsetOf(X64_RegBlock, fdp) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, mxcsr), (U16)OffsetOf(X64_RegBlock, mxcsr) + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, mxcsr_mask), (U16)OffsetOf(X64_RegBlock, mxcsr_mask) + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, ss), (U16)OffsetOf(X64_RegBlock, ss) + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, cs), (U16)OffsetOf(X64_RegBlock, cs) + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, ds), (U16)OffsetOf(X64_RegBlock, ds) + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, es), (U16)OffsetOf(X64_RegBlock, es) + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, fs), (U16)OffsetOf(X64_RegBlock, fs) + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, gs), (U16)OffsetOf(X64_RegBlock, gs) + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm0), (U16)OffsetOf(X64_RegBlock, zmm0) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm1), (U16)OffsetOf(X64_RegBlock, zmm1) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm2), (U16)OffsetOf(X64_RegBlock, zmm2) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm3), (U16)OffsetOf(X64_RegBlock, zmm3) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm4), (U16)OffsetOf(X64_RegBlock, zmm4) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm5), (U16)OffsetOf(X64_RegBlock, zmm5) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm6), (U16)OffsetOf(X64_RegBlock, zmm6) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm7), (U16)OffsetOf(X64_RegBlock, zmm7) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm8), (U16)OffsetOf(X64_RegBlock, zmm8) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm9), (U16)OffsetOf(X64_RegBlock, zmm9) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm10), (U16)OffsetOf(X64_RegBlock, zmm10) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm11), (U16)OffsetOf(X64_RegBlock, zmm11) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm12), (U16)OffsetOf(X64_RegBlock, zmm12) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm13), (U16)OffsetOf(X64_RegBlock, zmm13) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm14), (U16)OffsetOf(X64_RegBlock, zmm14) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm15), (U16)OffsetOf(X64_RegBlock, zmm15) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm16), (U16)OffsetOf(X64_RegBlock, zmm16) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm17), (U16)OffsetOf(X64_RegBlock, zmm17) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm18), (U16)OffsetOf(X64_RegBlock, zmm18) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm19), (U16)OffsetOf(X64_RegBlock, zmm19) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm20), (U16)OffsetOf(X64_RegBlock, zmm20) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm21), (U16)OffsetOf(X64_RegBlock, zmm21) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm22), (U16)OffsetOf(X64_RegBlock, zmm22) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm23), (U16)OffsetOf(X64_RegBlock, zmm23) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm24), (U16)OffsetOf(X64_RegBlock, zmm24) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm25), (U16)OffsetOf(X64_RegBlock, zmm25) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm26), (U16)OffsetOf(X64_RegBlock, zmm26) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm27), (U16)OffsetOf(X64_RegBlock, zmm27) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm28), (U16)OffsetOf(X64_RegBlock, zmm28) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm29), (U16)OffsetOf(X64_RegBlock, zmm29) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm30), (U16)OffsetOf(X64_RegBlock, zmm30) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm31), (U16)OffsetOf(X64_RegBlock, zmm31) + 64},
|
||||
{(U16)OffsetOf(X64_RegBlock, k0), (U16)OffsetOf(X64_RegBlock, k0) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, k1), (U16)OffsetOf(X64_RegBlock, k1) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, k2), (U16)OffsetOf(X64_RegBlock, k2) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, k3), (U16)OffsetOf(X64_RegBlock, k3) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, k4), (U16)OffsetOf(X64_RegBlock, k4) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, k5), (U16)OffsetOf(X64_RegBlock, k5) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, k6), (U16)OffsetOf(X64_RegBlock, k6) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, k7), (U16)OffsetOf(X64_RegBlock, k7) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, cetmsr), (U16)OffsetOf(X64_RegBlock, cetmsr) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, cetssp), (U16)OffsetOf(X64_RegBlock, cetssp) + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, rax) + 0, (U16)OffsetOf(X64_RegBlock, rax) + 0 + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, rcx) + 0, (U16)OffsetOf(X64_RegBlock, rcx) + 0 + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, rdx) + 0, (U16)OffsetOf(X64_RegBlock, rdx) + 0 + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, rbx) + 0, (U16)OffsetOf(X64_RegBlock, rbx) + 0 + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, rsp) + 0, (U16)OffsetOf(X64_RegBlock, rsp) + 0 + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, rbp) + 0, (U16)OffsetOf(X64_RegBlock, rbp) + 0 + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, rsi) + 0, (U16)OffsetOf(X64_RegBlock, rsi) + 0 + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, rdi) + 0, (U16)OffsetOf(X64_RegBlock, rdi) + 0 + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, r8) + 0, (U16)OffsetOf(X64_RegBlock, r8) + 0 + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, r9) + 0, (U16)OffsetOf(X64_RegBlock, r9) + 0 + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, r10) + 0, (U16)OffsetOf(X64_RegBlock, r10) + 0 + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, r11) + 0, (U16)OffsetOf(X64_RegBlock, r11) + 0 + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, r12) + 0, (U16)OffsetOf(X64_RegBlock, r12) + 0 + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, r13) + 0, (U16)OffsetOf(X64_RegBlock, r13) + 0 + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, r14) + 0, (U16)OffsetOf(X64_RegBlock, r14) + 0 + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, r15) + 0, (U16)OffsetOf(X64_RegBlock, r15) + 0 + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, rflags) + 0, (U16)OffsetOf(X64_RegBlock, rflags) + 0 + 4},
|
||||
{(U16)OffsetOf(X64_RegBlock, rax) + 0, (U16)OffsetOf(X64_RegBlock, rax) + 0 + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, rcx) + 0, (U16)OffsetOf(X64_RegBlock, rcx) + 0 + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, rdx) + 0, (U16)OffsetOf(X64_RegBlock, rdx) + 0 + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, rbx) + 0, (U16)OffsetOf(X64_RegBlock, rbx) + 0 + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, rsi) + 0, (U16)OffsetOf(X64_RegBlock, rsi) + 0 + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, rdi) + 0, (U16)OffsetOf(X64_RegBlock, rdi) + 0 + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, rsp) + 0, (U16)OffsetOf(X64_RegBlock, rsp) + 0 + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, rbp) + 0, (U16)OffsetOf(X64_RegBlock, rbp) + 0 + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, rip) + 0, (U16)OffsetOf(X64_RegBlock, rip) + 0 + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, r8) + 0, (U16)OffsetOf(X64_RegBlock, r8) + 0 + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, r9) + 0, (U16)OffsetOf(X64_RegBlock, r9) + 0 + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, r10) + 0, (U16)OffsetOf(X64_RegBlock, r10) + 0 + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, r11) + 0, (U16)OffsetOf(X64_RegBlock, r11) + 0 + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, r12) + 0, (U16)OffsetOf(X64_RegBlock, r12) + 0 + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, r13) + 0, (U16)OffsetOf(X64_RegBlock, r13) + 0 + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, r14) + 0, (U16)OffsetOf(X64_RegBlock, r14) + 0 + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, r15) + 0, (U16)OffsetOf(X64_RegBlock, r15) + 0 + 2},
|
||||
{(U16)OffsetOf(X64_RegBlock, rax) + 0, (U16)OffsetOf(X64_RegBlock, rax) + 0 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, rcx) + 0, (U16)OffsetOf(X64_RegBlock, rcx) + 0 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, rdx) + 0, (U16)OffsetOf(X64_RegBlock, rdx) + 0 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, rbx) + 0, (U16)OffsetOf(X64_RegBlock, rbx) + 0 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, rsi) + 0, (U16)OffsetOf(X64_RegBlock, rsi) + 0 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, rdi) + 0, (U16)OffsetOf(X64_RegBlock, rdi) + 0 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, rbp) + 0, (U16)OffsetOf(X64_RegBlock, rbp) + 0 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, rsp) + 0, (U16)OffsetOf(X64_RegBlock, rsp) + 0 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, r8) + 0, (U16)OffsetOf(X64_RegBlock, r8) + 0 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, r9) + 0, (U16)OffsetOf(X64_RegBlock, r9) + 0 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, r10) + 0, (U16)OffsetOf(X64_RegBlock, r10) + 0 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, r11) + 0, (U16)OffsetOf(X64_RegBlock, r11) + 0 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, r12) + 0, (U16)OffsetOf(X64_RegBlock, r12) + 0 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, r13) + 0, (U16)OffsetOf(X64_RegBlock, r13) + 0 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, r14) + 0, (U16)OffsetOf(X64_RegBlock, r14) + 0 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, r15) + 0, (U16)OffsetOf(X64_RegBlock, r15) + 0 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, rax) + 1, (U16)OffsetOf(X64_RegBlock, rax) + 1 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, rcx) + 1, (U16)OffsetOf(X64_RegBlock, rcx) + 1 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, rdx) + 1, (U16)OffsetOf(X64_RegBlock, rdx) + 1 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, rbx) + 1, (U16)OffsetOf(X64_RegBlock, rbx) + 1 + 1},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm0) + 0, (U16)OffsetOf(X64_RegBlock, zmm0) + 0 + 16},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm1) + 0, (U16)OffsetOf(X64_RegBlock, zmm1) + 0 + 16},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm2) + 0, (U16)OffsetOf(X64_RegBlock, zmm2) + 0 + 16},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm3) + 0, (U16)OffsetOf(X64_RegBlock, zmm3) + 0 + 16},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm4) + 0, (U16)OffsetOf(X64_RegBlock, zmm4) + 0 + 16},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm5) + 0, (U16)OffsetOf(X64_RegBlock, zmm5) + 0 + 16},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm6) + 0, (U16)OffsetOf(X64_RegBlock, zmm6) + 0 + 16},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm7) + 0, (U16)OffsetOf(X64_RegBlock, zmm7) + 0 + 16},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm8) + 0, (U16)OffsetOf(X64_RegBlock, zmm8) + 0 + 16},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm9) + 0, (U16)OffsetOf(X64_RegBlock, zmm9) + 0 + 16},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm10) + 0, (U16)OffsetOf(X64_RegBlock, zmm10) + 0 + 16},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm11) + 0, (U16)OffsetOf(X64_RegBlock, zmm11) + 0 + 16},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm12) + 0, (U16)OffsetOf(X64_RegBlock, zmm12) + 0 + 16},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm13) + 0, (U16)OffsetOf(X64_RegBlock, zmm13) + 0 + 16},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm14) + 0, (U16)OffsetOf(X64_RegBlock, zmm14) + 0 + 16},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm15) + 0, (U16)OffsetOf(X64_RegBlock, zmm15) + 0 + 16},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm0) + 0, (U16)OffsetOf(X64_RegBlock, zmm0) + 0 + 32},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm1) + 0, (U16)OffsetOf(X64_RegBlock, zmm1) + 0 + 32},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm2) + 0, (U16)OffsetOf(X64_RegBlock, zmm2) + 0 + 32},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm3) + 0, (U16)OffsetOf(X64_RegBlock, zmm3) + 0 + 32},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm4) + 0, (U16)OffsetOf(X64_RegBlock, zmm4) + 0 + 32},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm5) + 0, (U16)OffsetOf(X64_RegBlock, zmm5) + 0 + 32},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm6) + 0, (U16)OffsetOf(X64_RegBlock, zmm6) + 0 + 32},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm7) + 0, (U16)OffsetOf(X64_RegBlock, zmm7) + 0 + 32},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm8) + 0, (U16)OffsetOf(X64_RegBlock, zmm8) + 0 + 32},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm9) + 0, (U16)OffsetOf(X64_RegBlock, zmm9) + 0 + 32},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm10) + 0, (U16)OffsetOf(X64_RegBlock, zmm10) + 0 + 32},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm11) + 0, (U16)OffsetOf(X64_RegBlock, zmm11) + 0 + 32},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm12) + 0, (U16)OffsetOf(X64_RegBlock, zmm12) + 0 + 32},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm13) + 0, (U16)OffsetOf(X64_RegBlock, zmm13) + 0 + 32},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm14) + 0, (U16)OffsetOf(X64_RegBlock, zmm14) + 0 + 32},
|
||||
{(U16)OffsetOf(X64_RegBlock, zmm15) + 0, (U16)OffsetOf(X64_RegBlock, zmm15) + 0 + 32},
|
||||
{(U16)OffsetOf(X64_RegBlock, st0) + 0, (U16)OffsetOf(X64_RegBlock, st0) + 0 + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, st1) + 0, (U16)OffsetOf(X64_RegBlock, st1) + 0 + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, st2) + 0, (U16)OffsetOf(X64_RegBlock, st2) + 0 + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, st3) + 0, (U16)OffsetOf(X64_RegBlock, st3) + 0 + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, st4) + 0, (U16)OffsetOf(X64_RegBlock, st4) + 0 + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, st5) + 0, (U16)OffsetOf(X64_RegBlock, st5) + 0 + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, st6) + 0, (U16)OffsetOf(X64_RegBlock, st6) + 0 + 8},
|
||||
{(U16)OffsetOf(X64_RegBlock, st7) + 0, (U16)OffsetOf(X64_RegBlock, st7) + 0 + 8},
|
||||
};
|
||||
|
||||
C_LINKAGE_END
|
||||
|
||||
@@ -0,0 +1,310 @@
|
||||
// Copyright (c) Epic Games Tools
|
||||
// Licensed under the MIT license (https://opensource.org/license/mit/)
|
||||
|
||||
//- GENERATED CODE
|
||||
|
||||
#ifndef X64_META_H
|
||||
#define X64_META_H
|
||||
|
||||
typedef enum X64_RegCode
|
||||
{
|
||||
X64_RegCode_nil,
|
||||
X64_RegCode_rax,
|
||||
X64_RegCode_rcx,
|
||||
X64_RegCode_rdx,
|
||||
X64_RegCode_rbx,
|
||||
X64_RegCode_rsp,
|
||||
X64_RegCode_rbp,
|
||||
X64_RegCode_rsi,
|
||||
X64_RegCode_rdi,
|
||||
X64_RegCode_r8,
|
||||
X64_RegCode_r9,
|
||||
X64_RegCode_r10,
|
||||
X64_RegCode_r11,
|
||||
X64_RegCode_r12,
|
||||
X64_RegCode_r13,
|
||||
X64_RegCode_r14,
|
||||
X64_RegCode_r15,
|
||||
X64_RegCode_fsbase,
|
||||
X64_RegCode_gsbase,
|
||||
X64_RegCode_rip,
|
||||
X64_RegCode_rflags,
|
||||
X64_RegCode_dr0,
|
||||
X64_RegCode_dr1,
|
||||
X64_RegCode_dr2,
|
||||
X64_RegCode_dr3,
|
||||
X64_RegCode_dr4,
|
||||
X64_RegCode_dr5,
|
||||
X64_RegCode_dr6,
|
||||
X64_RegCode_dr7,
|
||||
X64_RegCode_st0,
|
||||
X64_RegCode_st1,
|
||||
X64_RegCode_st2,
|
||||
X64_RegCode_st3,
|
||||
X64_RegCode_st4,
|
||||
X64_RegCode_st5,
|
||||
X64_RegCode_st6,
|
||||
X64_RegCode_st7,
|
||||
X64_RegCode_fcw,
|
||||
X64_RegCode_fsw,
|
||||
X64_RegCode_ftw,
|
||||
X64_RegCode_fop,
|
||||
X64_RegCode_fcs,
|
||||
X64_RegCode_fds,
|
||||
X64_RegCode_fip,
|
||||
X64_RegCode_fdp,
|
||||
X64_RegCode_mxcsr,
|
||||
X64_RegCode_mxcsr_mask,
|
||||
X64_RegCode_ss,
|
||||
X64_RegCode_cs,
|
||||
X64_RegCode_ds,
|
||||
X64_RegCode_es,
|
||||
X64_RegCode_fs,
|
||||
X64_RegCode_gs,
|
||||
X64_RegCode_zmm0,
|
||||
X64_RegCode_zmm1,
|
||||
X64_RegCode_zmm2,
|
||||
X64_RegCode_zmm3,
|
||||
X64_RegCode_zmm4,
|
||||
X64_RegCode_zmm5,
|
||||
X64_RegCode_zmm6,
|
||||
X64_RegCode_zmm7,
|
||||
X64_RegCode_zmm8,
|
||||
X64_RegCode_zmm9,
|
||||
X64_RegCode_zmm10,
|
||||
X64_RegCode_zmm11,
|
||||
X64_RegCode_zmm12,
|
||||
X64_RegCode_zmm13,
|
||||
X64_RegCode_zmm14,
|
||||
X64_RegCode_zmm15,
|
||||
X64_RegCode_zmm16,
|
||||
X64_RegCode_zmm17,
|
||||
X64_RegCode_zmm18,
|
||||
X64_RegCode_zmm19,
|
||||
X64_RegCode_zmm20,
|
||||
X64_RegCode_zmm21,
|
||||
X64_RegCode_zmm22,
|
||||
X64_RegCode_zmm23,
|
||||
X64_RegCode_zmm24,
|
||||
X64_RegCode_zmm25,
|
||||
X64_RegCode_zmm26,
|
||||
X64_RegCode_zmm27,
|
||||
X64_RegCode_zmm28,
|
||||
X64_RegCode_zmm29,
|
||||
X64_RegCode_zmm30,
|
||||
X64_RegCode_zmm31,
|
||||
X64_RegCode_k0,
|
||||
X64_RegCode_k1,
|
||||
X64_RegCode_k2,
|
||||
X64_RegCode_k3,
|
||||
X64_RegCode_k4,
|
||||
X64_RegCode_k5,
|
||||
X64_RegCode_k6,
|
||||
X64_RegCode_k7,
|
||||
X64_RegCode_cetmsr,
|
||||
X64_RegCode_cetssp,
|
||||
X64_RegCode_eax,
|
||||
X64_RegCode_ecx,
|
||||
X64_RegCode_edx,
|
||||
X64_RegCode_ebx,
|
||||
X64_RegCode_esp,
|
||||
X64_RegCode_ebp,
|
||||
X64_RegCode_esi,
|
||||
X64_RegCode_edi,
|
||||
X64_RegCode_r8d,
|
||||
X64_RegCode_r9d,
|
||||
X64_RegCode_r10d,
|
||||
X64_RegCode_r11d,
|
||||
X64_RegCode_r12d,
|
||||
X64_RegCode_r13d,
|
||||
X64_RegCode_r14d,
|
||||
X64_RegCode_r15d,
|
||||
X64_RegCode_eflags,
|
||||
X64_RegCode_ax,
|
||||
X64_RegCode_cx,
|
||||
X64_RegCode_dx,
|
||||
X64_RegCode_bx,
|
||||
X64_RegCode_si,
|
||||
X64_RegCode_di,
|
||||
X64_RegCode_sp,
|
||||
X64_RegCode_bp,
|
||||
X64_RegCode_ip,
|
||||
X64_RegCode_r8w,
|
||||
X64_RegCode_r9w,
|
||||
X64_RegCode_r10w,
|
||||
X64_RegCode_r11w,
|
||||
X64_RegCode_r12w,
|
||||
X64_RegCode_r13w,
|
||||
X64_RegCode_r14w,
|
||||
X64_RegCode_r15w,
|
||||
X64_RegCode_al,
|
||||
X64_RegCode_cl,
|
||||
X64_RegCode_dl,
|
||||
X64_RegCode_bl,
|
||||
X64_RegCode_sil,
|
||||
X64_RegCode_dil,
|
||||
X64_RegCode_bpl,
|
||||
X64_RegCode_spl,
|
||||
X64_RegCode_r8b,
|
||||
X64_RegCode_r9b,
|
||||
X64_RegCode_r10b,
|
||||
X64_RegCode_r11b,
|
||||
X64_RegCode_r12b,
|
||||
X64_RegCode_r13b,
|
||||
X64_RegCode_r14b,
|
||||
X64_RegCode_r15b,
|
||||
X64_RegCode_ah,
|
||||
X64_RegCode_ch,
|
||||
X64_RegCode_dh,
|
||||
X64_RegCode_bh,
|
||||
X64_RegCode_xmm0,
|
||||
X64_RegCode_xmm1,
|
||||
X64_RegCode_xmm2,
|
||||
X64_RegCode_xmm3,
|
||||
X64_RegCode_xmm4,
|
||||
X64_RegCode_xmm5,
|
||||
X64_RegCode_xmm6,
|
||||
X64_RegCode_xmm7,
|
||||
X64_RegCode_xmm8,
|
||||
X64_RegCode_xmm9,
|
||||
X64_RegCode_xmm10,
|
||||
X64_RegCode_xmm11,
|
||||
X64_RegCode_xmm12,
|
||||
X64_RegCode_xmm13,
|
||||
X64_RegCode_xmm14,
|
||||
X64_RegCode_xmm15,
|
||||
X64_RegCode_ymm0,
|
||||
X64_RegCode_ymm1,
|
||||
X64_RegCode_ymm2,
|
||||
X64_RegCode_ymm3,
|
||||
X64_RegCode_ymm4,
|
||||
X64_RegCode_ymm5,
|
||||
X64_RegCode_ymm6,
|
||||
X64_RegCode_ymm7,
|
||||
X64_RegCode_ymm8,
|
||||
X64_RegCode_ymm9,
|
||||
X64_RegCode_ymm10,
|
||||
X64_RegCode_ymm11,
|
||||
X64_RegCode_ymm12,
|
||||
X64_RegCode_ymm13,
|
||||
X64_RegCode_ymm14,
|
||||
X64_RegCode_ymm15,
|
||||
X64_RegCode_mm0,
|
||||
X64_RegCode_mm1,
|
||||
X64_RegCode_mm2,
|
||||
X64_RegCode_mm3,
|
||||
X64_RegCode_mm4,
|
||||
X64_RegCode_mm5,
|
||||
X64_RegCode_mm6,
|
||||
X64_RegCode_mm7,
|
||||
X64_RegCode_COUNT,
|
||||
} X64_RegCode;
|
||||
|
||||
typedef struct X64_RegBlock X64_RegBlock;
|
||||
struct X64_RegBlock
|
||||
{
|
||||
U64 rax;
|
||||
U64 rcx;
|
||||
U64 rdx;
|
||||
U64 rbx;
|
||||
U64 rsp;
|
||||
U64 rbp;
|
||||
U64 rsi;
|
||||
U64 rdi;
|
||||
U64 r8;
|
||||
U64 r9;
|
||||
U64 r10;
|
||||
U64 r11;
|
||||
U64 r12;
|
||||
U64 r13;
|
||||
U64 r14;
|
||||
U64 r15;
|
||||
U64 fsbase;
|
||||
U64 gsbase;
|
||||
U64 rip;
|
||||
U64 rflags;
|
||||
U64 dr0;
|
||||
U64 dr1;
|
||||
U64 dr2;
|
||||
U64 dr3;
|
||||
U64 dr4;
|
||||
U64 dr5;
|
||||
U64 dr6;
|
||||
U64 dr7;
|
||||
U80 st0;
|
||||
U80 st1;
|
||||
U80 st2;
|
||||
U80 st3;
|
||||
U80 st4;
|
||||
U80 st5;
|
||||
U80 st6;
|
||||
U80 st7;
|
||||
U16 fcw;
|
||||
U16 fsw;
|
||||
U8 ftw;
|
||||
U16 fop;
|
||||
U16 fcs;
|
||||
U16 fds;
|
||||
U64 fip;
|
||||
U64 fdp;
|
||||
U32 mxcsr;
|
||||
U32 mxcsr_mask;
|
||||
U16 ss;
|
||||
U16 cs;
|
||||
U16 ds;
|
||||
U16 es;
|
||||
U16 fs;
|
||||
U16 gs;
|
||||
U512 zmm0;
|
||||
U512 zmm1;
|
||||
U512 zmm2;
|
||||
U512 zmm3;
|
||||
U512 zmm4;
|
||||
U512 zmm5;
|
||||
U512 zmm6;
|
||||
U512 zmm7;
|
||||
U512 zmm8;
|
||||
U512 zmm9;
|
||||
U512 zmm10;
|
||||
U512 zmm11;
|
||||
U512 zmm12;
|
||||
U512 zmm13;
|
||||
U512 zmm14;
|
||||
U512 zmm15;
|
||||
U512 zmm16;
|
||||
U512 zmm17;
|
||||
U512 zmm18;
|
||||
U512 zmm19;
|
||||
U512 zmm20;
|
||||
U512 zmm21;
|
||||
U512 zmm22;
|
||||
U512 zmm23;
|
||||
U512 zmm24;
|
||||
U512 zmm25;
|
||||
U512 zmm26;
|
||||
U512 zmm27;
|
||||
U512 zmm28;
|
||||
U512 zmm29;
|
||||
U512 zmm30;
|
||||
U512 zmm31;
|
||||
U64 k0;
|
||||
U64 k1;
|
||||
U64 k2;
|
||||
U64 k3;
|
||||
U64 k4;
|
||||
U64 k5;
|
||||
U64 k6;
|
||||
U64 k7;
|
||||
U64 cetmsr;
|
||||
U64 cetssp;
|
||||
};
|
||||
|
||||
C_LINKAGE_BEGIN
|
||||
extern B8 x64_reg_code_is_vector_table[189];
|
||||
extern String8 x64_reg_code_name_table[189];
|
||||
extern U8 x64_reg_code_base_table[189];
|
||||
extern Rng1U16 x64_reg_code_rng_table[189];
|
||||
|
||||
C_LINKAGE_END
|
||||
|
||||
#endif // X64_META_H
|
||||
+14
-1
@@ -1,6 +1,14 @@
|
||||
// Copyright (c) Epic Games Tools
|
||||
// Licensed under the MIT license (https://opensource.org/license/mit/)
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: Generated
|
||||
|
||||
#include "x64/generated/x64.meta.c"
|
||||
|
||||
////////////////////////////////
|
||||
//~ cpuid
|
||||
|
||||
internal void
|
||||
x64_cpuid(U32 leaf, U32 *eax, U32 *ebx, U32 *ecx, U32 *edx)
|
||||
{
|
||||
@@ -43,6 +51,9 @@ x64_cpuid_ex(U32 leaf, U32 sub_leaf, U32 *eax, U32 *ebx, U32 *ecx, U32 *edx)
|
||||
#endif
|
||||
}
|
||||
|
||||
////////////////////////////////
|
||||
//~ fxsave/xsave
|
||||
|
||||
internal B32
|
||||
x64_is_xsave_supported(void)
|
||||
{
|
||||
@@ -114,6 +125,9 @@ x64_get_xsave_layout(U64 xcr0)
|
||||
return xsave_layout;
|
||||
}
|
||||
|
||||
////////////////////////////////
|
||||
//~ Debug Control Register
|
||||
|
||||
internal void
|
||||
x64_set_debug_break(U64 *drs, U64 trap_idx, U64 addr, U64 size, X64_BreakpointType bp_type, X64_DebugBreakType break_type)
|
||||
{
|
||||
@@ -181,4 +195,3 @@ x64_set_debug_break(U64 *drs, U64 trap_idx, U64 addr, U64 size, X64_BreakpointTy
|
||||
default: { InvalidPath; }
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
+11
-7
@@ -177,30 +177,35 @@ typedef enum X64_DebugControlFlags
|
||||
X64_DebugControlFlag_L1 = (1 << 2),
|
||||
X64_DebugControlFlag_L2 = (1 << 4),
|
||||
X64_DebugControlFlag_L3 = (1 << 6),
|
||||
|
||||
|
||||
X64_DebugControlFlag_G0 = (1 << 1),
|
||||
X64_DebugControlFlag_G1 = (1 << 3),
|
||||
X64_DebugControlFlag_G3 = (1 << 5),
|
||||
X64_DebugControlFlag_G4 = (1 << 7),
|
||||
|
||||
|
||||
X64_DebugControlFlag_LE = (1 << 8),
|
||||
X64_DebugControlFlag_GE = (1 << 9),
|
||||
|
||||
|
||||
X64_DebugControlFlag_RTM = (1 << 11),
|
||||
|
||||
|
||||
X64_DebugControlFlag_GD = (1 << 13),
|
||||
|
||||
|
||||
X64_DebugControlFlag_RW0 = (3 << 16),
|
||||
X64_DebugControlFlag_RW1 = (3 << 20),
|
||||
X64_DebugControlFlag_RW2 = (3 << 24),
|
||||
X64_DebugControlFlag_FW3 = (3 << 26),
|
||||
|
||||
|
||||
X64_DebugControlFlag_LEN0 = (3 << 18),
|
||||
X64_DebugControlFlag_LEN1 = (3 << 22),
|
||||
X64_DebugControlFlag_LEN2 = (3 << 26),
|
||||
X64_DebugControlFlag_LEN3 = (3 << 30),
|
||||
} X64_DebugControlFlags;
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: Generated
|
||||
|
||||
#include "x64/generated/x64.meta.h"
|
||||
|
||||
////////////////////////////////
|
||||
//~ cpuid
|
||||
|
||||
@@ -222,4 +227,3 @@ internal X64_XSaveLayout x64_get_xsave_layout(U64 xcr0);
|
||||
internal void x64_set_debug_break(U64 *drs, U64 trap_idx, U64 addr, U64 size, X64_BreakpointType bp_type, X64_DebugBreakType break_type);
|
||||
|
||||
#endif // BASE_X64_H
|
||||
|
||||
|
||||
@@ -0,0 +1,231 @@
|
||||
// Copyright (c) Epic Games Tools
|
||||
// Licensed under the MIT license (https://opensource.org/license/mit/)
|
||||
|
||||
@table(name base off size is_vector has_rdi has_dwarf)
|
||||
X64_RegTable:
|
||||
{
|
||||
{nil - 0 0 - x - }
|
||||
{rax - 0 8 - x x }
|
||||
{rcx - 0 8 - x x }
|
||||
{rdx - 0 8 - x x }
|
||||
{rbx - 0 8 - x x }
|
||||
{rsp - 0 8 - x x }
|
||||
{rbp - 0 8 - x x }
|
||||
{rsi - 0 8 - x x }
|
||||
{rdi - 0 8 - x x }
|
||||
{r8 - 0 8 - x x }
|
||||
{r9 - 0 8 - x x }
|
||||
{r10 - 0 8 - x x }
|
||||
{r11 - 0 8 - x x }
|
||||
{r12 - 0 8 - x x }
|
||||
{r13 - 0 8 - x x }
|
||||
{r14 - 0 8 - x x }
|
||||
{r15 - 0 8 - x x }
|
||||
{fsbase - 0 8 - x x }
|
||||
{gsbase - 0 8 - x x }
|
||||
{rip - 0 8 - x x }
|
||||
{rflags - 0 8 - x x }
|
||||
{dr0 - 0 8 - x - }
|
||||
{dr1 - 0 8 - x - }
|
||||
{dr2 - 0 8 - x - }
|
||||
{dr3 - 0 8 - x - }
|
||||
{dr4 - 0 8 - x - }
|
||||
{dr5 - 0 8 - x - }
|
||||
{dr6 - 0 8 - x - }
|
||||
{dr7 - 0 8 - x - }
|
||||
{st0 - 0 10 - x x }
|
||||
{st1 - 0 10 - x x }
|
||||
{st2 - 0 10 - x x }
|
||||
{st3 - 0 10 - x x }
|
||||
{st4 - 0 10 - x x }
|
||||
{st5 - 0 10 - x x }
|
||||
{st6 - 0 10 - x x }
|
||||
{st7 - 0 10 - x x }
|
||||
{fcw - 0 2 - x - }
|
||||
{fsw - 0 2 - x - }
|
||||
{ftw - 0 1 - x - }
|
||||
{fop - 0 2 - x - }
|
||||
{fcs - 0 2 - x - }
|
||||
{fds - 0 2 - x - }
|
||||
{fip - 0 8 - x - }
|
||||
{fdp - 0 8 - x - }
|
||||
{mxcsr - 0 4 - x - }
|
||||
{mxcsr_mask - 0 4 - x - }
|
||||
{ss - 0 2 - x x }
|
||||
{cs - 0 2 - x x }
|
||||
{ds - 0 2 - x x }
|
||||
{es - 0 2 - x x }
|
||||
{fs - 0 2 - x x }
|
||||
{gs - 0 2 - x x }
|
||||
{zmm0 - 0 64 x x x }
|
||||
{zmm1 - 0 64 x x x }
|
||||
{zmm2 - 0 64 x x x }
|
||||
{zmm3 - 0 64 x x x }
|
||||
{zmm4 - 0 64 x x x }
|
||||
{zmm5 - 0 64 x x x }
|
||||
{zmm6 - 0 64 x x x }
|
||||
{zmm7 - 0 64 x x x }
|
||||
{zmm8 - 0 64 x x x }
|
||||
{zmm9 - 0 64 x x x }
|
||||
{zmm10 - 0 64 x x x }
|
||||
{zmm11 - 0 64 x x x }
|
||||
{zmm12 - 0 64 x x x }
|
||||
{zmm13 - 0 64 x x x }
|
||||
{zmm14 - 0 64 x x x }
|
||||
{zmm15 - 0 64 x x x }
|
||||
{zmm16 - 0 64 x x x }
|
||||
{zmm17 - 0 64 x x x }
|
||||
{zmm18 - 0 64 x x x }
|
||||
{zmm19 - 0 64 x x x }
|
||||
{zmm20 - 0 64 x x x }
|
||||
{zmm21 - 0 64 x x x }
|
||||
{zmm22 - 0 64 x x x }
|
||||
{zmm23 - 0 64 x x x }
|
||||
{zmm24 - 0 64 x x x }
|
||||
{zmm25 - 0 64 x x x }
|
||||
{zmm26 - 0 64 x x x }
|
||||
{zmm27 - 0 64 x x x }
|
||||
{zmm28 - 0 64 x x x }
|
||||
{zmm29 - 0 64 x x x }
|
||||
{zmm30 - 0 64 x x x }
|
||||
{zmm31 - 0 64 x x x }
|
||||
{k0 - 0 8 - x - }
|
||||
{k1 - 0 8 - x - }
|
||||
{k2 - 0 8 - x - }
|
||||
{k3 - 0 8 - x - }
|
||||
{k4 - 0 8 - x - }
|
||||
{k5 - 0 8 - x - }
|
||||
{k6 - 0 8 - x - }
|
||||
{k7 - 0 8 - x - }
|
||||
{cetmsr - 0 8 - x - }
|
||||
{cetssp - 0 8 - x - }
|
||||
//-
|
||||
//- aliases
|
||||
//-
|
||||
{eax rax 0 4 - - - }
|
||||
{ecx rcx 0 4 - - - }
|
||||
{edx rdx 0 4 - - - }
|
||||
{ebx rbx 0 4 - - - }
|
||||
{esp rsp 0 4 - - - }
|
||||
{ebp rbp 0 4 - - - }
|
||||
{esi rsi 0 4 - - - }
|
||||
{edi rdi 0 4 - - - }
|
||||
{r8d r8 0 4 - - - }
|
||||
{r9d r9 0 4 - - - }
|
||||
{r10d r10 0 4 - - - }
|
||||
{r11d r11 0 4 - - - }
|
||||
{r12d r12 0 4 - - - }
|
||||
{r13d r13 0 4 - - - }
|
||||
{r14d r14 0 4 - - - }
|
||||
{r15d r15 0 4 - - - }
|
||||
{eflags rflags 0 4 - - - }
|
||||
{ax rax 0 2 - - - }
|
||||
{cx rcx 0 2 - - - }
|
||||
{dx rdx 0 2 - - - }
|
||||
{bx rbx 0 2 - - - }
|
||||
{si rsi 0 2 - - - }
|
||||
{di rdi 0 2 - - - }
|
||||
{sp rsp 0 2 - - - }
|
||||
{bp rbp 0 2 - - - }
|
||||
{ip rip 0 2 - - - }
|
||||
{r8w r8 0 2 - - - }
|
||||
{r9w r9 0 2 - - - }
|
||||
{r10w r10 0 2 - - - }
|
||||
{r11w r11 0 2 - - - }
|
||||
{r12w r12 0 2 - - - }
|
||||
{r13w r13 0 2 - - - }
|
||||
{r14w r14 0 2 - - - }
|
||||
{r15w r15 0 2 - - - }
|
||||
{al rax 0 1 - - - }
|
||||
{cl rcx 0 1 - - - }
|
||||
{dl rdx 0 1 - - - }
|
||||
{bl rbx 0 1 - - - }
|
||||
{sil rsi 0 1 - - - }
|
||||
{dil rdi 0 1 - - - }
|
||||
{bpl rbp 0 1 - - - }
|
||||
{spl rsp 0 1 - - - }
|
||||
{r8b r8 0 1 - - - }
|
||||
{r9b r9 0 1 - - - }
|
||||
{r10b r10 0 1 - - - }
|
||||
{r11b r11 0 1 - - - }
|
||||
{r12b r12 0 1 - - - }
|
||||
{r13b r13 0 1 - - - }
|
||||
{r14b r14 0 1 - - - }
|
||||
{r15b r15 0 1 - - - }
|
||||
{ah rax 1 1 - - - }
|
||||
{ch rcx 1 1 - - - }
|
||||
{dh rdx 1 1 - - - }
|
||||
{bh rbx 1 1 - - - }
|
||||
{xmm0 zmm0 0 16 x - - }
|
||||
{xmm1 zmm1 0 16 x - - }
|
||||
{xmm2 zmm2 0 16 x - - }
|
||||
{xmm3 zmm3 0 16 x - - }
|
||||
{xmm4 zmm4 0 16 x - - }
|
||||
{xmm5 zmm5 0 16 x - - }
|
||||
{xmm6 zmm6 0 16 x - - }
|
||||
{xmm7 zmm7 0 16 x - - }
|
||||
{xmm8 zmm8 0 16 x - - }
|
||||
{xmm9 zmm9 0 16 x - - }
|
||||
{xmm10 zmm10 0 16 x - - }
|
||||
{xmm11 zmm11 0 16 x - - }
|
||||
{xmm12 zmm12 0 16 x - - }
|
||||
{xmm13 zmm13 0 16 x - - }
|
||||
{xmm14 zmm14 0 16 x - - }
|
||||
{xmm15 zmm15 0 16 x - - }
|
||||
{ymm0 zmm0 0 32 x - - }
|
||||
{ymm1 zmm1 0 32 x - - }
|
||||
{ymm2 zmm2 0 32 x - - }
|
||||
{ymm3 zmm3 0 32 x - - }
|
||||
{ymm4 zmm4 0 32 x - - }
|
||||
{ymm5 zmm5 0 32 x - - }
|
||||
{ymm6 zmm6 0 32 x - - }
|
||||
{ymm7 zmm7 0 32 x - - }
|
||||
{ymm8 zmm8 0 32 x - - }
|
||||
{ymm9 zmm9 0 32 x - - }
|
||||
{ymm10 zmm10 0 32 x - - }
|
||||
{ymm11 zmm11 0 32 x - - }
|
||||
{ymm12 zmm12 0 32 x - - }
|
||||
{ymm13 zmm13 0 32 x - - }
|
||||
{ymm14 zmm14 0 32 x - - }
|
||||
{ymm15 zmm15 0 32 x - - }
|
||||
{mm0 st0 0 8 x - x }
|
||||
{mm1 st1 0 8 x - x }
|
||||
{mm2 st2 0 8 x - x }
|
||||
{mm3 st3 0 8 x - x }
|
||||
{mm4 st4 0 8 x - x }
|
||||
{mm5 st5 0 8 x - x }
|
||||
{mm6 st6 0 8 x - x }
|
||||
{mm7 st7 0 8 x - x }
|
||||
}
|
||||
|
||||
@enum X64_RegCode:
|
||||
{
|
||||
@expand(X64_RegTable a) `$(a.name)`,
|
||||
COUNT,
|
||||
}
|
||||
|
||||
@struct X64_RegBlock:
|
||||
{
|
||||
@expand(X64_RegTable a) `$(a.name != 'nil' && a.base == '-' -> 'U' .. a.size*8 .. ' ' .. a.name)`,
|
||||
}
|
||||
|
||||
@data(B8) x64_reg_code_is_vector_table:
|
||||
{
|
||||
@expand(X64_RegTable a) `$(a.is_vector == 'x' -> '1')$(a.is_vector != 'x' -> '0')`;
|
||||
}
|
||||
|
||||
@data(String8) x64_reg_code_name_table:
|
||||
{
|
||||
@expand(X64_RegTable a) `str8_lit_comp("$(a.name)")`;
|
||||
}
|
||||
|
||||
@data(U8) x64_reg_code_base_table:
|
||||
{
|
||||
@expand(X64_RegTable a) `$(a.base != '-' -> "X64_RegCode_" .. a.base)$(a.base == '-' -> 0)`;
|
||||
}
|
||||
|
||||
@data(Rng1U16) x64_reg_code_rng_table:
|
||||
{
|
||||
`{0}`,
|
||||
@expand(X64_RegTable a) `$(a.name != 'nil' && a.base == '-'-> ("{(U16)OffsetOf(X64_RegBlock, " .. a.name .. "), (U16)OffsetOf(X64_RegBlock, " .. a.name .. ") + " .. a.size .. "}"))$(a.name != 'nil' && a.base != '-' -> ("{(U16)OffsetOf(X64_RegBlock, " .. a.base .. ") + " .. a.off .. ", (U16)OffsetOf(X64_RegBlock, " .. a.base .. ") + " .. a.off .. " + " .. a.size .. "}"))`,
|
||||
}
|
||||
Reference in New Issue
Block a user