mirror of
https://github.com/Ed94/raddebugger.git
synced 2026-07-21 13:55:43 +00:00
initial upload
This commit is contained in:
Ryan Fleury
@@ -0,0 +1,104 @@
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// Copyright (c) 2024 Epic Games Tools
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// Licensed under the MIT license (https://opensource.org/license/mit/)
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//- GENERATED CODE
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internal U64 regs_block_size_from_architecture(Architecture arch)
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{
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U64 result = 0;
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switch(arch)
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{
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default:{}break;
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case Architecture_x64:{result = sizeof(REGS_RegBlockX64);}break;
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case Architecture_x86:{result = sizeof(REGS_RegBlockX86);}break;
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}
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return result;
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}
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internal U64 regs_reg_code_count_from_architecture(Architecture arch)
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{
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U64 result = 0;
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switch(arch)
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{
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default:{}break;
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case Architecture_x64:{result = REGS_RegCodeX64_COUNT;}break;
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case Architecture_x86:{result = REGS_RegCodeX86_COUNT;}break;
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}
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return result;
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}
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internal U64 regs_alias_code_count_from_architecture(Architecture arch)
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{
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U64 result = 0;
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switch(arch)
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{
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default:{}break;
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case Architecture_x64:{result = REGS_AliasCodeX64_COUNT;}break;
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case Architecture_x86:{result = REGS_AliasCodeX86_COUNT;}break;
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}
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return result;
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}
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internal String8 *regs_reg_code_string_table_from_architecture(Architecture arch)
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{
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String8 *result = 0;
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switch(arch)
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{
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default:{}break;
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case Architecture_x64:{result = regs_g_reg_code_x64_string_table;}break;
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case Architecture_x86:{result = regs_g_reg_code_x86_string_table;}break;
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}
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return result;
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}
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internal String8 *regs_alias_code_string_table_from_architecture(Architecture arch)
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{
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String8 *result = 0;
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switch(arch)
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{
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default:{}break;
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case Architecture_x64:{result = regs_g_alias_code_x64_string_table;}break;
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case Architecture_x86:{result = regs_g_alias_code_x86_string_table;}break;
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}
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return result;
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}
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internal REGS_Rng *regs_reg_code_rng_table_from_architecture(Architecture arch)
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{
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REGS_Rng *result = 0;
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switch(arch)
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{
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default:{}break;
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case Architecture_x64:{result = regs_g_reg_code_x64_rng_table;}break;
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case Architecture_x86:{result = regs_g_reg_code_x86_rng_table;}break;
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}
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return result;
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}
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internal REGS_Slice *regs_alias_code_slice_table_from_architecture(Architecture arch)
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{
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REGS_Slice *result = 0;
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switch(arch)
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{
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default:{}break;
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case Architecture_x64:{result = regs_g_alias_code_x64_slice_table;}break;
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case Architecture_x86:{result = regs_g_alias_code_x86_slice_table;}break;
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}
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return result;
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}
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internal REGS_UsageKind *regs_reg_code_usage_kind_table_from_architecture(Architecture arch)
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{
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REGS_UsageKind *result = 0;
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switch(arch)
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{
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default:{}break;
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case Architecture_x64:{result = regs_g_reg_code_x64_usage_kind_table;}break;
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case Architecture_x86:{result = regs_g_reg_code_x86_usage_kind_table;}break;
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}
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return result;
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}
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internal REGS_UsageKind *regs_alias_code_usage_kind_table_from_architecture(Architecture arch)
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{
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REGS_UsageKind *result = 0;
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switch(arch)
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{
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default:{}break;
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case Architecture_x64:{result = regs_g_alias_code_x64_usage_kind_table;}break;
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case Architecture_x86:{result = regs_g_alias_code_x86_usage_kind_table;}break;
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}
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return result;
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}
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,322 @@
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// generated
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#ifndef _REGS_RADDBG_META_C
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#define _REGS_RADDBG_META_C
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internal RADDBG_RegisterCode regs_raddbg_code_from_arch_reg_code(Architecture arch, REGS_RegCode code)
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{
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RADDBG_RegisterCode result = 0;
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switch(arch)
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{
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case Architecture_x64:
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{
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switch(code)
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{
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default:{}break;
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case REGS_RegCodeX64_rax:{result = RADDBG_RegisterCode_X64_rax;}break;
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case REGS_RegCodeX64_rcx:{result = RADDBG_RegisterCode_X64_rcx;}break;
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case REGS_RegCodeX64_rdx:{result = RADDBG_RegisterCode_X64_rdx;}break;
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case REGS_RegCodeX64_rbx:{result = RADDBG_RegisterCode_X64_rbx;}break;
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case REGS_RegCodeX64_rsp:{result = RADDBG_RegisterCode_X64_rsp;}break;
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case REGS_RegCodeX64_rbp:{result = RADDBG_RegisterCode_X64_rbp;}break;
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case REGS_RegCodeX64_rsi:{result = RADDBG_RegisterCode_X64_rsi;}break;
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case REGS_RegCodeX64_rdi:{result = RADDBG_RegisterCode_X64_rdi;}break;
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case REGS_RegCodeX64_r8:{result = RADDBG_RegisterCode_X64_r8;}break;
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case REGS_RegCodeX64_r9:{result = RADDBG_RegisterCode_X64_r9;}break;
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case REGS_RegCodeX64_r10:{result = RADDBG_RegisterCode_X64_r10;}break;
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case REGS_RegCodeX64_r11:{result = RADDBG_RegisterCode_X64_r11;}break;
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case REGS_RegCodeX64_r12:{result = RADDBG_RegisterCode_X64_r12;}break;
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case REGS_RegCodeX64_r13:{result = RADDBG_RegisterCode_X64_r13;}break;
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case REGS_RegCodeX64_r14:{result = RADDBG_RegisterCode_X64_r14;}break;
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case REGS_RegCodeX64_r15:{result = RADDBG_RegisterCode_X64_r15;}break;
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case REGS_RegCodeX64_fsbase:{result = RADDBG_RegisterCode_X64_fsbase;}break;
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case REGS_RegCodeX64_gsbase:{result = RADDBG_RegisterCode_X64_gsbase;}break;
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case REGS_RegCodeX64_rip:{result = RADDBG_RegisterCode_X64_rip;}break;
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case REGS_RegCodeX64_rflags:{result = RADDBG_RegisterCode_X64_rflags;}break;
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case REGS_RegCodeX64_dr0:{result = RADDBG_RegisterCode_X64_dr0;}break;
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case REGS_RegCodeX64_dr1:{result = RADDBG_RegisterCode_X64_dr1;}break;
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case REGS_RegCodeX64_dr2:{result = RADDBG_RegisterCode_X64_dr2;}break;
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case REGS_RegCodeX64_dr3:{result = RADDBG_RegisterCode_X64_dr3;}break;
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case REGS_RegCodeX64_dr4:{result = RADDBG_RegisterCode_X64_dr4;}break;
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case REGS_RegCodeX64_dr5:{result = RADDBG_RegisterCode_X64_dr5;}break;
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case REGS_RegCodeX64_dr6:{result = RADDBG_RegisterCode_X64_dr6;}break;
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case REGS_RegCodeX64_dr7:{result = RADDBG_RegisterCode_X64_dr7;}break;
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case REGS_RegCodeX64_fpr0:{result = RADDBG_RegisterCode_X64_fpr0;}break;
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case REGS_RegCodeX64_fpr1:{result = RADDBG_RegisterCode_X64_fpr1;}break;
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case REGS_RegCodeX64_fpr2:{result = RADDBG_RegisterCode_X64_fpr2;}break;
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case REGS_RegCodeX64_fpr3:{result = RADDBG_RegisterCode_X64_fpr3;}break;
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case REGS_RegCodeX64_fpr4:{result = RADDBG_RegisterCode_X64_fpr4;}break;
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case REGS_RegCodeX64_fpr5:{result = RADDBG_RegisterCode_X64_fpr5;}break;
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case REGS_RegCodeX64_fpr6:{result = RADDBG_RegisterCode_X64_fpr6;}break;
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case REGS_RegCodeX64_fpr7:{result = RADDBG_RegisterCode_X64_fpr7;}break;
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case REGS_RegCodeX64_st0:{result = RADDBG_RegisterCode_X64_st0;}break;
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case REGS_RegCodeX64_st1:{result = RADDBG_RegisterCode_X64_st1;}break;
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case REGS_RegCodeX64_st2:{result = RADDBG_RegisterCode_X64_st2;}break;
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case REGS_RegCodeX64_st3:{result = RADDBG_RegisterCode_X64_st3;}break;
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case REGS_RegCodeX64_st4:{result = RADDBG_RegisterCode_X64_st4;}break;
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case REGS_RegCodeX64_st5:{result = RADDBG_RegisterCode_X64_st5;}break;
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case REGS_RegCodeX64_st6:{result = RADDBG_RegisterCode_X64_st6;}break;
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case REGS_RegCodeX64_st7:{result = RADDBG_RegisterCode_X64_st7;}break;
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case REGS_RegCodeX64_fcw:{result = RADDBG_RegisterCode_X64_fcw;}break;
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case REGS_RegCodeX64_fsw:{result = RADDBG_RegisterCode_X64_fsw;}break;
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case REGS_RegCodeX64_ftw:{result = RADDBG_RegisterCode_X64_ftw;}break;
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case REGS_RegCodeX64_fop:{result = RADDBG_RegisterCode_X64_fop;}break;
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case REGS_RegCodeX64_fcs:{result = RADDBG_RegisterCode_X64_fcs;}break;
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case REGS_RegCodeX64_fds:{result = RADDBG_RegisterCode_X64_fds;}break;
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case REGS_RegCodeX64_fip:{result = RADDBG_RegisterCode_X64_fip;}break;
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case REGS_RegCodeX64_fdp:{result = RADDBG_RegisterCode_X64_fdp;}break;
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case REGS_RegCodeX64_mxcsr:{result = RADDBG_RegisterCode_X64_mxcsr;}break;
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case REGS_RegCodeX64_mxcsr_mask:{result = RADDBG_RegisterCode_X64_mxcsr_mask;}break;
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case REGS_RegCodeX64_ss:{result = RADDBG_RegisterCode_X64_ss;}break;
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case REGS_RegCodeX64_cs:{result = RADDBG_RegisterCode_X64_cs;}break;
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case REGS_RegCodeX64_ds:{result = RADDBG_RegisterCode_X64_ds;}break;
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case REGS_RegCodeX64_es:{result = RADDBG_RegisterCode_X64_es;}break;
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case REGS_RegCodeX64_fs:{result = RADDBG_RegisterCode_X64_fs;}break;
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case REGS_RegCodeX64_gs:{result = RADDBG_RegisterCode_X64_gs;}break;
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case REGS_RegCodeX64_ymm0:{result = RADDBG_RegisterCode_X64_ymm0;}break;
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case REGS_RegCodeX64_ymm1:{result = RADDBG_RegisterCode_X64_ymm1;}break;
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case REGS_RegCodeX64_ymm2:{result = RADDBG_RegisterCode_X64_ymm2;}break;
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case REGS_RegCodeX64_ymm3:{result = RADDBG_RegisterCode_X64_ymm3;}break;
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case REGS_RegCodeX64_ymm4:{result = RADDBG_RegisterCode_X64_ymm4;}break;
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case REGS_RegCodeX64_ymm5:{result = RADDBG_RegisterCode_X64_ymm5;}break;
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case REGS_RegCodeX64_ymm6:{result = RADDBG_RegisterCode_X64_ymm6;}break;
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case REGS_RegCodeX64_ymm7:{result = RADDBG_RegisterCode_X64_ymm7;}break;
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case REGS_RegCodeX64_ymm8:{result = RADDBG_RegisterCode_X64_ymm8;}break;
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case REGS_RegCodeX64_ymm9:{result = RADDBG_RegisterCode_X64_ymm9;}break;
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case REGS_RegCodeX64_ymm10:{result = RADDBG_RegisterCode_X64_ymm10;}break;
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case REGS_RegCodeX64_ymm11:{result = RADDBG_RegisterCode_X64_ymm11;}break;
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case REGS_RegCodeX64_ymm12:{result = RADDBG_RegisterCode_X64_ymm12;}break;
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case REGS_RegCodeX64_ymm13:{result = RADDBG_RegisterCode_X64_ymm13;}break;
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case REGS_RegCodeX64_ymm14:{result = RADDBG_RegisterCode_X64_ymm14;}break;
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case REGS_RegCodeX64_ymm15:{result = RADDBG_RegisterCode_X64_ymm15;}break;
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}
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}break;
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case Architecture_x86:
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{
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switch(code)
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{
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default:{}break;
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case REGS_RegCodeX86_eax:{result = RADDBG_RegisterCode_X86_eax;}break;
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case REGS_RegCodeX86_ecx:{result = RADDBG_RegisterCode_X86_ecx;}break;
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case REGS_RegCodeX86_edx:{result = RADDBG_RegisterCode_X86_edx;}break;
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case REGS_RegCodeX86_ebx:{result = RADDBG_RegisterCode_X86_ebx;}break;
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case REGS_RegCodeX86_esp:{result = RADDBG_RegisterCode_X86_esp;}break;
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case REGS_RegCodeX86_ebp:{result = RADDBG_RegisterCode_X86_ebp;}break;
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case REGS_RegCodeX86_esi:{result = RADDBG_RegisterCode_X86_esi;}break;
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case REGS_RegCodeX86_edi:{result = RADDBG_RegisterCode_X86_edi;}break;
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case REGS_RegCodeX86_fsbase:{result = RADDBG_RegisterCode_X86_fsbase;}break;
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case REGS_RegCodeX86_gsbase:{result = RADDBG_RegisterCode_X86_gsbase;}break;
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case REGS_RegCodeX86_eflags:{result = RADDBG_RegisterCode_X86_eflags;}break;
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case REGS_RegCodeX86_eip:{result = RADDBG_RegisterCode_X86_eip;}break;
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case REGS_RegCodeX86_dr0:{result = RADDBG_RegisterCode_X86_dr0;}break;
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case REGS_RegCodeX86_dr1:{result = RADDBG_RegisterCode_X86_dr1;}break;
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case REGS_RegCodeX86_dr2:{result = RADDBG_RegisterCode_X86_dr2;}break;
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case REGS_RegCodeX86_dr3:{result = RADDBG_RegisterCode_X86_dr3;}break;
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case REGS_RegCodeX86_dr4:{result = RADDBG_RegisterCode_X86_dr4;}break;
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case REGS_RegCodeX86_dr5:{result = RADDBG_RegisterCode_X86_dr5;}break;
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case REGS_RegCodeX86_dr6:{result = RADDBG_RegisterCode_X86_dr6;}break;
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case REGS_RegCodeX86_dr7:{result = RADDBG_RegisterCode_X86_dr7;}break;
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case REGS_RegCodeX86_fpr0:{result = RADDBG_RegisterCode_X86_fpr0;}break;
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case REGS_RegCodeX86_fpr1:{result = RADDBG_RegisterCode_X86_fpr1;}break;
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case REGS_RegCodeX86_fpr2:{result = RADDBG_RegisterCode_X86_fpr2;}break;
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case REGS_RegCodeX86_fpr3:{result = RADDBG_RegisterCode_X86_fpr3;}break;
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case REGS_RegCodeX86_fpr4:{result = RADDBG_RegisterCode_X86_fpr4;}break;
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case REGS_RegCodeX86_fpr5:{result = RADDBG_RegisterCode_X86_fpr5;}break;
|
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case REGS_RegCodeX86_fpr6:{result = RADDBG_RegisterCode_X86_fpr6;}break;
|
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case REGS_RegCodeX86_fpr7:{result = RADDBG_RegisterCode_X86_fpr7;}break;
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case REGS_RegCodeX86_st0:{result = RADDBG_RegisterCode_X86_st0;}break;
|
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case REGS_RegCodeX86_st1:{result = RADDBG_RegisterCode_X86_st1;}break;
|
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case REGS_RegCodeX86_st2:{result = RADDBG_RegisterCode_X86_st2;}break;
|
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case REGS_RegCodeX86_st3:{result = RADDBG_RegisterCode_X86_st3;}break;
|
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case REGS_RegCodeX86_st4:{result = RADDBG_RegisterCode_X86_st4;}break;
|
||||
case REGS_RegCodeX86_st5:{result = RADDBG_RegisterCode_X86_st5;}break;
|
||||
case REGS_RegCodeX86_st6:{result = RADDBG_RegisterCode_X86_st6;}break;
|
||||
case REGS_RegCodeX86_st7:{result = RADDBG_RegisterCode_X86_st7;}break;
|
||||
case REGS_RegCodeX86_fcw:{result = RADDBG_RegisterCode_X86_fcw;}break;
|
||||
case REGS_RegCodeX86_fsw:{result = RADDBG_RegisterCode_X86_fsw;}break;
|
||||
case REGS_RegCodeX86_ftw:{result = RADDBG_RegisterCode_X86_ftw;}break;
|
||||
case REGS_RegCodeX86_fop:{result = RADDBG_RegisterCode_X86_fop;}break;
|
||||
case REGS_RegCodeX86_fcs:{result = RADDBG_RegisterCode_X86_fcs;}break;
|
||||
case REGS_RegCodeX86_fds:{result = RADDBG_RegisterCode_X86_fds;}break;
|
||||
case REGS_RegCodeX86_fip:{result = RADDBG_RegisterCode_X86_fip;}break;
|
||||
case REGS_RegCodeX86_fdp:{result = RADDBG_RegisterCode_X86_fdp;}break;
|
||||
case REGS_RegCodeX86_mxcsr:{result = RADDBG_RegisterCode_X86_mxcsr;}break;
|
||||
case REGS_RegCodeX86_mxcsr_mask:{result = RADDBG_RegisterCode_X86_mxcsr_mask;}break;
|
||||
case REGS_RegCodeX86_ss:{result = RADDBG_RegisterCode_X86_ss;}break;
|
||||
case REGS_RegCodeX86_cs:{result = RADDBG_RegisterCode_X86_cs;}break;
|
||||
case REGS_RegCodeX86_ds:{result = RADDBG_RegisterCode_X86_ds;}break;
|
||||
case REGS_RegCodeX86_es:{result = RADDBG_RegisterCode_X86_es;}break;
|
||||
case REGS_RegCodeX86_fs:{result = RADDBG_RegisterCode_X86_fs;}break;
|
||||
case REGS_RegCodeX86_gs:{result = RADDBG_RegisterCode_X86_gs;}break;
|
||||
case REGS_RegCodeX86_ymm0:{result = RADDBG_RegisterCode_X86_ymm0;}break;
|
||||
case REGS_RegCodeX86_ymm1:{result = RADDBG_RegisterCode_X86_ymm1;}break;
|
||||
case REGS_RegCodeX86_ymm2:{result = RADDBG_RegisterCode_X86_ymm2;}break;
|
||||
case REGS_RegCodeX86_ymm3:{result = RADDBG_RegisterCode_X86_ymm3;}break;
|
||||
case REGS_RegCodeX86_ymm4:{result = RADDBG_RegisterCode_X86_ymm4;}break;
|
||||
case REGS_RegCodeX86_ymm5:{result = RADDBG_RegisterCode_X86_ymm5;}break;
|
||||
case REGS_RegCodeX86_ymm6:{result = RADDBG_RegisterCode_X86_ymm6;}break;
|
||||
case REGS_RegCodeX86_ymm7:{result = RADDBG_RegisterCode_X86_ymm7;}break;
|
||||
}
|
||||
}break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
internal REGS_RegCode regs_reg_code_from_arch_raddbg_code(Architecture arch, RADDBG_RegisterCode code)
|
||||
{
|
||||
REGS_RegCode result = 0;
|
||||
switch(arch)
|
||||
{
|
||||
case Architecture_x64:
|
||||
{
|
||||
switch(code)
|
||||
{
|
||||
default:{}break;
|
||||
case RADDBG_RegisterCode_X64_rax:{result = REGS_RegCodeX64_rax;}break;
|
||||
case RADDBG_RegisterCode_X64_rcx:{result = REGS_RegCodeX64_rcx;}break;
|
||||
case RADDBG_RegisterCode_X64_rdx:{result = REGS_RegCodeX64_rdx;}break;
|
||||
case RADDBG_RegisterCode_X64_rbx:{result = REGS_RegCodeX64_rbx;}break;
|
||||
case RADDBG_RegisterCode_X64_rsp:{result = REGS_RegCodeX64_rsp;}break;
|
||||
case RADDBG_RegisterCode_X64_rbp:{result = REGS_RegCodeX64_rbp;}break;
|
||||
case RADDBG_RegisterCode_X64_rsi:{result = REGS_RegCodeX64_rsi;}break;
|
||||
case RADDBG_RegisterCode_X64_rdi:{result = REGS_RegCodeX64_rdi;}break;
|
||||
case RADDBG_RegisterCode_X64_r8:{result = REGS_RegCodeX64_r8;}break;
|
||||
case RADDBG_RegisterCode_X64_r9:{result = REGS_RegCodeX64_r9;}break;
|
||||
case RADDBG_RegisterCode_X64_r10:{result = REGS_RegCodeX64_r10;}break;
|
||||
case RADDBG_RegisterCode_X64_r11:{result = REGS_RegCodeX64_r11;}break;
|
||||
case RADDBG_RegisterCode_X64_r12:{result = REGS_RegCodeX64_r12;}break;
|
||||
case RADDBG_RegisterCode_X64_r13:{result = REGS_RegCodeX64_r13;}break;
|
||||
case RADDBG_RegisterCode_X64_r14:{result = REGS_RegCodeX64_r14;}break;
|
||||
case RADDBG_RegisterCode_X64_r15:{result = REGS_RegCodeX64_r15;}break;
|
||||
case RADDBG_RegisterCode_X64_fsbase:{result = REGS_RegCodeX64_fsbase;}break;
|
||||
case RADDBG_RegisterCode_X64_gsbase:{result = REGS_RegCodeX64_gsbase;}break;
|
||||
case RADDBG_RegisterCode_X64_rip:{result = REGS_RegCodeX64_rip;}break;
|
||||
case RADDBG_RegisterCode_X64_rflags:{result = REGS_RegCodeX64_rflags;}break;
|
||||
case RADDBG_RegisterCode_X64_dr0:{result = REGS_RegCodeX64_dr0;}break;
|
||||
case RADDBG_RegisterCode_X64_dr1:{result = REGS_RegCodeX64_dr1;}break;
|
||||
case RADDBG_RegisterCode_X64_dr2:{result = REGS_RegCodeX64_dr2;}break;
|
||||
case RADDBG_RegisterCode_X64_dr3:{result = REGS_RegCodeX64_dr3;}break;
|
||||
case RADDBG_RegisterCode_X64_dr4:{result = REGS_RegCodeX64_dr4;}break;
|
||||
case RADDBG_RegisterCode_X64_dr5:{result = REGS_RegCodeX64_dr5;}break;
|
||||
case RADDBG_RegisterCode_X64_dr6:{result = REGS_RegCodeX64_dr6;}break;
|
||||
case RADDBG_RegisterCode_X64_dr7:{result = REGS_RegCodeX64_dr7;}break;
|
||||
case RADDBG_RegisterCode_X64_fpr0:{result = REGS_RegCodeX64_fpr0;}break;
|
||||
case RADDBG_RegisterCode_X64_fpr1:{result = REGS_RegCodeX64_fpr1;}break;
|
||||
case RADDBG_RegisterCode_X64_fpr2:{result = REGS_RegCodeX64_fpr2;}break;
|
||||
case RADDBG_RegisterCode_X64_fpr3:{result = REGS_RegCodeX64_fpr3;}break;
|
||||
case RADDBG_RegisterCode_X64_fpr4:{result = REGS_RegCodeX64_fpr4;}break;
|
||||
case RADDBG_RegisterCode_X64_fpr5:{result = REGS_RegCodeX64_fpr5;}break;
|
||||
case RADDBG_RegisterCode_X64_fpr6:{result = REGS_RegCodeX64_fpr6;}break;
|
||||
case RADDBG_RegisterCode_X64_fpr7:{result = REGS_RegCodeX64_fpr7;}break;
|
||||
case RADDBG_RegisterCode_X64_st0:{result = REGS_RegCodeX64_st0;}break;
|
||||
case RADDBG_RegisterCode_X64_st1:{result = REGS_RegCodeX64_st1;}break;
|
||||
case RADDBG_RegisterCode_X64_st2:{result = REGS_RegCodeX64_st2;}break;
|
||||
case RADDBG_RegisterCode_X64_st3:{result = REGS_RegCodeX64_st3;}break;
|
||||
case RADDBG_RegisterCode_X64_st4:{result = REGS_RegCodeX64_st4;}break;
|
||||
case RADDBG_RegisterCode_X64_st5:{result = REGS_RegCodeX64_st5;}break;
|
||||
case RADDBG_RegisterCode_X64_st6:{result = REGS_RegCodeX64_st6;}break;
|
||||
case RADDBG_RegisterCode_X64_st7:{result = REGS_RegCodeX64_st7;}break;
|
||||
case RADDBG_RegisterCode_X64_fcw:{result = REGS_RegCodeX64_fcw;}break;
|
||||
case RADDBG_RegisterCode_X64_fsw:{result = REGS_RegCodeX64_fsw;}break;
|
||||
case RADDBG_RegisterCode_X64_ftw:{result = REGS_RegCodeX64_ftw;}break;
|
||||
case RADDBG_RegisterCode_X64_fop:{result = REGS_RegCodeX64_fop;}break;
|
||||
case RADDBG_RegisterCode_X64_fcs:{result = REGS_RegCodeX64_fcs;}break;
|
||||
case RADDBG_RegisterCode_X64_fds:{result = REGS_RegCodeX64_fds;}break;
|
||||
case RADDBG_RegisterCode_X64_fip:{result = REGS_RegCodeX64_fip;}break;
|
||||
case RADDBG_RegisterCode_X64_fdp:{result = REGS_RegCodeX64_fdp;}break;
|
||||
case RADDBG_RegisterCode_X64_mxcsr:{result = REGS_RegCodeX64_mxcsr;}break;
|
||||
case RADDBG_RegisterCode_X64_mxcsr_mask:{result = REGS_RegCodeX64_mxcsr_mask;}break;
|
||||
case RADDBG_RegisterCode_X64_ss:{result = REGS_RegCodeX64_ss;}break;
|
||||
case RADDBG_RegisterCode_X64_cs:{result = REGS_RegCodeX64_cs;}break;
|
||||
case RADDBG_RegisterCode_X64_ds:{result = REGS_RegCodeX64_ds;}break;
|
||||
case RADDBG_RegisterCode_X64_es:{result = REGS_RegCodeX64_es;}break;
|
||||
case RADDBG_RegisterCode_X64_fs:{result = REGS_RegCodeX64_fs;}break;
|
||||
case RADDBG_RegisterCode_X64_gs:{result = REGS_RegCodeX64_gs;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm0:{result = REGS_RegCodeX64_ymm0;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm1:{result = REGS_RegCodeX64_ymm1;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm2:{result = REGS_RegCodeX64_ymm2;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm3:{result = REGS_RegCodeX64_ymm3;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm4:{result = REGS_RegCodeX64_ymm4;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm5:{result = REGS_RegCodeX64_ymm5;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm6:{result = REGS_RegCodeX64_ymm6;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm7:{result = REGS_RegCodeX64_ymm7;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm8:{result = REGS_RegCodeX64_ymm8;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm9:{result = REGS_RegCodeX64_ymm9;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm10:{result = REGS_RegCodeX64_ymm10;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm11:{result = REGS_RegCodeX64_ymm11;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm12:{result = REGS_RegCodeX64_ymm12;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm13:{result = REGS_RegCodeX64_ymm13;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm14:{result = REGS_RegCodeX64_ymm14;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm15:{result = REGS_RegCodeX64_ymm15;}break;
|
||||
}
|
||||
}break;
|
||||
case Architecture_x86:
|
||||
{
|
||||
switch(code)
|
||||
{
|
||||
default:{}break;
|
||||
case RADDBG_RegisterCode_X86_eax:{result = REGS_RegCodeX86_eax;}break;
|
||||
case RADDBG_RegisterCode_X86_ecx:{result = REGS_RegCodeX86_ecx;}break;
|
||||
case RADDBG_RegisterCode_X86_edx:{result = REGS_RegCodeX86_edx;}break;
|
||||
case RADDBG_RegisterCode_X86_ebx:{result = REGS_RegCodeX86_ebx;}break;
|
||||
case RADDBG_RegisterCode_X86_esp:{result = REGS_RegCodeX86_esp;}break;
|
||||
case RADDBG_RegisterCode_X86_ebp:{result = REGS_RegCodeX86_ebp;}break;
|
||||
case RADDBG_RegisterCode_X86_esi:{result = REGS_RegCodeX86_esi;}break;
|
||||
case RADDBG_RegisterCode_X86_edi:{result = REGS_RegCodeX86_edi;}break;
|
||||
case RADDBG_RegisterCode_X86_fsbase:{result = REGS_RegCodeX86_fsbase;}break;
|
||||
case RADDBG_RegisterCode_X86_gsbase:{result = REGS_RegCodeX86_gsbase;}break;
|
||||
case RADDBG_RegisterCode_X86_eflags:{result = REGS_RegCodeX86_eflags;}break;
|
||||
case RADDBG_RegisterCode_X86_eip:{result = REGS_RegCodeX86_eip;}break;
|
||||
case RADDBG_RegisterCode_X86_dr0:{result = REGS_RegCodeX86_dr0;}break;
|
||||
case RADDBG_RegisterCode_X86_dr1:{result = REGS_RegCodeX86_dr1;}break;
|
||||
case RADDBG_RegisterCode_X86_dr2:{result = REGS_RegCodeX86_dr2;}break;
|
||||
case RADDBG_RegisterCode_X86_dr3:{result = REGS_RegCodeX86_dr3;}break;
|
||||
case RADDBG_RegisterCode_X86_dr4:{result = REGS_RegCodeX86_dr4;}break;
|
||||
case RADDBG_RegisterCode_X86_dr5:{result = REGS_RegCodeX86_dr5;}break;
|
||||
case RADDBG_RegisterCode_X86_dr6:{result = REGS_RegCodeX86_dr6;}break;
|
||||
case RADDBG_RegisterCode_X86_dr7:{result = REGS_RegCodeX86_dr7;}break;
|
||||
case RADDBG_RegisterCode_X86_fpr0:{result = REGS_RegCodeX86_fpr0;}break;
|
||||
case RADDBG_RegisterCode_X86_fpr1:{result = REGS_RegCodeX86_fpr1;}break;
|
||||
case RADDBG_RegisterCode_X86_fpr2:{result = REGS_RegCodeX86_fpr2;}break;
|
||||
case RADDBG_RegisterCode_X86_fpr3:{result = REGS_RegCodeX86_fpr3;}break;
|
||||
case RADDBG_RegisterCode_X86_fpr4:{result = REGS_RegCodeX86_fpr4;}break;
|
||||
case RADDBG_RegisterCode_X86_fpr5:{result = REGS_RegCodeX86_fpr5;}break;
|
||||
case RADDBG_RegisterCode_X86_fpr6:{result = REGS_RegCodeX86_fpr6;}break;
|
||||
case RADDBG_RegisterCode_X86_fpr7:{result = REGS_RegCodeX86_fpr7;}break;
|
||||
case RADDBG_RegisterCode_X86_st0:{result = REGS_RegCodeX86_st0;}break;
|
||||
case RADDBG_RegisterCode_X86_st1:{result = REGS_RegCodeX86_st1;}break;
|
||||
case RADDBG_RegisterCode_X86_st2:{result = REGS_RegCodeX86_st2;}break;
|
||||
case RADDBG_RegisterCode_X86_st3:{result = REGS_RegCodeX86_st3;}break;
|
||||
case RADDBG_RegisterCode_X86_st4:{result = REGS_RegCodeX86_st4;}break;
|
||||
case RADDBG_RegisterCode_X86_st5:{result = REGS_RegCodeX86_st5;}break;
|
||||
case RADDBG_RegisterCode_X86_st6:{result = REGS_RegCodeX86_st6;}break;
|
||||
case RADDBG_RegisterCode_X86_st7:{result = REGS_RegCodeX86_st7;}break;
|
||||
case RADDBG_RegisterCode_X86_fcw:{result = REGS_RegCodeX86_fcw;}break;
|
||||
case RADDBG_RegisterCode_X86_fsw:{result = REGS_RegCodeX86_fsw;}break;
|
||||
case RADDBG_RegisterCode_X86_ftw:{result = REGS_RegCodeX86_ftw;}break;
|
||||
case RADDBG_RegisterCode_X86_fop:{result = REGS_RegCodeX86_fop;}break;
|
||||
case RADDBG_RegisterCode_X86_fcs:{result = REGS_RegCodeX86_fcs;}break;
|
||||
case RADDBG_RegisterCode_X86_fds:{result = REGS_RegCodeX86_fds;}break;
|
||||
case RADDBG_RegisterCode_X86_fip:{result = REGS_RegCodeX86_fip;}break;
|
||||
case RADDBG_RegisterCode_X86_fdp:{result = REGS_RegCodeX86_fdp;}break;
|
||||
case RADDBG_RegisterCode_X86_mxcsr:{result = REGS_RegCodeX86_mxcsr;}break;
|
||||
case RADDBG_RegisterCode_X86_mxcsr_mask:{result = REGS_RegCodeX86_mxcsr_mask;}break;
|
||||
case RADDBG_RegisterCode_X86_ss:{result = REGS_RegCodeX86_ss;}break;
|
||||
case RADDBG_RegisterCode_X86_cs:{result = REGS_RegCodeX86_cs;}break;
|
||||
case RADDBG_RegisterCode_X86_ds:{result = REGS_RegCodeX86_ds;}break;
|
||||
case RADDBG_RegisterCode_X86_es:{result = REGS_RegCodeX86_es;}break;
|
||||
case RADDBG_RegisterCode_X86_fs:{result = REGS_RegCodeX86_fs;}break;
|
||||
case RADDBG_RegisterCode_X86_gs:{result = REGS_RegCodeX86_gs;}break;
|
||||
case RADDBG_RegisterCode_X86_ymm0:{result = REGS_RegCodeX86_ymm0;}break;
|
||||
case RADDBG_RegisterCode_X86_ymm1:{result = REGS_RegCodeX86_ymm1;}break;
|
||||
case RADDBG_RegisterCode_X86_ymm2:{result = REGS_RegCodeX86_ymm2;}break;
|
||||
case RADDBG_RegisterCode_X86_ymm3:{result = REGS_RegCodeX86_ymm3;}break;
|
||||
case RADDBG_RegisterCode_X86_ymm4:{result = REGS_RegCodeX86_ymm4;}break;
|
||||
case RADDBG_RegisterCode_X86_ymm5:{result = REGS_RegCodeX86_ymm5;}break;
|
||||
case RADDBG_RegisterCode_X86_ymm6:{result = REGS_RegCodeX86_ymm6;}break;
|
||||
case RADDBG_RegisterCode_X86_ymm7:{result = REGS_RegCodeX86_ymm7;}break;
|
||||
}
|
||||
}break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,323 @@
|
||||
// Copyright (c) 2024 Epic Games Tools
|
||||
// Licensed under the MIT license (https://opensource.org/license/mit/)
|
||||
|
||||
//- GENERATED CODE
|
||||
|
||||
internal RADDBG_RegisterCode regs_raddbg_code_from_arch_reg_code(Architecture arch, REGS_RegCode code)
|
||||
{
|
||||
RADDBG_RegisterCode result = 0;
|
||||
switch(arch)
|
||||
{
|
||||
default:{}break;
|
||||
case Architecture_x64:
|
||||
{
|
||||
switch(code)
|
||||
{
|
||||
default:{}break;
|
||||
case REGS_RegCodeX64_rax:{result = RADDBG_RegisterCode_X64_rax;}break;
|
||||
case REGS_RegCodeX64_rcx:{result = RADDBG_RegisterCode_X64_rcx;}break;
|
||||
case REGS_RegCodeX64_rdx:{result = RADDBG_RegisterCode_X64_rdx;}break;
|
||||
case REGS_RegCodeX64_rbx:{result = RADDBG_RegisterCode_X64_rbx;}break;
|
||||
case REGS_RegCodeX64_rsp:{result = RADDBG_RegisterCode_X64_rsp;}break;
|
||||
case REGS_RegCodeX64_rbp:{result = RADDBG_RegisterCode_X64_rbp;}break;
|
||||
case REGS_RegCodeX64_rsi:{result = RADDBG_RegisterCode_X64_rsi;}break;
|
||||
case REGS_RegCodeX64_rdi:{result = RADDBG_RegisterCode_X64_rdi;}break;
|
||||
case REGS_RegCodeX64_r8:{result = RADDBG_RegisterCode_X64_r8;}break;
|
||||
case REGS_RegCodeX64_r9:{result = RADDBG_RegisterCode_X64_r9;}break;
|
||||
case REGS_RegCodeX64_r10:{result = RADDBG_RegisterCode_X64_r10;}break;
|
||||
case REGS_RegCodeX64_r11:{result = RADDBG_RegisterCode_X64_r11;}break;
|
||||
case REGS_RegCodeX64_r12:{result = RADDBG_RegisterCode_X64_r12;}break;
|
||||
case REGS_RegCodeX64_r13:{result = RADDBG_RegisterCode_X64_r13;}break;
|
||||
case REGS_RegCodeX64_r14:{result = RADDBG_RegisterCode_X64_r14;}break;
|
||||
case REGS_RegCodeX64_r15:{result = RADDBG_RegisterCode_X64_r15;}break;
|
||||
case REGS_RegCodeX64_fsbase:{result = RADDBG_RegisterCode_X64_fsbase;}break;
|
||||
case REGS_RegCodeX64_gsbase:{result = RADDBG_RegisterCode_X64_gsbase;}break;
|
||||
case REGS_RegCodeX64_rip:{result = RADDBG_RegisterCode_X64_rip;}break;
|
||||
case REGS_RegCodeX64_rflags:{result = RADDBG_RegisterCode_X64_rflags;}break;
|
||||
case REGS_RegCodeX64_dr0:{result = RADDBG_RegisterCode_X64_dr0;}break;
|
||||
case REGS_RegCodeX64_dr1:{result = RADDBG_RegisterCode_X64_dr1;}break;
|
||||
case REGS_RegCodeX64_dr2:{result = RADDBG_RegisterCode_X64_dr2;}break;
|
||||
case REGS_RegCodeX64_dr3:{result = RADDBG_RegisterCode_X64_dr3;}break;
|
||||
case REGS_RegCodeX64_dr4:{result = RADDBG_RegisterCode_X64_dr4;}break;
|
||||
case REGS_RegCodeX64_dr5:{result = RADDBG_RegisterCode_X64_dr5;}break;
|
||||
case REGS_RegCodeX64_dr6:{result = RADDBG_RegisterCode_X64_dr6;}break;
|
||||
case REGS_RegCodeX64_dr7:{result = RADDBG_RegisterCode_X64_dr7;}break;
|
||||
case REGS_RegCodeX64_fpr0:{result = RADDBG_RegisterCode_X64_fpr0;}break;
|
||||
case REGS_RegCodeX64_fpr1:{result = RADDBG_RegisterCode_X64_fpr1;}break;
|
||||
case REGS_RegCodeX64_fpr2:{result = RADDBG_RegisterCode_X64_fpr2;}break;
|
||||
case REGS_RegCodeX64_fpr3:{result = RADDBG_RegisterCode_X64_fpr3;}break;
|
||||
case REGS_RegCodeX64_fpr4:{result = RADDBG_RegisterCode_X64_fpr4;}break;
|
||||
case REGS_RegCodeX64_fpr5:{result = RADDBG_RegisterCode_X64_fpr5;}break;
|
||||
case REGS_RegCodeX64_fpr6:{result = RADDBG_RegisterCode_X64_fpr6;}break;
|
||||
case REGS_RegCodeX64_fpr7:{result = RADDBG_RegisterCode_X64_fpr7;}break;
|
||||
case REGS_RegCodeX64_st0:{result = RADDBG_RegisterCode_X64_st0;}break;
|
||||
case REGS_RegCodeX64_st1:{result = RADDBG_RegisterCode_X64_st1;}break;
|
||||
case REGS_RegCodeX64_st2:{result = RADDBG_RegisterCode_X64_st2;}break;
|
||||
case REGS_RegCodeX64_st3:{result = RADDBG_RegisterCode_X64_st3;}break;
|
||||
case REGS_RegCodeX64_st4:{result = RADDBG_RegisterCode_X64_st4;}break;
|
||||
case REGS_RegCodeX64_st5:{result = RADDBG_RegisterCode_X64_st5;}break;
|
||||
case REGS_RegCodeX64_st6:{result = RADDBG_RegisterCode_X64_st6;}break;
|
||||
case REGS_RegCodeX64_st7:{result = RADDBG_RegisterCode_X64_st7;}break;
|
||||
case REGS_RegCodeX64_fcw:{result = RADDBG_RegisterCode_X64_fcw;}break;
|
||||
case REGS_RegCodeX64_fsw:{result = RADDBG_RegisterCode_X64_fsw;}break;
|
||||
case REGS_RegCodeX64_ftw:{result = RADDBG_RegisterCode_X64_ftw;}break;
|
||||
case REGS_RegCodeX64_fop:{result = RADDBG_RegisterCode_X64_fop;}break;
|
||||
case REGS_RegCodeX64_fcs:{result = RADDBG_RegisterCode_X64_fcs;}break;
|
||||
case REGS_RegCodeX64_fds:{result = RADDBG_RegisterCode_X64_fds;}break;
|
||||
case REGS_RegCodeX64_fip:{result = RADDBG_RegisterCode_X64_fip;}break;
|
||||
case REGS_RegCodeX64_fdp:{result = RADDBG_RegisterCode_X64_fdp;}break;
|
||||
case REGS_RegCodeX64_mxcsr:{result = RADDBG_RegisterCode_X64_mxcsr;}break;
|
||||
case REGS_RegCodeX64_mxcsr_mask:{result = RADDBG_RegisterCode_X64_mxcsr_mask;}break;
|
||||
case REGS_RegCodeX64_ss:{result = RADDBG_RegisterCode_X64_ss;}break;
|
||||
case REGS_RegCodeX64_cs:{result = RADDBG_RegisterCode_X64_cs;}break;
|
||||
case REGS_RegCodeX64_ds:{result = RADDBG_RegisterCode_X64_ds;}break;
|
||||
case REGS_RegCodeX64_es:{result = RADDBG_RegisterCode_X64_es;}break;
|
||||
case REGS_RegCodeX64_fs:{result = RADDBG_RegisterCode_X64_fs;}break;
|
||||
case REGS_RegCodeX64_gs:{result = RADDBG_RegisterCode_X64_gs;}break;
|
||||
case REGS_RegCodeX64_ymm0:{result = RADDBG_RegisterCode_X64_ymm0;}break;
|
||||
case REGS_RegCodeX64_ymm1:{result = RADDBG_RegisterCode_X64_ymm1;}break;
|
||||
case REGS_RegCodeX64_ymm2:{result = RADDBG_RegisterCode_X64_ymm2;}break;
|
||||
case REGS_RegCodeX64_ymm3:{result = RADDBG_RegisterCode_X64_ymm3;}break;
|
||||
case REGS_RegCodeX64_ymm4:{result = RADDBG_RegisterCode_X64_ymm4;}break;
|
||||
case REGS_RegCodeX64_ymm5:{result = RADDBG_RegisterCode_X64_ymm5;}break;
|
||||
case REGS_RegCodeX64_ymm6:{result = RADDBG_RegisterCode_X64_ymm6;}break;
|
||||
case REGS_RegCodeX64_ymm7:{result = RADDBG_RegisterCode_X64_ymm7;}break;
|
||||
case REGS_RegCodeX64_ymm8:{result = RADDBG_RegisterCode_X64_ymm8;}break;
|
||||
case REGS_RegCodeX64_ymm9:{result = RADDBG_RegisterCode_X64_ymm9;}break;
|
||||
case REGS_RegCodeX64_ymm10:{result = RADDBG_RegisterCode_X64_ymm10;}break;
|
||||
case REGS_RegCodeX64_ymm11:{result = RADDBG_RegisterCode_X64_ymm11;}break;
|
||||
case REGS_RegCodeX64_ymm12:{result = RADDBG_RegisterCode_X64_ymm12;}break;
|
||||
case REGS_RegCodeX64_ymm13:{result = RADDBG_RegisterCode_X64_ymm13;}break;
|
||||
case REGS_RegCodeX64_ymm14:{result = RADDBG_RegisterCode_X64_ymm14;}break;
|
||||
case REGS_RegCodeX64_ymm15:{result = RADDBG_RegisterCode_X64_ymm15;}break;
|
||||
}
|
||||
}break;
|
||||
case Architecture_x86:
|
||||
{
|
||||
switch(code)
|
||||
{
|
||||
default:{}break;
|
||||
case REGS_RegCodeX86_eax:{result = RADDBG_RegisterCode_X86_eax;}break;
|
||||
case REGS_RegCodeX86_ecx:{result = RADDBG_RegisterCode_X86_ecx;}break;
|
||||
case REGS_RegCodeX86_edx:{result = RADDBG_RegisterCode_X86_edx;}break;
|
||||
case REGS_RegCodeX86_ebx:{result = RADDBG_RegisterCode_X86_ebx;}break;
|
||||
case REGS_RegCodeX86_esp:{result = RADDBG_RegisterCode_X86_esp;}break;
|
||||
case REGS_RegCodeX86_ebp:{result = RADDBG_RegisterCode_X86_ebp;}break;
|
||||
case REGS_RegCodeX86_esi:{result = RADDBG_RegisterCode_X86_esi;}break;
|
||||
case REGS_RegCodeX86_edi:{result = RADDBG_RegisterCode_X86_edi;}break;
|
||||
case REGS_RegCodeX86_fsbase:{result = RADDBG_RegisterCode_X86_fsbase;}break;
|
||||
case REGS_RegCodeX86_gsbase:{result = RADDBG_RegisterCode_X86_gsbase;}break;
|
||||
case REGS_RegCodeX86_eflags:{result = RADDBG_RegisterCode_X86_eflags;}break;
|
||||
case REGS_RegCodeX86_eip:{result = RADDBG_RegisterCode_X86_eip;}break;
|
||||
case REGS_RegCodeX86_dr0:{result = RADDBG_RegisterCode_X86_dr0;}break;
|
||||
case REGS_RegCodeX86_dr1:{result = RADDBG_RegisterCode_X86_dr1;}break;
|
||||
case REGS_RegCodeX86_dr2:{result = RADDBG_RegisterCode_X86_dr2;}break;
|
||||
case REGS_RegCodeX86_dr3:{result = RADDBG_RegisterCode_X86_dr3;}break;
|
||||
case REGS_RegCodeX86_dr4:{result = RADDBG_RegisterCode_X86_dr4;}break;
|
||||
case REGS_RegCodeX86_dr5:{result = RADDBG_RegisterCode_X86_dr5;}break;
|
||||
case REGS_RegCodeX86_dr6:{result = RADDBG_RegisterCode_X86_dr6;}break;
|
||||
case REGS_RegCodeX86_dr7:{result = RADDBG_RegisterCode_X86_dr7;}break;
|
||||
case REGS_RegCodeX86_fpr0:{result = RADDBG_RegisterCode_X86_fpr0;}break;
|
||||
case REGS_RegCodeX86_fpr1:{result = RADDBG_RegisterCode_X86_fpr1;}break;
|
||||
case REGS_RegCodeX86_fpr2:{result = RADDBG_RegisterCode_X86_fpr2;}break;
|
||||
case REGS_RegCodeX86_fpr3:{result = RADDBG_RegisterCode_X86_fpr3;}break;
|
||||
case REGS_RegCodeX86_fpr4:{result = RADDBG_RegisterCode_X86_fpr4;}break;
|
||||
case REGS_RegCodeX86_fpr5:{result = RADDBG_RegisterCode_X86_fpr5;}break;
|
||||
case REGS_RegCodeX86_fpr6:{result = RADDBG_RegisterCode_X86_fpr6;}break;
|
||||
case REGS_RegCodeX86_fpr7:{result = RADDBG_RegisterCode_X86_fpr7;}break;
|
||||
case REGS_RegCodeX86_st0:{result = RADDBG_RegisterCode_X86_st0;}break;
|
||||
case REGS_RegCodeX86_st1:{result = RADDBG_RegisterCode_X86_st1;}break;
|
||||
case REGS_RegCodeX86_st2:{result = RADDBG_RegisterCode_X86_st2;}break;
|
||||
case REGS_RegCodeX86_st3:{result = RADDBG_RegisterCode_X86_st3;}break;
|
||||
case REGS_RegCodeX86_st4:{result = RADDBG_RegisterCode_X86_st4;}break;
|
||||
case REGS_RegCodeX86_st5:{result = RADDBG_RegisterCode_X86_st5;}break;
|
||||
case REGS_RegCodeX86_st6:{result = RADDBG_RegisterCode_X86_st6;}break;
|
||||
case REGS_RegCodeX86_st7:{result = RADDBG_RegisterCode_X86_st7;}break;
|
||||
case REGS_RegCodeX86_fcw:{result = RADDBG_RegisterCode_X86_fcw;}break;
|
||||
case REGS_RegCodeX86_fsw:{result = RADDBG_RegisterCode_X86_fsw;}break;
|
||||
case REGS_RegCodeX86_ftw:{result = RADDBG_RegisterCode_X86_ftw;}break;
|
||||
case REGS_RegCodeX86_fop:{result = RADDBG_RegisterCode_X86_fop;}break;
|
||||
case REGS_RegCodeX86_fcs:{result = RADDBG_RegisterCode_X86_fcs;}break;
|
||||
case REGS_RegCodeX86_fds:{result = RADDBG_RegisterCode_X86_fds;}break;
|
||||
case REGS_RegCodeX86_fip:{result = RADDBG_RegisterCode_X86_fip;}break;
|
||||
case REGS_RegCodeX86_fdp:{result = RADDBG_RegisterCode_X86_fdp;}break;
|
||||
case REGS_RegCodeX86_mxcsr:{result = RADDBG_RegisterCode_X86_mxcsr;}break;
|
||||
case REGS_RegCodeX86_mxcsr_mask:{result = RADDBG_RegisterCode_X86_mxcsr_mask;}break;
|
||||
case REGS_RegCodeX86_ss:{result = RADDBG_RegisterCode_X86_ss;}break;
|
||||
case REGS_RegCodeX86_cs:{result = RADDBG_RegisterCode_X86_cs;}break;
|
||||
case REGS_RegCodeX86_ds:{result = RADDBG_RegisterCode_X86_ds;}break;
|
||||
case REGS_RegCodeX86_es:{result = RADDBG_RegisterCode_X86_es;}break;
|
||||
case REGS_RegCodeX86_fs:{result = RADDBG_RegisterCode_X86_fs;}break;
|
||||
case REGS_RegCodeX86_gs:{result = RADDBG_RegisterCode_X86_gs;}break;
|
||||
case REGS_RegCodeX86_ymm0:{result = RADDBG_RegisterCode_X86_ymm0;}break;
|
||||
case REGS_RegCodeX86_ymm1:{result = RADDBG_RegisterCode_X86_ymm1;}break;
|
||||
case REGS_RegCodeX86_ymm2:{result = RADDBG_RegisterCode_X86_ymm2;}break;
|
||||
case REGS_RegCodeX86_ymm3:{result = RADDBG_RegisterCode_X86_ymm3;}break;
|
||||
case REGS_RegCodeX86_ymm4:{result = RADDBG_RegisterCode_X86_ymm4;}break;
|
||||
case REGS_RegCodeX86_ymm5:{result = RADDBG_RegisterCode_X86_ymm5;}break;
|
||||
case REGS_RegCodeX86_ymm6:{result = RADDBG_RegisterCode_X86_ymm6;}break;
|
||||
case REGS_RegCodeX86_ymm7:{result = RADDBG_RegisterCode_X86_ymm7;}break;
|
||||
}
|
||||
}break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
internal REGS_RegCode regs_reg_code_from_arch_raddbg_code(Architecture arch, RADDBG_RegisterCode code)
|
||||
{
|
||||
REGS_RegCode result = 0;
|
||||
switch(arch)
|
||||
{
|
||||
default:{}break;
|
||||
case Architecture_x64:
|
||||
{
|
||||
switch(code)
|
||||
{
|
||||
default:{}break;
|
||||
case RADDBG_RegisterCode_X64_rax:{result = REGS_RegCodeX64_rax;}break;
|
||||
case RADDBG_RegisterCode_X64_rcx:{result = REGS_RegCodeX64_rcx;}break;
|
||||
case RADDBG_RegisterCode_X64_rdx:{result = REGS_RegCodeX64_rdx;}break;
|
||||
case RADDBG_RegisterCode_X64_rbx:{result = REGS_RegCodeX64_rbx;}break;
|
||||
case RADDBG_RegisterCode_X64_rsp:{result = REGS_RegCodeX64_rsp;}break;
|
||||
case RADDBG_RegisterCode_X64_rbp:{result = REGS_RegCodeX64_rbp;}break;
|
||||
case RADDBG_RegisterCode_X64_rsi:{result = REGS_RegCodeX64_rsi;}break;
|
||||
case RADDBG_RegisterCode_X64_rdi:{result = REGS_RegCodeX64_rdi;}break;
|
||||
case RADDBG_RegisterCode_X64_r8:{result = REGS_RegCodeX64_r8;}break;
|
||||
case RADDBG_RegisterCode_X64_r9:{result = REGS_RegCodeX64_r9;}break;
|
||||
case RADDBG_RegisterCode_X64_r10:{result = REGS_RegCodeX64_r10;}break;
|
||||
case RADDBG_RegisterCode_X64_r11:{result = REGS_RegCodeX64_r11;}break;
|
||||
case RADDBG_RegisterCode_X64_r12:{result = REGS_RegCodeX64_r12;}break;
|
||||
case RADDBG_RegisterCode_X64_r13:{result = REGS_RegCodeX64_r13;}break;
|
||||
case RADDBG_RegisterCode_X64_r14:{result = REGS_RegCodeX64_r14;}break;
|
||||
case RADDBG_RegisterCode_X64_r15:{result = REGS_RegCodeX64_r15;}break;
|
||||
case RADDBG_RegisterCode_X64_fsbase:{result = REGS_RegCodeX64_fsbase;}break;
|
||||
case RADDBG_RegisterCode_X64_gsbase:{result = REGS_RegCodeX64_gsbase;}break;
|
||||
case RADDBG_RegisterCode_X64_rip:{result = REGS_RegCodeX64_rip;}break;
|
||||
case RADDBG_RegisterCode_X64_rflags:{result = REGS_RegCodeX64_rflags;}break;
|
||||
case RADDBG_RegisterCode_X64_dr0:{result = REGS_RegCodeX64_dr0;}break;
|
||||
case RADDBG_RegisterCode_X64_dr1:{result = REGS_RegCodeX64_dr1;}break;
|
||||
case RADDBG_RegisterCode_X64_dr2:{result = REGS_RegCodeX64_dr2;}break;
|
||||
case RADDBG_RegisterCode_X64_dr3:{result = REGS_RegCodeX64_dr3;}break;
|
||||
case RADDBG_RegisterCode_X64_dr4:{result = REGS_RegCodeX64_dr4;}break;
|
||||
case RADDBG_RegisterCode_X64_dr5:{result = REGS_RegCodeX64_dr5;}break;
|
||||
case RADDBG_RegisterCode_X64_dr6:{result = REGS_RegCodeX64_dr6;}break;
|
||||
case RADDBG_RegisterCode_X64_dr7:{result = REGS_RegCodeX64_dr7;}break;
|
||||
case RADDBG_RegisterCode_X64_fpr0:{result = REGS_RegCodeX64_fpr0;}break;
|
||||
case RADDBG_RegisterCode_X64_fpr1:{result = REGS_RegCodeX64_fpr1;}break;
|
||||
case RADDBG_RegisterCode_X64_fpr2:{result = REGS_RegCodeX64_fpr2;}break;
|
||||
case RADDBG_RegisterCode_X64_fpr3:{result = REGS_RegCodeX64_fpr3;}break;
|
||||
case RADDBG_RegisterCode_X64_fpr4:{result = REGS_RegCodeX64_fpr4;}break;
|
||||
case RADDBG_RegisterCode_X64_fpr5:{result = REGS_RegCodeX64_fpr5;}break;
|
||||
case RADDBG_RegisterCode_X64_fpr6:{result = REGS_RegCodeX64_fpr6;}break;
|
||||
case RADDBG_RegisterCode_X64_fpr7:{result = REGS_RegCodeX64_fpr7;}break;
|
||||
case RADDBG_RegisterCode_X64_st0:{result = REGS_RegCodeX64_st0;}break;
|
||||
case RADDBG_RegisterCode_X64_st1:{result = REGS_RegCodeX64_st1;}break;
|
||||
case RADDBG_RegisterCode_X64_st2:{result = REGS_RegCodeX64_st2;}break;
|
||||
case RADDBG_RegisterCode_X64_st3:{result = REGS_RegCodeX64_st3;}break;
|
||||
case RADDBG_RegisterCode_X64_st4:{result = REGS_RegCodeX64_st4;}break;
|
||||
case RADDBG_RegisterCode_X64_st5:{result = REGS_RegCodeX64_st5;}break;
|
||||
case RADDBG_RegisterCode_X64_st6:{result = REGS_RegCodeX64_st6;}break;
|
||||
case RADDBG_RegisterCode_X64_st7:{result = REGS_RegCodeX64_st7;}break;
|
||||
case RADDBG_RegisterCode_X64_fcw:{result = REGS_RegCodeX64_fcw;}break;
|
||||
case RADDBG_RegisterCode_X64_fsw:{result = REGS_RegCodeX64_fsw;}break;
|
||||
case RADDBG_RegisterCode_X64_ftw:{result = REGS_RegCodeX64_ftw;}break;
|
||||
case RADDBG_RegisterCode_X64_fop:{result = REGS_RegCodeX64_fop;}break;
|
||||
case RADDBG_RegisterCode_X64_fcs:{result = REGS_RegCodeX64_fcs;}break;
|
||||
case RADDBG_RegisterCode_X64_fds:{result = REGS_RegCodeX64_fds;}break;
|
||||
case RADDBG_RegisterCode_X64_fip:{result = REGS_RegCodeX64_fip;}break;
|
||||
case RADDBG_RegisterCode_X64_fdp:{result = REGS_RegCodeX64_fdp;}break;
|
||||
case RADDBG_RegisterCode_X64_mxcsr:{result = REGS_RegCodeX64_mxcsr;}break;
|
||||
case RADDBG_RegisterCode_X64_mxcsr_mask:{result = REGS_RegCodeX64_mxcsr_mask;}break;
|
||||
case RADDBG_RegisterCode_X64_ss:{result = REGS_RegCodeX64_ss;}break;
|
||||
case RADDBG_RegisterCode_X64_cs:{result = REGS_RegCodeX64_cs;}break;
|
||||
case RADDBG_RegisterCode_X64_ds:{result = REGS_RegCodeX64_ds;}break;
|
||||
case RADDBG_RegisterCode_X64_es:{result = REGS_RegCodeX64_es;}break;
|
||||
case RADDBG_RegisterCode_X64_fs:{result = REGS_RegCodeX64_fs;}break;
|
||||
case RADDBG_RegisterCode_X64_gs:{result = REGS_RegCodeX64_gs;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm0:{result = REGS_RegCodeX64_ymm0;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm1:{result = REGS_RegCodeX64_ymm1;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm2:{result = REGS_RegCodeX64_ymm2;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm3:{result = REGS_RegCodeX64_ymm3;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm4:{result = REGS_RegCodeX64_ymm4;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm5:{result = REGS_RegCodeX64_ymm5;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm6:{result = REGS_RegCodeX64_ymm6;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm7:{result = REGS_RegCodeX64_ymm7;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm8:{result = REGS_RegCodeX64_ymm8;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm9:{result = REGS_RegCodeX64_ymm9;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm10:{result = REGS_RegCodeX64_ymm10;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm11:{result = REGS_RegCodeX64_ymm11;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm12:{result = REGS_RegCodeX64_ymm12;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm13:{result = REGS_RegCodeX64_ymm13;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm14:{result = REGS_RegCodeX64_ymm14;}break;
|
||||
case RADDBG_RegisterCode_X64_ymm15:{result = REGS_RegCodeX64_ymm15;}break;
|
||||
}
|
||||
}break;
|
||||
case Architecture_x86:
|
||||
{
|
||||
switch(code)
|
||||
{
|
||||
default:{}break;
|
||||
case RADDBG_RegisterCode_X86_eax:{result = REGS_RegCodeX86_eax;}break;
|
||||
case RADDBG_RegisterCode_X86_ecx:{result = REGS_RegCodeX86_ecx;}break;
|
||||
case RADDBG_RegisterCode_X86_edx:{result = REGS_RegCodeX86_edx;}break;
|
||||
case RADDBG_RegisterCode_X86_ebx:{result = REGS_RegCodeX86_ebx;}break;
|
||||
case RADDBG_RegisterCode_X86_esp:{result = REGS_RegCodeX86_esp;}break;
|
||||
case RADDBG_RegisterCode_X86_ebp:{result = REGS_RegCodeX86_ebp;}break;
|
||||
case RADDBG_RegisterCode_X86_esi:{result = REGS_RegCodeX86_esi;}break;
|
||||
case RADDBG_RegisterCode_X86_edi:{result = REGS_RegCodeX86_edi;}break;
|
||||
case RADDBG_RegisterCode_X86_fsbase:{result = REGS_RegCodeX86_fsbase;}break;
|
||||
case RADDBG_RegisterCode_X86_gsbase:{result = REGS_RegCodeX86_gsbase;}break;
|
||||
case RADDBG_RegisterCode_X86_eflags:{result = REGS_RegCodeX86_eflags;}break;
|
||||
case RADDBG_RegisterCode_X86_eip:{result = REGS_RegCodeX86_eip;}break;
|
||||
case RADDBG_RegisterCode_X86_dr0:{result = REGS_RegCodeX86_dr0;}break;
|
||||
case RADDBG_RegisterCode_X86_dr1:{result = REGS_RegCodeX86_dr1;}break;
|
||||
case RADDBG_RegisterCode_X86_dr2:{result = REGS_RegCodeX86_dr2;}break;
|
||||
case RADDBG_RegisterCode_X86_dr3:{result = REGS_RegCodeX86_dr3;}break;
|
||||
case RADDBG_RegisterCode_X86_dr4:{result = REGS_RegCodeX86_dr4;}break;
|
||||
case RADDBG_RegisterCode_X86_dr5:{result = REGS_RegCodeX86_dr5;}break;
|
||||
case RADDBG_RegisterCode_X86_dr6:{result = REGS_RegCodeX86_dr6;}break;
|
||||
case RADDBG_RegisterCode_X86_dr7:{result = REGS_RegCodeX86_dr7;}break;
|
||||
case RADDBG_RegisterCode_X86_fpr0:{result = REGS_RegCodeX86_fpr0;}break;
|
||||
case RADDBG_RegisterCode_X86_fpr1:{result = REGS_RegCodeX86_fpr1;}break;
|
||||
case RADDBG_RegisterCode_X86_fpr2:{result = REGS_RegCodeX86_fpr2;}break;
|
||||
case RADDBG_RegisterCode_X86_fpr3:{result = REGS_RegCodeX86_fpr3;}break;
|
||||
case RADDBG_RegisterCode_X86_fpr4:{result = REGS_RegCodeX86_fpr4;}break;
|
||||
case RADDBG_RegisterCode_X86_fpr5:{result = REGS_RegCodeX86_fpr5;}break;
|
||||
case RADDBG_RegisterCode_X86_fpr6:{result = REGS_RegCodeX86_fpr6;}break;
|
||||
case RADDBG_RegisterCode_X86_fpr7:{result = REGS_RegCodeX86_fpr7;}break;
|
||||
case RADDBG_RegisterCode_X86_st0:{result = REGS_RegCodeX86_st0;}break;
|
||||
case RADDBG_RegisterCode_X86_st1:{result = REGS_RegCodeX86_st1;}break;
|
||||
case RADDBG_RegisterCode_X86_st2:{result = REGS_RegCodeX86_st2;}break;
|
||||
case RADDBG_RegisterCode_X86_st3:{result = REGS_RegCodeX86_st3;}break;
|
||||
case RADDBG_RegisterCode_X86_st4:{result = REGS_RegCodeX86_st4;}break;
|
||||
case RADDBG_RegisterCode_X86_st5:{result = REGS_RegCodeX86_st5;}break;
|
||||
case RADDBG_RegisterCode_X86_st6:{result = REGS_RegCodeX86_st6;}break;
|
||||
case RADDBG_RegisterCode_X86_st7:{result = REGS_RegCodeX86_st7;}break;
|
||||
case RADDBG_RegisterCode_X86_fcw:{result = REGS_RegCodeX86_fcw;}break;
|
||||
case RADDBG_RegisterCode_X86_fsw:{result = REGS_RegCodeX86_fsw;}break;
|
||||
case RADDBG_RegisterCode_X86_ftw:{result = REGS_RegCodeX86_ftw;}break;
|
||||
case RADDBG_RegisterCode_X86_fop:{result = REGS_RegCodeX86_fop;}break;
|
||||
case RADDBG_RegisterCode_X86_fcs:{result = REGS_RegCodeX86_fcs;}break;
|
||||
case RADDBG_RegisterCode_X86_fds:{result = REGS_RegCodeX86_fds;}break;
|
||||
case RADDBG_RegisterCode_X86_fip:{result = REGS_RegCodeX86_fip;}break;
|
||||
case RADDBG_RegisterCode_X86_fdp:{result = REGS_RegCodeX86_fdp;}break;
|
||||
case RADDBG_RegisterCode_X86_mxcsr:{result = REGS_RegCodeX86_mxcsr;}break;
|
||||
case RADDBG_RegisterCode_X86_mxcsr_mask:{result = REGS_RegCodeX86_mxcsr_mask;}break;
|
||||
case RADDBG_RegisterCode_X86_ss:{result = REGS_RegCodeX86_ss;}break;
|
||||
case RADDBG_RegisterCode_X86_cs:{result = REGS_RegCodeX86_cs;}break;
|
||||
case RADDBG_RegisterCode_X86_ds:{result = REGS_RegCodeX86_ds;}break;
|
||||
case RADDBG_RegisterCode_X86_es:{result = REGS_RegCodeX86_es;}break;
|
||||
case RADDBG_RegisterCode_X86_fs:{result = REGS_RegCodeX86_fs;}break;
|
||||
case RADDBG_RegisterCode_X86_gs:{result = REGS_RegCodeX86_gs;}break;
|
||||
case RADDBG_RegisterCode_X86_ymm0:{result = REGS_RegCodeX86_ymm0;}break;
|
||||
case RADDBG_RegisterCode_X86_ymm1:{result = REGS_RegCodeX86_ymm1;}break;
|
||||
case RADDBG_RegisterCode_X86_ymm2:{result = REGS_RegCodeX86_ymm2;}break;
|
||||
case RADDBG_RegisterCode_X86_ymm3:{result = REGS_RegCodeX86_ymm3;}break;
|
||||
case RADDBG_RegisterCode_X86_ymm4:{result = REGS_RegCodeX86_ymm4;}break;
|
||||
case RADDBG_RegisterCode_X86_ymm5:{result = REGS_RegCodeX86_ymm5;}break;
|
||||
case RADDBG_RegisterCode_X86_ymm6:{result = REGS_RegCodeX86_ymm6;}break;
|
||||
case RADDBG_RegisterCode_X86_ymm7:{result = REGS_RegCodeX86_ymm7;}break;
|
||||
}
|
||||
}break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
@@ -0,0 +1,10 @@
|
||||
// Copyright (c) 2024 Epic Games Tools
|
||||
// Licensed under the MIT license (https://opensource.org/license/mit/)
|
||||
|
||||
//- GENERATED CODE
|
||||
|
||||
#ifndef REGS_RADDBG_META_H
|
||||
#define REGS_RADDBG_META_H
|
||||
|
||||
|
||||
#endif // REGS_RADDBG_META_H
|
||||
@@ -0,0 +1,4 @@
|
||||
// Copyright (c) 2024 Epic Games Tools
|
||||
// Licensed under the MIT license (https://opensource.org/license/mit/)
|
||||
|
||||
#include "regs/raddbg/generated/regs_raddbg.meta.c"
|
||||
@@ -0,0 +1,10 @@
|
||||
// Copyright (c) 2024 Epic Games Tools
|
||||
// Licensed under the MIT license (https://opensource.org/license/mit/)
|
||||
|
||||
#ifndef REGS_RADDBG_H
|
||||
#define REGS_RADDBG_H
|
||||
|
||||
internal RADDBG_RegisterCode regs_raddbg_code_from_arch_reg_code(Architecture arch, REGS_RegCode code);
|
||||
internal REGS_RegCode regs_reg_code_from_arch_raddbg_code(Architecture arch, RADDBG_RegisterCode reg);
|
||||
|
||||
#endif //REGS_RADDBG_H
|
||||
@@ -0,0 +1,63 @@
|
||||
// Copyright (c) 2024 Epic Games Tools
|
||||
// Licensed under the MIT license (https://opensource.org/license/mit/)
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: RADDBG Converter Helper Implementation Generators
|
||||
|
||||
@table_gen @c_file
|
||||
{
|
||||
`internal RADDBG_RegisterCode regs_raddbg_code_from_arch_reg_code(Architecture arch, REGS_RegCode code)`;
|
||||
`{`;
|
||||
`RADDBG_RegisterCode result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
`case Architecture_x64:`;
|
||||
`{`;
|
||||
`switch(code)`
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_RegTableX64 a) `case REGS_RegCodeX64_$(a.name):{result = RADDBG_RegisterCode_X64_$(a.name);}break;`;
|
||||
`}`;
|
||||
`}break;`;
|
||||
`case Architecture_x86:`;
|
||||
`{`;
|
||||
`switch(code)`
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_RegTableX86 a) `case REGS_RegCodeX86_$(a.name):{result = RADDBG_RegisterCode_X86_$(a.name);}break;`;
|
||||
`}`;
|
||||
`}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
|
||||
@table_gen @c_file
|
||||
{
|
||||
`internal REGS_RegCode regs_reg_code_from_arch_raddbg_code(Architecture arch, RADDBG_RegisterCode code)`;
|
||||
`{`;
|
||||
`REGS_RegCode result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
`case Architecture_x64:`;
|
||||
`{`;
|
||||
`switch(code)`
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_RegTableX64 a) `case RADDBG_RegisterCode_X64_$(a.name):{result = REGS_RegCodeX64_$(a.name);}break;`;
|
||||
`}`;
|
||||
`}break;`;
|
||||
`case Architecture_x86:`;
|
||||
`{`;
|
||||
`switch(code)`
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_RegTableX86 a) `case RADDBG_RegisterCode_X86_$(a.name):{result = REGS_RegCodeX86_$(a.name);}break;`;
|
||||
`}`;
|
||||
`}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
@@ -0,0 +1,58 @@
|
||||
// Copyright (c) 2024 Epic Games Tools
|
||||
// Licensed under the MIT license (https://opensource.org/license/mit/)
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: Generated Code
|
||||
|
||||
#include "regs/generated/regs.meta.c"
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: Helpers
|
||||
|
||||
internal U64
|
||||
regs_rip_from_arch_block(Architecture arch, void *block)
|
||||
{
|
||||
U64 result = 0;
|
||||
switch(arch)
|
||||
{
|
||||
default:{}break;
|
||||
case Architecture_x64:{result = ((REGS_RegBlockX64 *)block)->rip.u64;}break;
|
||||
case Architecture_x86:{result = (U64)((REGS_RegBlockX86 *)block)->eip.u32;}break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
internal U64
|
||||
regs_rsp_from_arch_block(Architecture arch, void *block)
|
||||
{
|
||||
U64 result = 0;
|
||||
switch(arch)
|
||||
{
|
||||
default:{}break;
|
||||
case Architecture_x64:{result = ((REGS_RegBlockX64 *)block)->rsp.u64;}break;
|
||||
case Architecture_x86:{result = (U64)((REGS_RegBlockX86 *)block)->esp.u32;}break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
internal void
|
||||
regs_arch_block_write_rip(Architecture arch, void *block, U64 rip)
|
||||
{
|
||||
switch(arch)
|
||||
{
|
||||
default:{}break;
|
||||
case Architecture_x64:{((REGS_RegBlockX64 *)block)->rip.u64 = rip;}break;
|
||||
case Architecture_x86:{((REGS_RegBlockX86 *)block)->eip.u32 = (U32)rip;}break;
|
||||
}
|
||||
}
|
||||
|
||||
internal void
|
||||
regs_arch_block_write_rsp(Architecture arch, void *block, U64 rsp)
|
||||
{
|
||||
switch(arch)
|
||||
{
|
||||
default:{}break;
|
||||
case Architecture_x64:{((REGS_RegBlockX64 *)block)->rsp.u64 = rsp;}break;
|
||||
case Architecture_x86:{((REGS_RegBlockX86 *)block)->esp.u32 = (U32)rsp;}break;
|
||||
}
|
||||
}
|
||||
+115
@@ -0,0 +1,115 @@
|
||||
// Copyright (c) 2024 Epic Games Tools
|
||||
// Licensed under the MIT license (https://opensource.org/license/mit/)
|
||||
|
||||
#ifndef REGS_H
|
||||
#define REGS_H
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: Register Usage Kinds
|
||||
|
||||
typedef enum REGS_UsageKind
|
||||
{
|
||||
REGS_UsageKind_Normal,
|
||||
REGS_UsageKind_Vector,
|
||||
}
|
||||
REGS_UsageKind;
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: Register Types
|
||||
|
||||
typedef U8 REGS_RegCode;
|
||||
typedef U8 REGS_AliasCode;
|
||||
|
||||
typedef union REGS_Reg16 REGS_Reg16;
|
||||
union REGS_Reg16
|
||||
{
|
||||
U8 v[2];
|
||||
U16 u16;
|
||||
};
|
||||
|
||||
typedef union REGS_Reg32 REGS_Reg32;
|
||||
union REGS_Reg32
|
||||
{
|
||||
U8 v[4];
|
||||
U32 u32;
|
||||
F32 f32;
|
||||
};
|
||||
|
||||
typedef union REGS_Reg64 REGS_Reg64;
|
||||
union REGS_Reg64
|
||||
{
|
||||
U8 v[8];
|
||||
U64 u64;
|
||||
F64 f64;
|
||||
};
|
||||
|
||||
#pragma pack(push, 1)
|
||||
typedef struct REGS_Reg80 REGS_Reg80;
|
||||
struct REGS_Reg80
|
||||
{
|
||||
U64 int1_frac63;
|
||||
U16 sign1_exp15;
|
||||
};
|
||||
#pragma pack(pop)
|
||||
|
||||
typedef union REGS_Reg128 REGS_Reg128;
|
||||
union REGS_Reg128
|
||||
{
|
||||
U8 v[16];
|
||||
U32 u32[4];
|
||||
F32 f32[4];
|
||||
U64 u64[2];
|
||||
F64 f64[2];
|
||||
};
|
||||
|
||||
typedef union REGS_Reg256 REGS_Reg256;
|
||||
union REGS_Reg256
|
||||
{
|
||||
U8 v[32];
|
||||
U32 u32[8];
|
||||
F32 f32[8];
|
||||
U64 u64[4];
|
||||
F64 f64[4];
|
||||
};
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: Register Slicing Types
|
||||
|
||||
typedef struct REGS_Rng REGS_Rng;
|
||||
struct REGS_Rng
|
||||
{
|
||||
U16 byte_off;
|
||||
U16 byte_size;
|
||||
};
|
||||
|
||||
typedef struct REGS_Slice REGS_Slice;
|
||||
struct REGS_Slice
|
||||
{
|
||||
U16 code;
|
||||
U8 byte_off;
|
||||
U8 byte_size;
|
||||
};
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: Generated Code
|
||||
|
||||
#include "regs/generated/regs.meta.h"
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: Helpers
|
||||
|
||||
internal U64 regs_block_size_from_architecture(Architecture arch);
|
||||
internal U64 regs_reg_code_count_from_architecture(Architecture arch);
|
||||
internal U64 regs_alias_code_count_from_architecture(Architecture arch);
|
||||
internal String8 *regs_reg_code_string_table_from_architecture(Architecture arch);
|
||||
internal String8 *regs_alias_code_string_table_from_architecture(Architecture arch);
|
||||
internal REGS_Rng *regs_reg_code_rng_table_from_architecture(Architecture arch);
|
||||
internal REGS_Slice *regs_alias_code_slice_table_from_architecture(Architecture arch);
|
||||
internal REGS_UsageKind *regs_reg_code_usage_kind_table_from_architecture(Architecture arch);
|
||||
internal REGS_UsageKind *regs_alias_code_usage_kind_table_from_architecture(Architecture arch);
|
||||
internal U64 regs_rip_from_arch_block(Architecture arch, void *block);
|
||||
internal U64 regs_rsp_from_arch_block(Architecture arch, void *block);
|
||||
internal void regs_arch_block_write_rip(Architecture arch, void *block, U64 rip);
|
||||
internal void regs_arch_block_write_rsp(Architecture arch, void *block, U64 rsp);
|
||||
|
||||
#endif // REGS_H
|
||||
@@ -0,0 +1,556 @@
|
||||
// Copyright (c) 2024 Epic Games Tools
|
||||
// Licensed under the MIT license (https://opensource.org/license/mit/)
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: X64 Tables
|
||||
|
||||
@table(name size usage)
|
||||
REGS_RegTableX64:
|
||||
{
|
||||
{rax 64 Normal}
|
||||
{rcx 64 Normal}
|
||||
{rdx 64 Normal}
|
||||
{rbx 64 Normal}
|
||||
{rsp 64 Normal}
|
||||
{rbp 64 Normal}
|
||||
{rsi 64 Normal}
|
||||
{rdi 64 Normal}
|
||||
{r8 64 Normal}
|
||||
{r9 64 Normal}
|
||||
{r10 64 Normal}
|
||||
{r11 64 Normal}
|
||||
{r12 64 Normal}
|
||||
{r13 64 Normal}
|
||||
{r14 64 Normal}
|
||||
{r15 64 Normal}
|
||||
{fsbase 64 Normal}
|
||||
{gsbase 64 Normal}
|
||||
{rip 64 Normal}
|
||||
{rflags 64 Normal}
|
||||
{dr0 32 Normal}
|
||||
{dr1 32 Normal}
|
||||
{dr2 32 Normal}
|
||||
{dr3 32 Normal}
|
||||
{dr4 32 Normal}
|
||||
{dr5 32 Normal}
|
||||
{dr6 32 Normal}
|
||||
{dr7 32 Normal}
|
||||
{fpr0 80 Normal}
|
||||
{fpr1 80 Normal}
|
||||
{fpr2 80 Normal}
|
||||
{fpr3 80 Normal}
|
||||
{fpr4 80 Normal}
|
||||
{fpr5 80 Normal}
|
||||
{fpr6 80 Normal}
|
||||
{fpr7 80 Normal}
|
||||
{st0 80 Normal}
|
||||
{st1 80 Normal}
|
||||
{st2 80 Normal}
|
||||
{st3 80 Normal}
|
||||
{st4 80 Normal}
|
||||
{st5 80 Normal}
|
||||
{st6 80 Normal}
|
||||
{st7 80 Normal}
|
||||
{fcw 16 Normal}
|
||||
{fsw 16 Normal}
|
||||
{ftw 16 Normal}
|
||||
{fop 16 Normal}
|
||||
{fcs 16 Normal}
|
||||
{fds 16 Normal}
|
||||
{fip 32 Normal}
|
||||
{fdp 32 Normal}
|
||||
{mxcsr 32 Normal}
|
||||
{mxcsr_mask 32 Normal}
|
||||
{ss 16 Normal}
|
||||
{cs 16 Normal}
|
||||
{ds 16 Normal}
|
||||
{es 16 Normal}
|
||||
{fs 16 Normal}
|
||||
{gs 16 Normal}
|
||||
{ymm0 256 Normal}
|
||||
{ymm1 256 Normal}
|
||||
{ymm2 256 Normal}
|
||||
{ymm3 256 Normal}
|
||||
{ymm4 256 Normal}
|
||||
{ymm5 256 Normal}
|
||||
{ymm6 256 Normal}
|
||||
{ymm7 256 Normal}
|
||||
{ymm8 256 Normal}
|
||||
{ymm9 256 Normal}
|
||||
{ymm10 256 Normal}
|
||||
{ymm11 256 Normal}
|
||||
{ymm12 256 Normal}
|
||||
{ymm13 256 Normal}
|
||||
{ymm14 256 Normal}
|
||||
{ymm15 256 Normal}
|
||||
}
|
||||
|
||||
@table(name base off size usage)
|
||||
REGS_AliasTableX64:
|
||||
{
|
||||
{eax rax 0 32 Normal}
|
||||
{ecx rcx 0 32 Normal}
|
||||
{edx rdx 0 32 Normal}
|
||||
{ebx rbx 0 32 Normal}
|
||||
{esp rsp 0 32 Normal}
|
||||
{ebp rbp 0 32 Normal}
|
||||
{esi rsi 0 32 Normal}
|
||||
{edi rdi 0 32 Normal}
|
||||
{r8d r8 0 32 Normal}
|
||||
{r9d r9 0 32 Normal}
|
||||
{r10d r10 0 32 Normal}
|
||||
{r11d r11 0 32 Normal}
|
||||
{r12d r12 0 32 Normal}
|
||||
{r13d r13 0 32 Normal}
|
||||
{r14d r14 0 32 Normal}
|
||||
{r15d r15 0 32 Normal}
|
||||
|
||||
// TODO(allen): figure this one out; visual studio disagrees
|
||||
{eip rip 0 32 Normal}
|
||||
|
||||
{eflags rflags 0 32 Normal}
|
||||
{ax rax 0 16 Normal}
|
||||
{cx rcx 0 16 Normal}
|
||||
{dx rdx 0 16 Normal}
|
||||
{bx rbx 0 16 Normal}
|
||||
{si rsi 0 16 Normal}
|
||||
{di rdi 0 16 Normal}
|
||||
{sp rsp 0 16 Normal}
|
||||
{bp rbp 0 16 Normal}
|
||||
{ip rip 0 16 Normal}
|
||||
{r8w r8 0 16 Normal}
|
||||
{r9w r9 0 16 Normal}
|
||||
{r10w r10 0 16 Normal}
|
||||
{r11w r11 0 16 Normal}
|
||||
{r12w r12 0 16 Normal}
|
||||
{r13w r13 0 16 Normal}
|
||||
{r14w r14 0 16 Normal}
|
||||
{r15w r15 0 16 Normal}
|
||||
{al rax 0 8 Normal}
|
||||
{cl rcx 0 8 Normal}
|
||||
{dl rdx 0 8 Normal}
|
||||
{bl rbx 0 8 Normal}
|
||||
{sil rsi 0 8 Normal}
|
||||
{dil rdi 0 8 Normal}
|
||||
{bpl rbp 0 8 Normal}
|
||||
{spl rsp 0 8 Normal}
|
||||
{r8b r8 0 8 Normal}
|
||||
{r9b r9 0 8 Normal}
|
||||
{r10b r10 0 8 Normal}
|
||||
{r11b r11 0 8 Normal}
|
||||
{r12b r12 0 8 Normal}
|
||||
{r13b r13 0 8 Normal}
|
||||
{r14b r14 0 8 Normal}
|
||||
{r15b r15 0 8 Normal}
|
||||
{ah rax 8 8 Normal}
|
||||
{ch rcx 8 8 Normal}
|
||||
{dh rdx 8 8 Normal}
|
||||
{bh rbx 8 8 Normal}
|
||||
{xmm0 ymm0 0 128 Normal}
|
||||
{xmm1 ymm1 0 128 Normal}
|
||||
{xmm2 ymm2 0 128 Normal}
|
||||
{xmm3 ymm3 0 128 Normal}
|
||||
{xmm4 ymm4 0 128 Normal}
|
||||
{xmm5 ymm5 0 128 Normal}
|
||||
{xmm6 ymm6 0 128 Normal}
|
||||
{xmm7 ymm7 0 128 Normal}
|
||||
{xmm8 ymm8 0 128 Normal}
|
||||
{xmm9 ymm9 0 128 Normal}
|
||||
{xmm10 ymm10 0 128 Normal}
|
||||
{xmm11 ymm11 0 128 Normal}
|
||||
{xmm12 ymm12 0 128 Normal}
|
||||
{xmm13 ymm13 0 128 Normal}
|
||||
{xmm14 ymm14 0 128 Normal}
|
||||
{xmm15 ymm15 0 128 Normal}
|
||||
{mm0 fpr0 0 64 Normal}
|
||||
{mm1 fpr1 0 64 Normal}
|
||||
{mm2 fpr2 0 64 Normal}
|
||||
{mm3 fpr3 0 64 Normal}
|
||||
{mm4 fpr4 0 64 Normal}
|
||||
{mm5 fpr5 0 64 Normal}
|
||||
{mm6 fpr6 0 64 Normal}
|
||||
{mm7 fpr7 0 64 Normal}
|
||||
}
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: X86 Tables
|
||||
|
||||
@table(name size usage)
|
||||
REGS_RegTableX86:
|
||||
{
|
||||
{eax 32 Normal}
|
||||
{ecx 32 Normal}
|
||||
{edx 32 Normal}
|
||||
{ebx 32 Normal}
|
||||
{esp 32 Normal}
|
||||
{ebp 32 Normal}
|
||||
{esi 32 Normal}
|
||||
{edi 32 Normal}
|
||||
{fsbase 32 Normal}
|
||||
{gsbase 32 Normal}
|
||||
{eflags 32 Normal}
|
||||
{eip 32 Normal}
|
||||
{dr0 32 Normal}
|
||||
{dr1 32 Normal}
|
||||
{dr2 32 Normal}
|
||||
{dr3 32 Normal}
|
||||
{dr4 32 Normal}
|
||||
{dr5 32 Normal}
|
||||
{dr6 32 Normal}
|
||||
{dr7 32 Normal}
|
||||
// FSave registers
|
||||
// TODO(allen): I am suspicious of this stuff here.
|
||||
// Are fpr0-7 and st0-7 actually different things? Visual studio doesn't show
|
||||
// frp0-7. Not sure if the mm0-7 aliases are setup the right way either.
|
||||
{fpr0 80 Normal}
|
||||
{fpr1 80 Normal}
|
||||
{fpr2 80 Normal}
|
||||
{fpr3 80 Normal}
|
||||
{fpr4 80 Normal}
|
||||
{fpr5 80 Normal}
|
||||
{fpr6 80 Normal}
|
||||
{fpr7 80 Normal}
|
||||
{st0 80 Normal}
|
||||
{st1 80 Normal}
|
||||
{st2 80 Normal}
|
||||
{st3 80 Normal}
|
||||
{st4 80 Normal}
|
||||
{st5 80 Normal}
|
||||
{st6 80 Normal}
|
||||
{st7 80 Normal}
|
||||
{fcw 16 Normal}
|
||||
{fsw 16 Normal}
|
||||
{ftw 16 Normal}
|
||||
{fop 16 Normal}
|
||||
{fcs 16 Normal}
|
||||
{fds 16 Normal}
|
||||
{fip 32 Normal}
|
||||
{fdp 32 Normal}
|
||||
{mxcsr 32 Normal}
|
||||
// TODO(allen): I don't think this is really a "register" - think about this...
|
||||
{mxcsr_mask 32 Normal}
|
||||
{ss 16 Normal}
|
||||
{cs 16 Normal}
|
||||
{ds 16 Normal}
|
||||
{es 16 Normal}
|
||||
{fs 16 Normal}
|
||||
{gs 16 Normal}
|
||||
// SIMD REGISTERS
|
||||
{ymm0 256 Normal}
|
||||
{ymm1 256 Normal}
|
||||
{ymm2 256 Normal}
|
||||
{ymm3 256 Normal}
|
||||
{ymm4 256 Normal}
|
||||
{ymm5 256 Normal}
|
||||
{ymm6 256 Normal}
|
||||
{ymm7 256 Normal}
|
||||
}
|
||||
|
||||
@table(name base off size usage)
|
||||
REGS_AliasTableX86:
|
||||
{
|
||||
{ax eax 0 16 Normal}
|
||||
{cx ecx 0 16 Normal}
|
||||
{bx ebx 0 16 Normal}
|
||||
{dx edx 0 16 Normal}
|
||||
{sp esp 0 16 Normal}
|
||||
{bp ebp 0 16 Normal}
|
||||
{si esi 0 16 Normal}
|
||||
{di edi 0 16 Normal}
|
||||
{ip eip 0 16 Normal}
|
||||
{ah eax 8 8 Normal}
|
||||
{ch ecx 8 8 Normal}
|
||||
{dh edx 8 8 Normal}
|
||||
{bh ebx 8 8 Normal}
|
||||
{al eax 0 8 Normal}
|
||||
{cl ecx 0 8 Normal}
|
||||
{dl edx 0 8 Normal}
|
||||
{bl ebx 0 8 Normal}
|
||||
{bpl ebp 0 8 Normal}
|
||||
{spl esp 0 8 Normal}
|
||||
{xmm0 ymm0 0 128 Normal}
|
||||
{xmm1 ymm1 0 128 Normal}
|
||||
{xmm2 ymm2 0 128 Normal}
|
||||
{xmm3 ymm3 0 128 Normal}
|
||||
{xmm4 ymm4 0 128 Normal}
|
||||
{xmm5 ymm5 0 128 Normal}
|
||||
{xmm6 ymm6 0 128 Normal}
|
||||
{xmm7 ymm7 0 128 Normal}
|
||||
{mm0 fpr0 0 64 Normal}
|
||||
{mm1 fpr1 0 64 Normal}
|
||||
{mm2 fpr2 0 64 Normal}
|
||||
{mm3 fpr3 0 64 Normal}
|
||||
{mm4 fpr4 0 64 Normal}
|
||||
{mm5 fpr5 0 64 Normal}
|
||||
{mm6 fpr6 0 64 Normal}
|
||||
{mm7 fpr7 0 64 Normal}
|
||||
}
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: Architecture Tables
|
||||
|
||||
@table(name, name_lower)
|
||||
REGS_ArchTable:
|
||||
{
|
||||
{X64 x64}
|
||||
{X86 x86}
|
||||
}
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: X64 Generators
|
||||
|
||||
@table_gen_enum REGS_RegCodeX64:
|
||||
{
|
||||
`REGS_RegCodeX64_NULL,`;
|
||||
@expand(REGS_RegTableX64 a) `REGS_RegCodeX64_$(a.name),`;
|
||||
`REGS_RegCodeX64_COUNT`;
|
||||
}
|
||||
|
||||
@table_gen_enum REGS_AliasCodeX64:
|
||||
{
|
||||
`REGS_AliasCodeX64_NULL,`;
|
||||
@expand(REGS_AliasTableX64 a) `REGS_AliasCodeX64_$(a.name),`;
|
||||
`REGS_AliasCodeX64_COUNT`;
|
||||
}
|
||||
|
||||
@table_gen_struct
|
||||
REGS_RegBlockX64:
|
||||
{
|
||||
@expand(REGS_RegTableX64 a) `REGS_Reg$(a.size) $(a.name);`;
|
||||
}
|
||||
|
||||
@table_gen_data(type:REGS_UsageKind, fallback:`REGS_UsageKind_Normal`)
|
||||
regs_g_reg_code_x64_usage_kind_table:
|
||||
{
|
||||
`REGS_UsageKind_Normal,`;
|
||||
@expand(REGS_RegTableX64 a) `REGS_UsageKind_$(a.usage),`;
|
||||
}
|
||||
|
||||
@table_gen_data(type:REGS_UsageKind, fallback:`REGS_UsageKind_Normal`)
|
||||
regs_g_alias_code_x64_usage_kind_table:
|
||||
{
|
||||
`REGS_UsageKind_Normal,`;
|
||||
@expand(REGS_AliasTableX64 a) `REGS_UsageKind_$(a.usage),`;
|
||||
}
|
||||
|
||||
@table_gen_data(type:String8, fallback:`{0}`)
|
||||
regs_g_reg_code_x64_string_table:
|
||||
{
|
||||
`str8_lit_comp(""),`;
|
||||
@expand(REGS_RegTableX64 a) `str8_lit_comp("$(a.name)"),`;
|
||||
}
|
||||
|
||||
@table_gen_data(type:String8, fallback:`{0}`)
|
||||
regs_g_alias_code_x64_string_table:
|
||||
{
|
||||
`str8_lit_comp(""),`;
|
||||
@expand(REGS_AliasTableX64 a) `str8_lit_comp("$(a.name)"),`;
|
||||
}
|
||||
|
||||
@table_gen_data(type: REGS_Rng, fallback: `{0}`)
|
||||
regs_g_reg_code_x64_rng_table:
|
||||
{
|
||||
`{0},`;
|
||||
@expand(REGS_RegTableX64 a) `{(U16)OffsetOf(REGS_RegBlockX64, $(a.name)), $(a.size/8)},`,
|
||||
}
|
||||
|
||||
@table_gen_data(type: REGS_Slice, fallback: `{0}`)
|
||||
regs_g_alias_code_x64_slice_table:
|
||||
{
|
||||
`{0},`;
|
||||
@expand(REGS_AliasTableX64 a) `{REGS_RegCodeX64_$(a.base), $(a.off/8), $(a.size/8)},`,
|
||||
}
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: X86 Generators
|
||||
|
||||
@table_gen_enum REGS_RegCodeX86:
|
||||
{
|
||||
`REGS_RegCodeX86_NULL,`;
|
||||
@expand(REGS_RegTableX86 a) `REGS_RegCodeX86_$(a.name),`;
|
||||
`REGS_RegCodeX86_COUNT`;
|
||||
}
|
||||
|
||||
@table_gen_enum REGS_AliasCodeX86:
|
||||
{
|
||||
`REGS_AliasCodeX86_NULL,`;
|
||||
@expand(REGS_AliasTableX86 a) `REGS_AliasCodeX86_$(a.name),`;
|
||||
`REGS_AliasCodeX86_COUNT`;
|
||||
}
|
||||
|
||||
@table_gen_struct
|
||||
REGS_RegBlockX86:
|
||||
{
|
||||
@expand(REGS_RegTableX86 a) `REGS_Reg$(a.size) $(a.name);`;
|
||||
}
|
||||
|
||||
@table_gen_data(type:REGS_UsageKind, fallback:`REGS_UsageKind_Normal`)
|
||||
regs_g_reg_code_x86_usage_kind_table:
|
||||
{
|
||||
`REGS_UsageKind_Normal,`;
|
||||
@expand(REGS_RegTableX86 a) `REGS_UsageKind_$(a.usage),`;
|
||||
}
|
||||
|
||||
@table_gen_data(type:REGS_UsageKind, fallback:`REGS_UsageKind_Normal`)
|
||||
regs_g_alias_code_x86_usage_kind_table:
|
||||
{
|
||||
`REGS_UsageKind_Normal,`;
|
||||
@expand(REGS_AliasTableX86 a) `REGS_UsageKind_$(a.usage),`;
|
||||
}
|
||||
|
||||
@table_gen_data(type:String8, fallback:`{0}`)
|
||||
regs_g_reg_code_x86_string_table:
|
||||
{
|
||||
`str8_lit_comp(""),`;
|
||||
@expand(REGS_RegTableX86 a) `str8_lit_comp("$(a.name)"),`;
|
||||
}
|
||||
|
||||
@table_gen_data(type:String8, fallback:`{0}`)
|
||||
regs_g_alias_code_x86_string_table:
|
||||
{
|
||||
`str8_lit_comp(""),`;
|
||||
@expand(REGS_AliasTableX86 a) `str8_lit_comp("$(a.name)"),`;
|
||||
}
|
||||
|
||||
@table_gen_data(type: REGS_Rng, fallback: `{0}`)
|
||||
regs_g_reg_code_x86_rng_table:
|
||||
{
|
||||
`{0},`;
|
||||
@expand(REGS_RegTableX86 a) `{(U16)OffsetOf(REGS_RegBlockX86, $(a.name)), $(a.size/8)},`,
|
||||
}
|
||||
|
||||
@table_gen_data(type: REGS_Slice, fallback: `{0}`)
|
||||
regs_g_alias_code_x86_slice_table:
|
||||
{
|
||||
`{0},`;
|
||||
@expand(REGS_AliasTableX86 a) `{REGS_RegCodeX86_$(a.base), $(a.off/8), $(a.size/8)},`,
|
||||
}
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: Architecture-Dynamic Helper Implementation Generators
|
||||
|
||||
@c_file @table_gen
|
||||
{
|
||||
`internal U64 regs_block_size_from_architecture(Architecture arch)`;
|
||||
`{`;
|
||||
`U64 result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_ArchTable a) `case Architecture_$(a.name_lower):{result = sizeof(REGS_RegBlock$(a.name));}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
|
||||
@c_file @table_gen
|
||||
{
|
||||
`internal U64 regs_reg_code_count_from_architecture(Architecture arch)`;
|
||||
`{`;
|
||||
`U64 result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_ArchTable a) `case Architecture_$(a.name_lower):{result = REGS_RegCode$(a.name)_COUNT;}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
|
||||
@c_file @table_gen
|
||||
{
|
||||
`internal U64 regs_alias_code_count_from_architecture(Architecture arch)`;
|
||||
`{`;
|
||||
`U64 result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_ArchTable a) `case Architecture_$(a.name_lower):{result = REGS_AliasCode$(a.name)_COUNT;}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
|
||||
@c_file @table_gen
|
||||
{
|
||||
`internal String8 *regs_reg_code_string_table_from_architecture(Architecture arch)`;
|
||||
`{`;
|
||||
`String8 *result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_ArchTable a) `case Architecture_$(a.name_lower):{result = regs_g_reg_code_$(a.name_lower)_string_table;}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
|
||||
@c_file @table_gen
|
||||
{
|
||||
`internal String8 *regs_alias_code_string_table_from_architecture(Architecture arch)`;
|
||||
`{`;
|
||||
`String8 *result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_ArchTable a) `case Architecture_$(a.name_lower):{result = regs_g_alias_code_$(a.name_lower)_string_table;}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
|
||||
@c_file @table_gen
|
||||
{
|
||||
`internal REGS_Rng *regs_reg_code_rng_table_from_architecture(Architecture arch)`;
|
||||
`{`;
|
||||
`REGS_Rng *result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_ArchTable a) `case Architecture_$(a.name_lower):{result = regs_g_reg_code_$(a.name_lower)_rng_table;}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
|
||||
@c_file @table_gen
|
||||
{
|
||||
`internal REGS_Slice *regs_alias_code_slice_table_from_architecture(Architecture arch)`;
|
||||
`{`;
|
||||
`REGS_Slice *result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_ArchTable a) `case Architecture_$(a.name_lower):{result = regs_g_alias_code_$(a.name_lower)_slice_table;}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
|
||||
@c_file @table_gen
|
||||
{
|
||||
`internal REGS_UsageKind *regs_reg_code_usage_kind_table_from_architecture(Architecture arch)`;
|
||||
`{`;
|
||||
`REGS_UsageKind *result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_ArchTable a) `case Architecture_$(a.name_lower):{result = regs_g_reg_code_$(a.name_lower)_usage_kind_table;}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
|
||||
@c_file @table_gen
|
||||
{
|
||||
`internal REGS_UsageKind *regs_alias_code_usage_kind_table_from_architecture(Architecture arch)`;
|
||||
`{`;
|
||||
`REGS_UsageKind *result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_ArchTable a) `case Architecture_$(a.name_lower):{result = regs_g_alias_code_$(a.name_lower)_usage_kind_table;}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
Reference in New Issue
Block a user