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first pass at setting up x64 debug registers for data breakpoints

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This commit is contained in:
Ryan Fleury
2025-04-11 17:49:16 -07:00
parent e621d13669
commit 929e68d074
5 changed files with 187 additions and 44 deletions
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src/regs/generated/regs.meta.c
+8 -8
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@@ -536,14 +536,14 @@ REGS_Rng regs_g_reg_code_x64_rng_table[101] =
{(U16)OffsetOf(REGS_RegBlockX64, gsbase), 8},
{(U16)OffsetOf(REGS_RegBlockX64, rip), 8},
{(U16)OffsetOf(REGS_RegBlockX64, rflags), 8},
{(U16)OffsetOf(REGS_RegBlockX64, dr0), 4},
{(U16)OffsetOf(REGS_RegBlockX64, dr1), 4},
{(U16)OffsetOf(REGS_RegBlockX64, dr2), 4},
{(U16)OffsetOf(REGS_RegBlockX64, dr3), 4},
{(U16)OffsetOf(REGS_RegBlockX64, dr4), 4},
{(U16)OffsetOf(REGS_RegBlockX64, dr5), 4},
{(U16)OffsetOf(REGS_RegBlockX64, dr6), 4},
{(U16)OffsetOf(REGS_RegBlockX64, dr7), 4},
{(U16)OffsetOf(REGS_RegBlockX64, dr0), 8},
{(U16)OffsetOf(REGS_RegBlockX64, dr1), 8},
{(U16)OffsetOf(REGS_RegBlockX64, dr2), 8},
{(U16)OffsetOf(REGS_RegBlockX64, dr3), 8},
{(U16)OffsetOf(REGS_RegBlockX64, dr4), 8},
{(U16)OffsetOf(REGS_RegBlockX64, dr5), 8},
{(U16)OffsetOf(REGS_RegBlockX64, dr6), 8},
{(U16)OffsetOf(REGS_RegBlockX64, dr7), 8},
{(U16)OffsetOf(REGS_RegBlockX64, fpr0), 10},
{(U16)OffsetOf(REGS_RegBlockX64, fpr1), 10},
{(U16)OffsetOf(REGS_RegBlockX64, fpr2), 10},
src/regs/generated/regs.meta.h
+8 -8
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@@ -343,14 +343,14 @@ REGS_Reg64 fsbase;
REGS_Reg64 gsbase;
REGS_Reg64 rip;
REGS_Reg64 rflags;
REGS_Reg32 dr0;
REGS_Reg32 dr1;
REGS_Reg32 dr2;
REGS_Reg32 dr3;
REGS_Reg32 dr4;
REGS_Reg32 dr5;
REGS_Reg32 dr6;
REGS_Reg32 dr7;
REGS_Reg64 dr0;
REGS_Reg64 dr1;
REGS_Reg64 dr2;
REGS_Reg64 dr3;
REGS_Reg64 dr4;
REGS_Reg64 dr5;
REGS_Reg64 dr6;
REGS_Reg64 dr7;
REGS_Reg80 fpr0;
REGS_Reg80 fpr1;
REGS_Reg80 fpr2;
src/regs/regs.mdesk
+8 -8
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@@ -27,14 +27,14 @@ REGS_RegTableX64:
{gsbase 64 Normal}
{rip 64 Normal}
{rflags 64 Normal}
{dr0 32 Normal}
{dr1 32 Normal}
{dr2 32 Normal}
{dr3 32 Normal}
{dr4 32 Normal}
{dr5 32 Normal}
{dr6 32 Normal}
{dr7 32 Normal}
{dr0 64 Normal}
{dr1 64 Normal}
{dr2 64 Normal}
{dr3 64 Normal}
{dr4 64 Normal}
{dr5 64 Normal}
{dr6 64 Normal}
{dr7 64 Normal}
{fpr0 80 Normal}
{fpr1 80 Normal}
{fpr2 80 Normal}