mirror of
https://github.com/Ed94/raddebugger.git
synced 2026-07-31 19:30:03 +00:00
switched to using base Arch enum for converting DWARF registers,
simplified top level building path
This commit is contained in:
+10
-10
@@ -2,7 +2,7 @@
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// Licensed under the MIT license (https://opensource.org/license/mit/)
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internal U64
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dw_reg_size_from_code_x86(U64 reg_code)
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dw_reg_size_from_code_x86(DW_Reg reg_code)
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{
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switch (reg_code) {
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#define X(reg_name_dw, reg_code_dw, reg_name_rdi, reg_pos, reg_size) case DW_RegX86_##reg_name_dw: return reg_size;
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@@ -13,7 +13,7 @@ dw_reg_size_from_code_x86(U64 reg_code)
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}
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internal U64
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dw_reg_pos_from_code_x86(U64 reg_code)
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dw_reg_pos_from_code_x86(DW_Reg reg_code)
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{
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switch (reg_code) {
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#define X(reg_name_dw, reg_code_dw, reg_name_rdi, reg_pos, reg_size) case DW_RegX86_##reg_name_dw: return reg_pos;
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@@ -24,7 +24,7 @@ dw_reg_pos_from_code_x86(U64 reg_code)
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}
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internal U64
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dw_reg_size_from_code_x64(U64 reg_code)
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dw_reg_size_from_code_x64(DW_Reg reg_code)
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{
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switch (reg_code) {
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#define X(reg_name_dw, reg_code_dw, reg_name_rdi, reg_pos, reg_size) case DW_RegX64_##reg_name_dw: return reg_size;
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@@ -35,7 +35,7 @@ dw_reg_size_from_code_x64(U64 reg_code)
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}
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internal U64
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dw_reg_pos_from_code_x64(U64 reg_code)
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dw_reg_pos_from_code_x64(DW_Reg reg_code)
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{
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switch (reg_code) {
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#define X(reg_name_dw, reg_code_dw, reg_name_rdi, reg_pos, reg_size) case DW_RegX64_##reg_name_dw: return reg_pos;
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@@ -46,21 +46,21 @@ dw_reg_pos_from_code_x64(U64 reg_code)
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}
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internal U64
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dw_reg_size_from_code(RDI_Arch arch, U64 reg_code)
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dw_reg_size_from_code(RDI_Arch arch, DW_Reg reg_code)
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{
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switch (arch) {
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case RDI_Arch_X86: return dw_reg_size_from_code_x86(reg_code);
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case RDI_Arch_X64: return dw_reg_size_from_code_x64(reg_code);
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case Arch_x86: return dw_reg_size_from_code_x86(reg_code);
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case Arch_x64: return dw_reg_size_from_code_x64(reg_code);
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}
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return 0;
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}
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internal U64
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dw_reg_pos_from_code(RDI_Arch arch, U64 reg_code)
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dw_reg_pos_from_code(RDI_Arch arch, DW_Reg reg_code)
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{
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switch (arch) {
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case RDI_Arch_X86: return dw_reg_pos_from_code_x86(reg_code);
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case RDI_Arch_X64: return dw_reg_pos_from_code_x64(reg_code);
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case Arch_x86: return dw_reg_pos_from_code_x86(reg_code);
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case Arch_x64: return dw_reg_pos_from_code_x64(reg_code);
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}
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return max_U64;
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}
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+6
-6
@@ -1734,12 +1734,12 @@ typedef enum DW_RegX64Enum
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////////////////////////////////
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internal U64 dw_reg_size_from_code_x86(U64 reg_code);
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internal U64 dw_reg_pos_from_code_x86(U64 reg_code);
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internal U64 dw_reg_size_from_code_x64(U64 reg_code);
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internal U64 dw_reg_pos_from_code_x64(U64 reg_code);
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internal U64 dw_reg_size_from_code(Arch arch, U64 reg_code);
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internal U64 dw_reg_pos_from_code(Arch arch, U64 reg_code);
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internal U64 dw_reg_size_from_code_x86(DW_Reg reg_code);
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internal U64 dw_reg_pos_from_code_x86(DW_Reg reg_code);
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internal U64 dw_reg_size_from_code_x64(DW_Reg reg_code);
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internal U64 dw_reg_pos_from_code_x64(DW_Reg reg_code);
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internal U64 dw_reg_size_from_code(Arch arch, DW_Reg reg_code);
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internal U64 dw_reg_pos_from_code(Arch arch, DW_Reg reg_code);
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//- Attrib Class Encodings
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