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https://github.com/Ed94/raddebugger.git
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handle DW_Op_FBReg, DW_ExprOp_Deref, DW_ExprOp_BReg*, and DW_ExprOp_BRegX
This commit is contained in:
+2
-2
@@ -1675,8 +1675,8 @@ typedef enum DW_ExprOpEnum
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X(Ds, 53, ds, 0, 2) \
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X(Fs, 54, fs, 0, 2) \
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X(Gs, 55, gs, 0, 2) \
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X(FsBase, 58, fsbase, 0, 0) \
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X(GsBase, 59, gsbase, 0, 0)
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X(FsBase, 58, fsbase, 0, 8) \
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X(GsBase, 59, gsbase, 0, 8)
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// privileged registers:
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// X(Tr, 62, nil, 0, 0) \
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// X(Ldtr, 63, nil, 0, 0)
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+72
-2
@@ -1128,7 +1128,17 @@ dw_expr_inst_from_delta(DW_ExprInst *inst, S16 delta)
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}
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internal DW_ExprEvalResult
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dw_eval_expr(Arena *arena, Arch arch, DW_Format format, U64 cfa, U64 tls, U64 exec_op_limit, DW_Expr expr, MachineOp_RegRead *reg_read, void *reg_read_ud, DW_ExprValue *value_out)
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dw_eval_expr(Arena *arena,
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Arch arch,
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DW_Format format,
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U64 frame_base,
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U64 cfa,
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U64 tls,
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U64 exec_op_limit,
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DW_Expr expr,
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MachineOp_RegRead *reg_read, void *reg_read_ud,
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MachineOp_MemRead *mem_read, void *mem_read_ud,
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DW_ExprValue *value_out)
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{
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Temp scratch = scratch_begin(&arena, 1);
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@@ -1201,6 +1211,29 @@ dw_eval_expr(Arena *arena, Arch arch, DW_Format format, U64 cfa, U64 tls, U64 ex
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dw_expr_stack_push_unsigned(scratch.arena, stack, reg_value, reg_size);
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} break;
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case DW_ExprOp_BReg0: case DW_ExprOp_BReg1: case DW_ExprOp_BReg2:
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case DW_ExprOp_BReg3: case DW_ExprOp_BReg4: case DW_ExprOp_BReg5:
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case DW_ExprOp_BReg6: case DW_ExprOp_BReg7: case DW_ExprOp_BReg8:
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case DW_ExprOp_BReg9: case DW_ExprOp_BReg10: case DW_ExprOp_BReg11:
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case DW_ExprOp_BReg12: case DW_ExprOp_BReg13: case DW_ExprOp_BReg14:
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case DW_ExprOp_BReg15: case DW_ExprOp_BReg16: case DW_ExprOp_BReg17:
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case DW_ExprOp_BReg18: case DW_ExprOp_BReg19: case DW_ExprOp_BReg20:
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case DW_ExprOp_BReg21: case DW_ExprOp_BReg22: case DW_ExprOp_BReg23:
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case DW_ExprOp_BReg24: case DW_ExprOp_BReg25: case DW_ExprOp_BReg26:
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case DW_ExprOp_BReg27: case DW_ExprOp_BReg28: case DW_ExprOp_BReg29:
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case DW_ExprOp_BReg30: case DW_ExprOp_BReg31: {
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DW_Reg reg_id = inst->opcode - DW_ExprOp_BReg0;
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U64 reg_size = dw_reg_size_from_code(arch, reg_id);
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AssertAlways(reg_size <= byte_size_from_arch(arch));
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U64 reg_value;
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MachineOpResult reg_read_result = reg_read(reg_id, ®_value, reg_size, reg_read_ud);
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if (reg_read_result != MachineOpResult_Ok) { goto exit; }
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U64 addr = (U64)((S64)reg_value + inst->operands[0].s64);
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dw_expr_stack_push(scratch.arena, stack, (DW_ExprValue){ .type = DW_ExprValueType_Addr, .addr = addr});
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} break;
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case DW_ExprOp_RegX: {
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U64 reg_size = dw_reg_size_from_code(arch, inst->operands[0].u64);
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U8 *reg_value = push_array(scratch.arena, U8, reg_size);
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@@ -1209,6 +1242,24 @@ dw_eval_expr(Arena *arena, Arch arch, DW_Format format, U64 cfa, U64 tls, U64 ex
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dw_expr_stack_push_unsigned(scratch.arena, stack, reg_value, reg_size);
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} break;
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case DW_ExprOp_BRegX: {
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DW_Reg reg_id = (DW_Reg)inst->operands[0].u64;
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U64 reg_size = dw_reg_size_from_code(arch, reg_id);
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AssertAlways(reg_size <= byte_size_from_arch(arch));
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U64 reg_value;
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MachineOpResult reg_read_result = reg_read(reg_id, ®_value, reg_size, reg_read_ud);
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if (reg_read_result != MachineOpResult_Ok) { goto exit; }
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U64 addr = (U64)((S64)reg_value + inst->operands[1].s64);
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dw_expr_stack_push(scratch.arena, stack, (DW_ExprValue){ .type = DW_ExprValueType_Addr, .addr = addr});
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} break;
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case DW_ExprOp_FBReg: {
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U64 addr = frame_base + inst->operands[0].s64;
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dw_expr_stack_push(scratch.arena, stack, (DW_ExprValue){ .type = DW_ExprValueType_Addr, .addr = addr});
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} break;
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case DW_ExprOp_ImplicitValue: {
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if (inst->operands[0].block.size <= sizeof(U512)) {
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dw_expr_stack_push_unsigned(scratch.arena, stack, inst->operands[0].block.str, inst->operands[0].block.size);
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@@ -1340,7 +1391,7 @@ dw_eval_expr(Arena *arena, Arch arch, DW_Format format, U64 cfa, U64 tls, U64 ex
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case DW_ExprOp_GNU_EntryValue: {
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DW_Expr entry_value_expr = dw_expr_from_data(scratch.arena, format, byte_size_from_arch(arch), inst->operands[0].block);
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DW_ExprValue entry_value;
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result = dw_eval_expr(scratch.arena, arch, format, cfa, tls, exec_op_limit, entry_value_expr, reg_read, reg_read_ud, &entry_value);
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result = dw_eval_expr(scratch.arena, arch, format, frame_base, cfa, tls, exec_op_limit, entry_value_expr, reg_read, reg_read_ud, mem_read, mem_read_ud, &entry_value);
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if (result != DW_ExprEvalResult_Ok) { goto exit; }
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dw_expr_stack_push(scratch.arena, stack, entry_value);
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} break;
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@@ -1401,6 +1452,25 @@ dw_eval_expr(Arena *arena, Arch arch, DW_Format format, U64 cfa, U64 tls, U64 ex
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dw_expr_stack_pop(stack);
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} break;
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case DW_ExprOp_Deref: {
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DW_ExprValue value = dw_expr_stack_pop(stack);
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// expression must be of an integral type
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if (!DW_ExprValueType_IsInt(value.type)) { goto exit; }
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// treat value as an address
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DW_ExprValue addr = dw_expr_cast(value, DW_ExprValueType_Addr);
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// read pointer size from the address
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U64 addr_size = byte_size_from_arch(arch);
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U8 *generic_value = push_array(scratch.arena, U8, addr_size);
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MachineOpResult read_result = mem_read(addr.addr, generic_value, addr_size, mem_read_ud);
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if (read_result != MachineOpResult_Ok) { goto exit; }
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// push generic data
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dw_expr_stack_push(scratch.arena, stack, (DW_ExprValue){ .type = DW_ExprValueType_Generic, .generic = str8(generic_value, addr_size) });
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} break;
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case DW_ExprOp_StackValue: {
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stack->top->v.type = dw_expr_unsigned_value_type_from_bit_size(bit_size_from_arch(arch));
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} break;
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@@ -235,7 +235,7 @@ internal DW_ExprValueNode * dw_expr_stack_pick(DW_ExprStack *stack, U64 idx);
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internal String8 dw_string_from_expr_value(Arena *arena, U64 addr_size, DW_ExprValue v);
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// evaluator
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internal DW_ExprEvalResult dw_eval_expr(Arena *arena, Arch arch, DW_Format format, U64 cfa, U64 tls_base, U64 op_limit, DW_Expr expr, MachineOp_RegRead *reg_read, void *reg_read_ud, DW_ExprValue *value_out);
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internal DW_ExprEvalResult dw_eval_expr(Arena *arena, Arch arch, DW_Format format, U64 frame_base, U64 cfa, U64 tls_base, U64 op_limit, DW_Expr expr, MachineOp_RegRead *reg_read, void *reg_read_ud, MachineOp_MemRead *mem_read, void *mem_read_ud, DW_ExprValue *value_out);
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// encoder
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internal String8 dw_encode_expr(Arena *arena, Arch arch, DW_Format format, DW_ExprEnc *encs, U64 encs_count);
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