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https://github.com/Ed94/raddebugger.git
synced 2026-08-14 17:28:07 +00:00
d2r2: fix line table register reset conditions in line table conversion
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@@ -922,10 +922,6 @@ d2r2_convert(Arena *arena, D2R2_ConvertParams *params)
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vm_regs.address += addr_advance;
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vm_regs.address += addr_advance;
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vm_regs.vliw_op_index = (vm_regs.vliw_op_index + op_advance) % line_table_header->max_ops_per_inst;
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vm_regs.vliw_op_index = (vm_regs.vliw_op_index + op_advance) % line_table_header->max_ops_per_inst;
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vm_regs.line += line_advance;
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vm_regs.line += line_advance;
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vm_regs.basic_block = 0;
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vm_regs.prologue_end = 0;
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vm_regs.epilogue_begin = 0;
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vm_regs.discriminator = 0;
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emit_line = 1;
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emit_line = 1;
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}
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}
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@@ -949,10 +945,6 @@ d2r2_convert(Arena *arena, D2R2_ConvertParams *params)
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case DW_StdOpcode_Copy:
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case DW_StdOpcode_Copy:
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{
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{
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emit_line = 1;
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emit_line = 1;
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vm_regs.discriminator = 0;
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vm_regs.basic_block = 0;
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vm_regs.prologue_end = 0;
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vm_regs.epilogue_begin = 0;
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}break;
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}break;
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//- rjf: PC advances
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//- rjf: PC advances
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@@ -1159,11 +1151,14 @@ d2r2_convert(Arena *arena, D2R2_ConvertParams *params)
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first_line_seq_chunk = last_line_seq_chunk = 0;
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first_line_seq_chunk = last_line_seq_chunk = 0;
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total_line_seq_count = 0;
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total_line_seq_count = 0;
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line_seq_src_file = 0;
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line_seq_src_file = 0;
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if(vm_regs.end_sequence)
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{
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MemoryZeroStruct(&vm_regs);
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MemoryZeroStruct(&vm_regs);
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vm_regs.file_index = 1;
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vm_regs.file_index = 1;
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vm_regs.line = 1;
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vm_regs.line = 1;
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vm_regs.is_stmt = line_table_header->default_is_stmt;
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vm_regs.is_stmt = line_table_header->default_is_stmt;
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}
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}
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}
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//- rjf: emit lines
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//- rjf: emit lines
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if(emit_line && vm_regs.address != 0 && vm_regs.line != 0)
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if(emit_line && vm_regs.address != 0 && vm_regs.line != 0)
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@@ -1186,6 +1181,23 @@ d2r2_convert(Arena *arena, D2R2_ConvertParams *params)
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chunk->line_count += 1;
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chunk->line_count += 1;
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total_line_seq_count += 1;
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total_line_seq_count += 1;
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line_seq_src_file = src_file;
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line_seq_src_file = src_file;
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// 0x0000000000030b80 141 0 201 0 0 0 is_stmt
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printf("0x%016I64x %6i %6i %6i %3i %13I64x %7i %s%s%s%s\n",
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vm_regs.address,
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(int)vm_regs.line,
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(int)vm_regs.column,
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(int)vm_regs.file_index,
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(int)vm_regs.isa,
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vm_regs.discriminator,
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(int)vm_regs.vliw_op_index,
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vm_regs.is_stmt ? " is_stmt" : "",
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vm_regs.prologue_end ? " prologue_end" : "",
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vm_regs.epilogue_begin ? " epilogue_begin" : "",
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vm_regs.end_sequence ? " end_sequence" : "");
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vm_regs.discriminator = 0;
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vm_regs.basic_block = 0;
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vm_regs.prologue_end = 0;
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vm_regs.epilogue_begin = 0;
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}
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}
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}
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}
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