mirror of
https://github.com/Ed94/raddebugger.git
synced 2026-08-07 06:18:42 +00:00
mc -> mdesk; I do not know what Monkey C is
This commit is contained in:
Ryan Fleury
@@ -0,0 +1,556 @@
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// Copyright (c) 2024 Epic Games Tools
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// Licensed under the MIT license (https://opensource.org/license/mit/)
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////////////////////////////////
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//~ rjf: X64 Tables
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||||
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@table(name size usage)
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REGS_RegTableX64:
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{
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{rax 64 Normal}
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{rcx 64 Normal}
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{rdx 64 Normal}
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{rbx 64 Normal}
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||||
{rsp 64 Normal}
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||||
{rbp 64 Normal}
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{rsi 64 Normal}
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||||
{rdi 64 Normal}
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||||
{r8 64 Normal}
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{r9 64 Normal}
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{r10 64 Normal}
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{r11 64 Normal}
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{r12 64 Normal}
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||||
{r13 64 Normal}
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{r14 64 Normal}
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{r15 64 Normal}
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{fsbase 64 Normal}
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{gsbase 64 Normal}
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{rip 64 Normal}
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{rflags 64 Normal}
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{dr0 32 Normal}
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{dr1 32 Normal}
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{dr2 32 Normal}
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{dr3 32 Normal}
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{dr4 32 Normal}
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{dr5 32 Normal}
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{dr6 32 Normal}
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{dr7 32 Normal}
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{fpr0 80 Normal}
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{fpr1 80 Normal}
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{fpr2 80 Normal}
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{fpr3 80 Normal}
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{fpr4 80 Normal}
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{fpr5 80 Normal}
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{fpr6 80 Normal}
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{fpr7 80 Normal}
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{st0 80 Normal}
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{st1 80 Normal}
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{st2 80 Normal}
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{st3 80 Normal}
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{st4 80 Normal}
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{st5 80 Normal}
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{st6 80 Normal}
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{st7 80 Normal}
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{fcw 16 Normal}
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{fsw 16 Normal}
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{ftw 16 Normal}
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{fop 16 Normal}
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{fcs 16 Normal}
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{fds 16 Normal}
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{fip 32 Normal}
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{fdp 32 Normal}
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{mxcsr 32 Normal}
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{mxcsr_mask 32 Normal}
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{ss 16 Normal}
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{cs 16 Normal}
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{ds 16 Normal}
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{es 16 Normal}
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{fs 16 Normal}
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{gs 16 Normal}
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{ymm0 256 Normal}
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{ymm1 256 Normal}
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{ymm2 256 Normal}
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{ymm3 256 Normal}
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{ymm4 256 Normal}
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{ymm5 256 Normal}
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{ymm6 256 Normal}
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{ymm7 256 Normal}
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{ymm8 256 Normal}
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{ymm9 256 Normal}
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{ymm10 256 Normal}
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{ymm11 256 Normal}
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{ymm12 256 Normal}
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{ymm13 256 Normal}
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{ymm14 256 Normal}
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{ymm15 256 Normal}
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}
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@table(name base off size usage)
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REGS_AliasTableX64:
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{
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{eax rax 0 32 Normal}
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{ecx rcx 0 32 Normal}
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{edx rdx 0 32 Normal}
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{ebx rbx 0 32 Normal}
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{esp rsp 0 32 Normal}
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{ebp rbp 0 32 Normal}
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{esi rsi 0 32 Normal}
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{edi rdi 0 32 Normal}
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{r8d r8 0 32 Normal}
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{r9d r9 0 32 Normal}
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{r10d r10 0 32 Normal}
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{r11d r11 0 32 Normal}
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{r12d r12 0 32 Normal}
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{r13d r13 0 32 Normal}
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{r14d r14 0 32 Normal}
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{r15d r15 0 32 Normal}
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// TODO(allen): figure this one out; visual studio disagrees
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{eip rip 0 32 Normal}
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{eflags rflags 0 32 Normal}
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{ax rax 0 16 Normal}
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{cx rcx 0 16 Normal}
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{dx rdx 0 16 Normal}
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{bx rbx 0 16 Normal}
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{si rsi 0 16 Normal}
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{di rdi 0 16 Normal}
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{sp rsp 0 16 Normal}
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{bp rbp 0 16 Normal}
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{ip rip 0 16 Normal}
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{r8w r8 0 16 Normal}
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{r9w r9 0 16 Normal}
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{r10w r10 0 16 Normal}
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{r11w r11 0 16 Normal}
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{r12w r12 0 16 Normal}
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{r13w r13 0 16 Normal}
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{r14w r14 0 16 Normal}
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{r15w r15 0 16 Normal}
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{al rax 0 8 Normal}
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||||
{cl rcx 0 8 Normal}
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{dl rdx 0 8 Normal}
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{bl rbx 0 8 Normal}
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||||
{sil rsi 0 8 Normal}
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{dil rdi 0 8 Normal}
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||||
{bpl rbp 0 8 Normal}
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||||
{spl rsp 0 8 Normal}
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{r8b r8 0 8 Normal}
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{r9b r9 0 8 Normal}
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{r10b r10 0 8 Normal}
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{r11b r11 0 8 Normal}
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{r12b r12 0 8 Normal}
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{r13b r13 0 8 Normal}
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{r14b r14 0 8 Normal}
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{r15b r15 0 8 Normal}
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{ah rax 8 8 Normal}
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{ch rcx 8 8 Normal}
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{dh rdx 8 8 Normal}
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{bh rbx 8 8 Normal}
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{xmm0 ymm0 0 128 Normal}
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{xmm1 ymm1 0 128 Normal}
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{xmm2 ymm2 0 128 Normal}
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{xmm3 ymm3 0 128 Normal}
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{xmm4 ymm4 0 128 Normal}
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{xmm5 ymm5 0 128 Normal}
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{xmm6 ymm6 0 128 Normal}
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{xmm7 ymm7 0 128 Normal}
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{xmm8 ymm8 0 128 Normal}
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{xmm9 ymm9 0 128 Normal}
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{xmm10 ymm10 0 128 Normal}
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{xmm11 ymm11 0 128 Normal}
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{xmm12 ymm12 0 128 Normal}
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{xmm13 ymm13 0 128 Normal}
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{xmm14 ymm14 0 128 Normal}
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{xmm15 ymm15 0 128 Normal}
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{mm0 fpr0 0 64 Normal}
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{mm1 fpr1 0 64 Normal}
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{mm2 fpr2 0 64 Normal}
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{mm3 fpr3 0 64 Normal}
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{mm4 fpr4 0 64 Normal}
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{mm5 fpr5 0 64 Normal}
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{mm6 fpr6 0 64 Normal}
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{mm7 fpr7 0 64 Normal}
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||||
}
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////////////////////////////////
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//~ rjf: X86 Tables
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||||
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@table(name size usage)
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||||
REGS_RegTableX86:
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{
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{eax 32 Normal}
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{ecx 32 Normal}
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{edx 32 Normal}
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{ebx 32 Normal}
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{esp 32 Normal}
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||||
{ebp 32 Normal}
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||||
{esi 32 Normal}
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||||
{edi 32 Normal}
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||||
{fsbase 32 Normal}
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||||
{gsbase 32 Normal}
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||||
{eflags 32 Normal}
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{eip 32 Normal}
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{dr0 32 Normal}
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{dr1 32 Normal}
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||||
{dr2 32 Normal}
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||||
{dr3 32 Normal}
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||||
{dr4 32 Normal}
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||||
{dr5 32 Normal}
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{dr6 32 Normal}
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{dr7 32 Normal}
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||||
// FSave registers
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// TODO(allen): I am suspicious of this stuff here.
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// Are fpr0-7 and st0-7 actually different things? Visual studio doesn't show
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// frp0-7. Not sure if the mm0-7 aliases are setup the right way either.
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{fpr0 80 Normal}
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{fpr1 80 Normal}
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{fpr2 80 Normal}
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{fpr3 80 Normal}
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||||
{fpr4 80 Normal}
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||||
{fpr5 80 Normal}
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{fpr6 80 Normal}
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||||
{fpr7 80 Normal}
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{st0 80 Normal}
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||||
{st1 80 Normal}
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||||
{st2 80 Normal}
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||||
{st3 80 Normal}
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||||
{st4 80 Normal}
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||||
{st5 80 Normal}
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{st6 80 Normal}
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||||
{st7 80 Normal}
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||||
{fcw 16 Normal}
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||||
{fsw 16 Normal}
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||||
{ftw 16 Normal}
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||||
{fop 16 Normal}
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||||
{fcs 16 Normal}
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||||
{fds 16 Normal}
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||||
{fip 32 Normal}
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{fdp 32 Normal}
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{mxcsr 32 Normal}
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// TODO(allen): I don't think this is really a "register" - think about this...
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{mxcsr_mask 32 Normal}
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{ss 16 Normal}
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{cs 16 Normal}
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{ds 16 Normal}
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{es 16 Normal}
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{fs 16 Normal}
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{gs 16 Normal}
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// SIMD REGISTERS
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{ymm0 256 Normal}
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{ymm1 256 Normal}
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{ymm2 256 Normal}
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{ymm3 256 Normal}
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{ymm4 256 Normal}
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{ymm5 256 Normal}
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{ymm6 256 Normal}
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{ymm7 256 Normal}
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}
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@table(name base off size usage)
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||||
REGS_AliasTableX86:
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{
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{ax eax 0 16 Normal}
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{cx ecx 0 16 Normal}
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{bx ebx 0 16 Normal}
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||||
{dx edx 0 16 Normal}
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{sp esp 0 16 Normal}
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{bp ebp 0 16 Normal}
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||||
{si esi 0 16 Normal}
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||||
{di edi 0 16 Normal}
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{ip eip 0 16 Normal}
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{ah eax 8 8 Normal}
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{ch ecx 8 8 Normal}
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{dh edx 8 8 Normal}
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{bh ebx 8 8 Normal}
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||||
{al eax 0 8 Normal}
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||||
{cl ecx 0 8 Normal}
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{dl edx 0 8 Normal}
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{bl ebx 0 8 Normal}
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||||
{bpl ebp 0 8 Normal}
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{spl esp 0 8 Normal}
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||||
{xmm0 ymm0 0 128 Normal}
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||||
{xmm1 ymm1 0 128 Normal}
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{xmm2 ymm2 0 128 Normal}
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||||
{xmm3 ymm3 0 128 Normal}
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{xmm4 ymm4 0 128 Normal}
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{xmm5 ymm5 0 128 Normal}
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{xmm6 ymm6 0 128 Normal}
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{xmm7 ymm7 0 128 Normal}
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{mm0 fpr0 0 64 Normal}
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{mm1 fpr1 0 64 Normal}
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{mm2 fpr2 0 64 Normal}
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{mm3 fpr3 0 64 Normal}
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{mm4 fpr4 0 64 Normal}
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{mm5 fpr5 0 64 Normal}
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{mm6 fpr6 0 64 Normal}
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{mm7 fpr7 0 64 Normal}
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}
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////////////////////////////////
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//~ rjf: Architecture Tables
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@table(name, name_lower)
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REGS_ArchTable:
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{
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{X64 x64}
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{X86 x86}
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}
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////////////////////////////////
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//~ rjf: X64 Generators
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@table_gen_enum REGS_RegCodeX64:
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{
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`REGS_RegCodeX64_NULL,`;
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@expand(REGS_RegTableX64 a) `REGS_RegCodeX64_$(a.name),`;
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`REGS_RegCodeX64_COUNT`;
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}
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@table_gen_enum REGS_AliasCodeX64:
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{
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`REGS_AliasCodeX64_NULL,`;
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@expand(REGS_AliasTableX64 a) `REGS_AliasCodeX64_$(a.name),`;
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`REGS_AliasCodeX64_COUNT`;
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}
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@table_gen_struct
|
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REGS_RegBlockX64:
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{
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||||
@expand(REGS_RegTableX64 a) `REGS_Reg$(a.size) $(a.name);`;
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}
|
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|
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@table_gen_data(type:REGS_UsageKind, fallback:`REGS_UsageKind_Normal`)
|
||||
regs_g_reg_code_x64_usage_kind_table:
|
||||
{
|
||||
`REGS_UsageKind_Normal,`;
|
||||
@expand(REGS_RegTableX64 a) `REGS_UsageKind_$(a.usage),`;
|
||||
}
|
||||
|
||||
@table_gen_data(type:REGS_UsageKind, fallback:`REGS_UsageKind_Normal`)
|
||||
regs_g_alias_code_x64_usage_kind_table:
|
||||
{
|
||||
`REGS_UsageKind_Normal,`;
|
||||
@expand(REGS_AliasTableX64 a) `REGS_UsageKind_$(a.usage),`;
|
||||
}
|
||||
|
||||
@table_gen_data(type:String8, fallback:`{0}`)
|
||||
regs_g_reg_code_x64_string_table:
|
||||
{
|
||||
`str8_lit_comp(""),`;
|
||||
@expand(REGS_RegTableX64 a) `str8_lit_comp("$(a.name)"),`;
|
||||
}
|
||||
|
||||
@table_gen_data(type:String8, fallback:`{0}`)
|
||||
regs_g_alias_code_x64_string_table:
|
||||
{
|
||||
`str8_lit_comp(""),`;
|
||||
@expand(REGS_AliasTableX64 a) `str8_lit_comp("$(a.name)"),`;
|
||||
}
|
||||
|
||||
@table_gen_data(type: REGS_Rng, fallback: `{0}`)
|
||||
regs_g_reg_code_x64_rng_table:
|
||||
{
|
||||
`{0},`;
|
||||
@expand(REGS_RegTableX64 a) `{(U16)OffsetOf(REGS_RegBlockX64, $(a.name)), $(a.size/8)},`,
|
||||
}
|
||||
|
||||
@table_gen_data(type: REGS_Slice, fallback: `{0}`)
|
||||
regs_g_alias_code_x64_slice_table:
|
||||
{
|
||||
`{0},`;
|
||||
@expand(REGS_AliasTableX64 a) `{REGS_RegCodeX64_$(a.base), $(a.off/8), $(a.size/8)},`,
|
||||
}
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: X86 Generators
|
||||
|
||||
@table_gen_enum REGS_RegCodeX86:
|
||||
{
|
||||
`REGS_RegCodeX86_NULL,`;
|
||||
@expand(REGS_RegTableX86 a) `REGS_RegCodeX86_$(a.name),`;
|
||||
`REGS_RegCodeX86_COUNT`;
|
||||
}
|
||||
|
||||
@table_gen_enum REGS_AliasCodeX86:
|
||||
{
|
||||
`REGS_AliasCodeX86_NULL,`;
|
||||
@expand(REGS_AliasTableX86 a) `REGS_AliasCodeX86_$(a.name),`;
|
||||
`REGS_AliasCodeX86_COUNT`;
|
||||
}
|
||||
|
||||
@table_gen_struct
|
||||
REGS_RegBlockX86:
|
||||
{
|
||||
@expand(REGS_RegTableX86 a) `REGS_Reg$(a.size) $(a.name);`;
|
||||
}
|
||||
|
||||
@table_gen_data(type:REGS_UsageKind, fallback:`REGS_UsageKind_Normal`)
|
||||
regs_g_reg_code_x86_usage_kind_table:
|
||||
{
|
||||
`REGS_UsageKind_Normal,`;
|
||||
@expand(REGS_RegTableX86 a) `REGS_UsageKind_$(a.usage),`;
|
||||
}
|
||||
|
||||
@table_gen_data(type:REGS_UsageKind, fallback:`REGS_UsageKind_Normal`)
|
||||
regs_g_alias_code_x86_usage_kind_table:
|
||||
{
|
||||
`REGS_UsageKind_Normal,`;
|
||||
@expand(REGS_AliasTableX86 a) `REGS_UsageKind_$(a.usage),`;
|
||||
}
|
||||
|
||||
@table_gen_data(type:String8, fallback:`{0}`)
|
||||
regs_g_reg_code_x86_string_table:
|
||||
{
|
||||
`str8_lit_comp(""),`;
|
||||
@expand(REGS_RegTableX86 a) `str8_lit_comp("$(a.name)"),`;
|
||||
}
|
||||
|
||||
@table_gen_data(type:String8, fallback:`{0}`)
|
||||
regs_g_alias_code_x86_string_table:
|
||||
{
|
||||
`str8_lit_comp(""),`;
|
||||
@expand(REGS_AliasTableX86 a) `str8_lit_comp("$(a.name)"),`;
|
||||
}
|
||||
|
||||
@table_gen_data(type: REGS_Rng, fallback: `{0}`)
|
||||
regs_g_reg_code_x86_rng_table:
|
||||
{
|
||||
`{0},`;
|
||||
@expand(REGS_RegTableX86 a) `{(U16)OffsetOf(REGS_RegBlockX86, $(a.name)), $(a.size/8)},`,
|
||||
}
|
||||
|
||||
@table_gen_data(type: REGS_Slice, fallback: `{0}`)
|
||||
regs_g_alias_code_x86_slice_table:
|
||||
{
|
||||
`{0},`;
|
||||
@expand(REGS_AliasTableX86 a) `{REGS_RegCodeX86_$(a.base), $(a.off/8), $(a.size/8)},`,
|
||||
}
|
||||
|
||||
////////////////////////////////
|
||||
//~ rjf: Architecture-Dynamic Helper Implementation Generators
|
||||
|
||||
@c_file @table_gen
|
||||
{
|
||||
`internal U64 regs_block_size_from_architecture(Architecture arch)`;
|
||||
`{`;
|
||||
`U64 result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_ArchTable a) `case Architecture_$(a.name_lower):{result = sizeof(REGS_RegBlock$(a.name));}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
|
||||
@c_file @table_gen
|
||||
{
|
||||
`internal U64 regs_reg_code_count_from_architecture(Architecture arch)`;
|
||||
`{`;
|
||||
`U64 result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_ArchTable a) `case Architecture_$(a.name_lower):{result = REGS_RegCode$(a.name)_COUNT;}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
|
||||
@c_file @table_gen
|
||||
{
|
||||
`internal U64 regs_alias_code_count_from_architecture(Architecture arch)`;
|
||||
`{`;
|
||||
`U64 result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_ArchTable a) `case Architecture_$(a.name_lower):{result = REGS_AliasCode$(a.name)_COUNT;}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
|
||||
@c_file @table_gen
|
||||
{
|
||||
`internal String8 *regs_reg_code_string_table_from_architecture(Architecture arch)`;
|
||||
`{`;
|
||||
`String8 *result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_ArchTable a) `case Architecture_$(a.name_lower):{result = regs_g_reg_code_$(a.name_lower)_string_table;}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
|
||||
@c_file @table_gen
|
||||
{
|
||||
`internal String8 *regs_alias_code_string_table_from_architecture(Architecture arch)`;
|
||||
`{`;
|
||||
`String8 *result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_ArchTable a) `case Architecture_$(a.name_lower):{result = regs_g_alias_code_$(a.name_lower)_string_table;}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
|
||||
@c_file @table_gen
|
||||
{
|
||||
`internal REGS_Rng *regs_reg_code_rng_table_from_architecture(Architecture arch)`;
|
||||
`{`;
|
||||
`REGS_Rng *result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_ArchTable a) `case Architecture_$(a.name_lower):{result = regs_g_reg_code_$(a.name_lower)_rng_table;}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
|
||||
@c_file @table_gen
|
||||
{
|
||||
`internal REGS_Slice *regs_alias_code_slice_table_from_architecture(Architecture arch)`;
|
||||
`{`;
|
||||
`REGS_Slice *result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_ArchTable a) `case Architecture_$(a.name_lower):{result = regs_g_alias_code_$(a.name_lower)_slice_table;}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
|
||||
@c_file @table_gen
|
||||
{
|
||||
`internal REGS_UsageKind *regs_reg_code_usage_kind_table_from_architecture(Architecture arch)`;
|
||||
`{`;
|
||||
`REGS_UsageKind *result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_ArchTable a) `case Architecture_$(a.name_lower):{result = regs_g_reg_code_$(a.name_lower)_usage_kind_table;}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
|
||||
@c_file @table_gen
|
||||
{
|
||||
`internal REGS_UsageKind *regs_alias_code_usage_kind_table_from_architecture(Architecture arch)`;
|
||||
`{`;
|
||||
`REGS_UsageKind *result = 0;`;
|
||||
`switch(arch)`;
|
||||
`{`;
|
||||
`default:{}break;`;
|
||||
@expand(REGS_ArchTable a) `case Architecture_$(a.name_lower):{result = regs_g_alias_code_$(a.name_lower)_usage_kind_table;}break;`;
|
||||
`}`;
|
||||
`return result;`;
|
||||
`}`;
|
||||
}
|
||||
Reference in New Issue
Block a user