From 18237a14648c9ece09dc36ad7f7ef59bbdf0debe Mon Sep 17 00:00:00 2001 From: Ryan Fleury Date: Wed, 7 Aug 2024 16:48:20 -0700 Subject: [PATCH] eliminate old architecture info tables --- src/df/core/df_core.c | 53 -- src/df/core/df_core.h | 25 - src/df/core/df_core.mdesk | 1097 -------------------------- src/df/core/generated/df_core.meta.h | 1073 ------------------------- 4 files changed, 2248 deletions(-) diff --git a/src/df/core/df_core.c b/src/df/core/df_core.c index 6c49d38d..7ca46867 100644 --- a/src/df/core/df_core.c +++ b/src/df/core/df_core.c @@ -5704,43 +5704,6 @@ df_current_path(void) return df_state->current_path; } -//- rjf: architecture info table lookups - -internal String8 -df_info_summary_from_string__x64(String8 string) -{ - String8 result = {0}; - { - U64 hash = df_hash_from_string__case_insensitive(string); - U64 slot_idx = hash % df_state->arch_info_x64_table_size; - DF_ArchInfoSlot *slot = &df_state->arch_info_x64_table[slot_idx]; - for(DF_ArchInfoNode *n = slot->first; n != 0; n = n->hash_next) - { - if(str8_match(n->key, string, StringMatchFlag_CaseInsensitive)) - { - result = n->val; - break; - } - } - } - return result; -} - -internal String8 -df_info_summary_from_string(Architecture arch, String8 string) -{ - String8 result = {0}; - switch(arch) - { - default:{}break; - case Architecture_x64: - { - result = df_info_summary_from_string__x64(string); - }break; - } - return result; -} - //- rjf: entity kind cache internal DF_EntityList @@ -6266,22 +6229,6 @@ df_core_init(CmdLine *cmdln, DF_StateDeltaHistory *hist) df_state->current_path = push_str8_copy(df_state->current_path_arena, current_path_with_slash); scratch_end(scratch); } - - // rjf: set up architecture info tables - df_state->arch_info_x64_table_size = 1024; - df_state->arch_info_x64_table = push_array(df_state->arena, DF_ArchInfoSlot, df_state->arch_info_x64_table_size); - for(U64 idx = 0; idx < ArrayCount(df_g_inst_table_x64); idx += 1) - { - String8 key = df_g_inst_table_x64[idx].mnemonic; - String8 val = df_g_inst_table_x64[idx].summary; - U64 hash = df_hash_from_string__case_insensitive(key); - U64 slot_idx = hash % df_state->arch_info_x64_table_size; - DF_ArchInfoSlot *slot = &df_state->arch_info_x64_table[slot_idx]; - DF_ArchInfoNode *n = push_array(df_state->arena, DF_ArchInfoNode, 1); - SLLQueuePush_N(slot->first, slot->last, n, hash_next); - n->key = key; - n->val = val; - } } internal DF_CmdList diff --git a/src/df/core/df_core.h b/src/df/core/df_core.h index 77fbce9c..72a298bb 100644 --- a/src/df/core/df_core.h +++ b/src/df/core/df_core.h @@ -1086,23 +1086,6 @@ struct DF_StateDeltaHistory //////////////////////////////// //~ rjf: Main State Types -//- rjf: architecture info table types - -typedef struct DF_ArchInfoNode DF_ArchInfoNode; -struct DF_ArchInfoNode -{ - DF_ArchInfoNode *hash_next; - String8 key; - String8 val; -}; - -typedef struct DF_ArchInfoSlot DF_ArchInfoSlot; -struct DF_ArchInfoSlot -{ - DF_ArchInfoNode *first; - DF_ArchInfoNode *last; -}; - //- rjf: name allocator types typedef struct DF_NameChunkNode DF_NameChunkNode; @@ -1225,10 +1208,6 @@ struct DF_State // rjf: current path Arena *current_path_arena; String8 current_path; - - // rjf: architecture info tables - U64 arch_info_x64_table_size; - DF_ArchInfoSlot *arch_info_x64_table; }; //////////////////////////////// @@ -1666,10 +1645,6 @@ internal void df_cfg_push_write_string(DF_CfgSrc src, String8 string); //- rjf: current path internal String8 df_current_path(void); -//- rjf: architecture info table lookups -internal String8 df_info_summary_from_string__x64(String8 string); -internal String8 df_info_summary_from_string(Architecture arch, String8 string); - //- rjf: entity kind cache internal DF_EntityList df_query_cached_entity_list_with_kind(DF_EntityKind kind); diff --git a/src/df/core/df_core.mdesk b/src/df/core/df_core.mdesk index 66f1b508..b8c6ce2b 100644 --- a/src/df/core/df_core.mdesk +++ b/src/df/core/df_core.mdesk @@ -605,1091 +605,6 @@ DF_IconTable: (Dot "c") } -//////////////////////////////// -//~ rjf: X64 Instruction Table - -@table(name summary) -DF_InstTableX64: -{ - - //- rjf: core - {AAA "ASCII Adjust After Addition" } - {AAD "ASCII Adjust AX Before Division" } - {AAM "ASCII Adjust AX After Multiply" } - {AAS "ASCII Adjust AL After Subtraction" } - {ADC "Add with Carry" } - {ADCX "Unsigned Integer Addition of Two Operands with Carry Flag" } - {ADD "Add" } - {ADDPD "Add Packed Double-Precision Floating-Point Values" } - {ADDPS "Add Packed Single-Precision Floating-Point Values" } - {ADDSD "Add Scalar Double-Precision Floating-Point Values" } - {ADDSS "Add Scalar Single-Precision Floating-Point Values" } - {ADDSUBPD "Packed Double-FP Add/Subtract" } - {ADDSUBPS "Packed Single-FP Add/Subtract" } - {ADOX "Unsigned Integer Addition of Two Operands with Overflow Flag" } - {AESDEC "Perform One Round of an AES Decryption Flow" } - {AESDEC128KL "Perform Ten Rounds of AES Decryption Flow with Key Locker Using 128-Bit Key" } - {AESDEC256KL "Perform 14 Rounds of AES Decryption Flow with Key Locker Using 256-Bit Key" } - {AESDECLAST "Perform Last Round of an AES Decryption Flow" } - {AESDECWIDE128KL "Perform Ten Rounds of AES Decryption Flow with Key Locker on 8 Blocks Using 128-Bit Key" } - {AESDECWIDE256KL "Perform 14 Rounds of AES Decryption Flow with Key Locker on 8 Blocks Using 256-Bit Key" } - {AESENC "Perform One Round of an AES Encryption Flow" } - {AESENC128KL "Perform Ten Rounds of AES Encryption Flow with Key Locker Using 128-Bit Key" } - {AESENC256KL "Perform 14 Rounds of AES Encryption Flow with Key Locker Using 256-Bit Key" } - {AESENCLAST "Perform Last Round of an AES Encryption Flow" } - {AESENCWIDE128KL "Perform Ten Rounds of AES Encryption Flow with Key Locker on 8 Blocks Using 128-Bit Key" } - {AESENCWIDE256KL "Perform 14 Rounds of AES Encryption Flow with Key Locker on 8 Blocks Using 256-Bit Key" } - {AESIMC "Perform the AES InvMixColumn Transformation" } - {AESKEYGENASSIST "AES Round Key Generation Assist" } - {AND "Logical AND" } - {ANDN "Logical AND NOT" } - {ANDNPD "Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values" } - {ANDNPS "Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values" } - {ANDPD "Bitwise Logical AND of Packed Double Precision Floating-Point Values" } - {ANDPS "Bitwise Logical AND of Packed Single Precision Floating-Point Values" } - {ARPL "Adjust RPL Field of Segment Selector" } - {BEXTR "Bit Field Extract" } - {BLENDPD "Blend Packed Double Precision Floating-Point Values" } - {BLENDPS "Blend Packed Single Precision Floating-Point Values" } - {BLENDVPD "Variable Blend Packed Double Precision Floating-Point Values" } - {BLENDVPS "Variable Blend Packed Single Precision Floating-Point Values" } - {BLSI "Extract Lowest Set Isolated Bit" } - {BLSMSK "Get Mask Up to Lowest Set Bit" } - {BLSR "Reset Lowest Set Bit" } - {BNDCL "Check Lower Bound" } - {BNDCN "Check Upper Bound" } - {BNDCU "Check Upper Bound" } - {BNDLDX "Load Extended Bounds Using Address Translation" } - {BNDMK "Make Bounds" } - {BNDMOV "Move Bounds" } - {BNDSTX "Store Extended Bounds Using Address Translation" } - {BOUND "Check Array Index Against Bounds" } - {BSF "Bit Scan Forward" } - {BSR "Bit Scan Reverse" } - {BSWAP "Byte Swap" } - {BT "Bit Test" } - {BTC "Bit Test and Complement" } - {BTR "Bit Test and Reset" } - {BTS "Bit Test and Set" } - {BZHI "Zero High Bits Starting with Specified Bit Position" } - {CALL "Call Procedure" } - {CBW "Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword" } - {CDQ "Convert Word to Doubleword/Convert Doubleword to Quadword" } - {CDQE "Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword" } - {CLAC "Clear AC Flag in EFLAGS Register" } - {CLC "Clear Carry Flag" } - {CLD "Clear Direction Flag" } - {CLDEMOTE "Cache Line Demote" } - {CLFLUSH "Flush Cache Line" } - {CLFLUSHOPT "Flush Cache Line Optimized" } - {CLI "Clear Interrupt Flag" } - {CLRSSBSY "Clear Busy Flag in a Supervisor Shadow Stack Token" } - {CLTS "Clear Task-Switched Flag in CR0" } - {CLWB "Cache Line Write Back" } - {CMC "Complement Carry Flag" } - {CMOVcc "Conditional Move" } - {CMP "Compare Two Operands" } - {CMPPD "Compare Packed Double-Precision Floating-Point Values" } - {CMPPS "Compare Packed Single-Precision Floating-Point Values" } - {CMPS "Compare String Operands" } - {CMPSB "Compare String Operands" } - {CMPSD "Compare String Operands" } - {CMPSQ "Compare String Operands" } - {CMPSS "Compare Scalar Single-Precision Floating-Point Value" } - {CMPSW "Compare String Operands" } - {CMPXCHG "Compare and Exchange" } - {CMPXCHG16B "Compare and Exchange Bytes" } - {CMPXCHG8B "Compare and Exchange Bytes" } - {COMISD "Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS" } - {COMISS "Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS" } - {CPUID "CPU Identification" } - {CQO "Convert Word to Doubleword/Convert Doubleword to Quadword" } - {CRC32 "Accumulate CRC32 Value" } - {CVTDQ2PD "Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values" } - {CVTDQ2PS "Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values" } - {CVTPD2DQ "Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers" } - {CVTPD2PI "Convert Packed Double-Precision FP Values to Packed Dword Integers" } - {CVTPD2PS "Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values" } - {CVTPI2PD "Convert Packed Dword Integers to Packed Double-Precision FP Values" } - {CVTPI2PS "Convert Packed Dword Integers to Packed Single-Precision FP Values" } - {CVTPS2DQ "Convert Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values" } - {CVTPS2PD "Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values" } - {CVTPS2PI "Convert Packed Single-Precision FP Values to Packed Dword Integers" } - {CVTSD2SI "Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer" } - {CVTSD2SS "Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value" } - {CVTSI2SD "Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value" } - {CVTSI2SS "Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value" } - {CVTSS2SD "Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value" } - {CVTSS2SI "Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer" } - {CVTTPD2DQ "Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers" } - {CVTTPD2PI "Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers" } - {CVTTPS2DQ "Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values" } - {CVTTPS2PI "Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers" } - {CVTTSD2SI "Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed Integer" } - {CVTTSS2SI "Convert with Truncation Scalar Single-Precision Floating-Point Value to Integer" } - {CWD "Convert Word to Doubleword/Convert Doubleword to Quadword" } - {CWDE "Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword" } - {DAA "Decimal Adjust AL after Addition" } - {DAS "Decimal Adjust AL after Subtraction" } - {DEC "Decrement by 1" } - {DIV "Unsigned Divide" } - {DIVPD "Divide Packed Double-Precision Floating-Point Values" } - {DIVPS "Divide Packed Single-Precision Floating-Point Values" } - {DIVSD "Divide Scalar Double-Precision Floating-Point Value" } - {DIVSS "Divide Scalar Single-Precision Floating-Point Values" } - {DPPD "Dot Product of Packed Double Precision Floating-Point Values" } - {DPPS "Dot Product of Packed Single Precision Floating-Point Values" } - {EMMS "Empty MMX Technology State" } - {ENCODEKEY128 "Encode 128-Bit Key with Key Locker" } - {ENCODEKEY256 "Encode 256-Bit Key with Key Locker" } - {ENDBR32 "Terminate an Indirect Branch in 32-bit and Compatibility Mode" } - {ENDBR64 "Terminate an Indirect Branch in 64-bit Mode" } - {ENTER "Make Stack Frame for Procedure Parameters" } - {EXTRACTPS "Extract Packed Floating-Point Values" } - {F2XM1 "Compute 2x–1" } - {FABS "Absolute Value" } - {FADD "Add" } - {FADDP "Add" } - {FBLD "Load Binary Coded Decimal" } - {FBSTP "Store BCD Integer and Pop" } - {FCHS "Change Sign" } - {FCLEX "Clear Exceptions" } - {FCMOVcc "Floating-Point Conditional Move" } - {FCOM "Compare Floating Point Values" } - {FCOMI "Compare Floating Point Values and Set EFLAGS" } - {FCOMIP "Compare Floating Point Values and Set EFLAGS" } - {FCOMP "Compare Floating Point Values" } - {FCOMPP "Compare Floating Point Values" } - {FCOS "Cosine" } - {FDECSTP "Decrement Stack-Top Pointer" } - {FDIV "Divide" } - {FDIVP "Divide" } - {FDIVR "Reverse Divide" } - {FDIVRP "Reverse Divide" } - {FFREE "Free Floating-Point Register" } - {FIADD "Add" } - {FICOM "Compare Integer" } - {FICOMP "Compare Integer" } - {FIDIV "Divide" } - {FIDIVR "Reverse Divide" } - {FILD "Load Integer" } - {FIMUL "Multiply" } - {FINCSTP "Increment Stack-Top Pointer" } - {FINIT "Initialize Floating-Point Unit" } - {FIST "Store Integer" } - {FISTP "Store Integer" } - {FISTTP "Store Integer with Truncation" } - {FISUB "Subtract" } - {FISUBR "Reverse Subtract" } - {FLD "Load Floating Point Value" } - {FLD1 "Load Constant" } - {FLDCW "Load x87 FPU Control Word" } - {FLDENV "Load x87 FPU Environment" } - {FLDL2E "Load Constant" } - {FLDL2T "Load Constant" } - {FLDLG2 "Load Constant" } - {FLDLN2 "Load Constant" } - {FLDPI "Load Constant" } - {FLDZ "Load Constant" } - {FMUL "Multiply" } - {FMULP "Multiply" } - {FNCLEX "Clear Exceptions" } - {FNINIT "Initialize Floating-Point Unit" } - {FNOP "No Operation" } - {FNSAVE "Store x87 FPU State" } - {FNSTCW "Store x87 FPU Control Word" } - {FNSTENV "Store x87 FPU Environment" } - {FNSTSW "Store x87 FPU Status Word" } - {FPATAN "Partial Arctangent" } - {FPREM "Partial Remainder" } - {FPREM1 "Partial Remainder" } - {FPTAN "Partial Tangent" } - {FRNDINT "Round to Integer" } - {FRSTOR "Restore x87 FPU State" } - {FSAVE "Store x87 FPU State" } - {FSCALE "Scale" } - {FSIN "Sine" } - {FSINCOS "Sine and Cosine" } - {FSQRT "Square Root" } - {FST "Store Floating Point Value" } - {FSTCW "Store x87 FPU Control Word" } - {FSTENV "Store x87 FPU Environment" } - {FSTP "Store Floating Point Value" } - {FSTSW "Store x87 FPU Status Word" } - {FSUB "Subtract" } - {FSUBP "Subtract" } - {FSUBR "Reverse Subtract" } - {FSUBRP "Reverse Subtract" } - {FTST "TEST" } - {FUCOM "Unordered Compare Floating Point Values" } - {FUCOMI "Compare Floating Point Values and Set EFLAGS" } - {FUCOMIP "Compare Floating Point Values and Set EFLAGS" } - {FUCOMP "Unordered Compare Floating Point Values" } - {FUCOMPP "Unordered Compare Floating Point Values" } - {FWAIT "Wait" } - {FXAM "Examine Floating-Point" } - {FXCH "Exchange Register Contents" } - {FXRSTOR "Restore x87 FPU, MMX, XMM, and MXCSR State" } - {FXSAVE "Save x87 FPU, MMX Technology, and SSE State" } - {FXTRACT "Extract Exponent and Significand" } - {FYL2X "Compute y * log2x" } - {FYL2XP1 "Compute y * log2(x +1)" } - {GF2P8AFFINEINVQB "Galois Field Affine Transformation Inverse" } - {GF2P8AFFINEQB "Galois Field Affine Transformation" } - {GF2P8MULB "Galois Field Multiply Bytes" } - {HADDPD "Packed Double-FP Horizontal Add" } - {HADDPS "Packed Single-FP Horizontal Add" } - {HLT "Halt" } - {HRESET "History Reset" } - {HSUBPD "Packed Double-FP Horizontal Subtract" } - {HSUBPS "Packed Single-FP Horizontal Subtract" } - {IDIV "Signed Divide" } - {IMUL "Signed Multiply" } - {IN "Input from Port" } - {INC "Increment by 1" } - {INCSSPD "Increment Shadow Stack Pointer" } - {INCSSPQ "Increment Shadow Stack Pointer" } - {INS "Input from Port to String" } - {INSB "Input from Port to String" } - {INSD "Input from Port to String" } - {INSERTPS "Insert Scalar Single-Precision Floating-Point Value" } - {INSW "Input from Port to String" } - {INT "Call to Interrupt Procedure" } - {INT1 "Call to Interrupt Procedure" } - {INT3 "Call to Interrupt Procedure" } - {INTO "Call to Interrupt Procedure" } - {INVD "Invalidate Internal Caches" } - {INVLPG "Invalidate TLB Entries" } - {INVPCID "Invalidate Process-Context Identifier" } - {IRET "Interrupt Return" } - {IRETD "Interrupt Return" } - {IRETQ "Interrupt Return" } - {JMP "Jump" } - {Jcc "Jump if Condition Is Met" } - {KADDB "ADD Two Masks" } - {KADDD "ADD Two Masks" } - {KADDQ "ADD Two Masks" } - {KADDW "ADD Two Masks" } - {KANDB "Bitwise Logical AND Masks" } - {KANDD "Bitwise Logical AND Masks" } - {KANDNB "Bitwise Logical AND NOT Masks" } - {KANDND "Bitwise Logical AND NOT Masks" } - {KANDNQ "Bitwise Logical AND NOT Masks" } - {KANDNW "Bitwise Logical AND NOT Masks" } - {KANDQ "Bitwise Logical AND Masks" } - {KANDW "Bitwise Logical AND Masks" } - {KMOVB "Move from and to Mask Registers" } - {KMOVD "Move from and to Mask Registers" } - {KMOVQ "Move from and to Mask Registers" } - {KMOVW "Move from and to Mask Registers" } - {KNOTB "NOT Mask Register" } - {KNOTD "NOT Mask Register" } - {KNOTQ "NOT Mask Register" } - {KNOTW "NOT Mask Register" } - {KORB "Bitwise Logical OR Masks" } - {KORD "Bitwise Logical OR Masks" } - {KORQ "Bitwise Logical OR Masks" } - {KORTESTB "OR Masks And Set Flags" } - {KORTESTD "OR Masks And Set Flags" } - {KORTESTQ "OR Masks And Set Flags" } - {KORTESTW "OR Masks And Set Flags" } - {KORW "Bitwise Logical OR Masks" } - {KSHIFTLB "Shift Left Mask Registers" } - {KSHIFTLD "Shift Left Mask Registers" } - {KSHIFTLQ "Shift Left Mask Registers" } - {KSHIFTLW "Shift Left Mask Registers" } - {KSHIFTRB "Shift Right Mask Registers" } - {KSHIFTRD "Shift Right Mask Registers" } - {KSHIFTRQ "Shift Right Mask Registers" } - {KSHIFTRW "Shift Right Mask Registers" } - {KTESTB "Packed Bit Test Masks and Set Flags" } - {KTESTD "Packed Bit Test Masks and Set Flags" } - {KTESTQ "Packed Bit Test Masks and Set Flags" } - {KTESTW "Packed Bit Test Masks and Set Flags" } - {KUNPCKBW "Unpack for Mask Registers" } - {KUNPCKDQ "Unpack for Mask Registers" } - {KUNPCKWD "Unpack for Mask Registers" } - {KXNORB "Bitwise Logical XNOR Masks" } - {KXNORD "Bitwise Logical XNOR Masks" } - {KXNORQ "Bitwise Logical XNOR Masks" } - {KXNORW "Bitwise Logical XNOR Masks" } - {KXORB "Bitwise Logical XOR Masks" } - {KXORD "Bitwise Logical XOR Masks" } - {KXORQ "Bitwise Logical XOR Masks" } - {KXORW "Bitwise Logical XOR Masks" } - {LAHF "Load Status Flags into AH Register" } - {LAR "Load Access Rights Byte" } - {LDDQU "Load Unaligned Integer 128 Bits" } - {LDMXCSR "Load MXCSR Register" } - {LDS "Load Far Pointer" } - {LEA "Load Effective Address" } - {LEAVE "High Level Procedure Exit" } - {LES "Load Far Pointer" } - {LFENCE "Load Fence" } - {LFS "Load Far Pointer" } - {LGDT "Load Global/Interrupt Descriptor Table Register" } - {LGS "Load Far Pointer" } - {LIDT "Load Global/Interrupt Descriptor Table Register" } - {LLDT "Load Local Descriptor Table Register" } - {LMSW "Load Machine Status Word" } - {LOADIWKEY "Load Internal Wrapping Key with Key Locker" } - {LOCK "Assert LOCK# Signal Prefix" } - {LODS "Load String" } - {LODSB "Load String" } - {LODSD "Load String" } - {LODSQ "Load String" } - {LODSW "Load String" } - {LOOP "Loop According to ECX Counter" } - {LOOPcc "Loop According to ECX Counter" } - {LSL "Load Segment Limit" } - {LSS "Load Far Pointer" } - {LTR "Load Task Register" } - {LZCNT "Count the Number of Leading Zero Bits" } - {MASKMOVDQU "Store Selected Bytes of Double Quadword" } - {MASKMOVQ "Store Selected Bytes of Quadword" } - {MAXPD "Maximum of Packed Double-Precision Floating-Point Values" } - {MAXPS "Maximum of Packed Single-Precision Floating-Point Values" } - {MAXSD "Return Maximum Scalar Double-Precision Floating-Point Value" } - {MAXSS "Return Maximum Scalar Single-Precision Floating-Point Value" } - {MFENCE "Memory Fence" } - {MINPD "Minimum of Packed Double-Precision Floating-Point Values" } - {MINPS "Minimum of Packed Single-Precision Floating-Point Values" } - {MINSD "Return Minimum Scalar Double-Precision Floating-Point Value" } - {MINSS "Return Minimum Scalar Single-Precision Floating-Point Value" } - {MONITOR "Set Up Monitor Address" } - {MOV "Move" } - {MOVAPD "Move Aligned Packed Double-Precision Floating-Point Values" } - {MOVAPS "Move Aligned Packed Single-Precision Floating-Point Values" } - {MOVBE "Move Data After Swapping Bytes" } - {MOVD "Move Doubleword/Move Quadword" } - {MOVDDUP "Replicate Double FP Values" } - {MOVDIR64B "Move 64 Bytes as Direct Store" } - {MOVDIRI "Move Doubleword as Direct Store" } - {MOVDQ2Q "Move Quadword from XMM to MMX Technology Register" } - {MOVDQA "Move Aligned Packed Integer Values" } - {MOVDQU "Move Unaligned Packed Integer Values" } - {MOVHLPS "Move Packed Single-Precision Floating-Point Values High to Low" } - {MOVHPD "Move High Packed Double-Precision Floating-Point Value" } - {MOVHPS "Move High Packed Single-Precision Floating-Point Values" } - {MOVLHPS "Move Packed Single-Precision Floating-Point Values Low to High" } - {MOVLPD "Move Low Packed Double-Precision Floating-Point Value" } - {MOVLPS "Move Low Packed Single-Precision Floating-Point Values" } - {MOVMSKPD "Extract Packed Double-Precision Floating-Point Sign Mask" } - {MOVMSKPS "Extract Packed Single-Precision Floating-Point Sign Mask" } - {MOVNTDQ "Store Packed Integers Using Non-Temporal Hint" } - {MOVNTDQA "Load Double Quadword Non-Temporal Aligned Hint" } - {MOVNTI "Store Doubleword Using Non-Temporal Hint" } - {MOVNTPD "Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint" } - {MOVNTPS "Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint" } - {MOVNTQ "Store of Quadword Using Non-Temporal Hint" } - {MOVQ "Move Doubleword/Move Quadword" } - {MOVQ2DQ "Move Quadword from MMX Technology to XMM Register" } - {MOVS "Move Data from String to String" } - {MOVSB "Move Data from String to String" } - {MOVSD "Move Data from String to String" } - {MOVSHDUP "Replicate Single FP Values" } - {MOVSLDUP "Replicate Single FP Values" } - {MOVSQ "Move Data from String to String" } - {MOVSS "Move or Merge Scalar Single-Precision Floating-Point Value" } - {MOVSW "Move Data from String to String" } - {MOVSX "Move with Sign-Extension" } - {MOVSXD "Move with Sign-Extension" } - {MOVUPD "Move Unaligned Packed Double-Precision Floating-Point Values" } - {MOVUPS "Move Unaligned Packed Single-Precision Floating-Point Values" } - {MOVZX "Move with Zero-Extend" } - {MPSADBW "Compute Multiple Packed Sums of Absolute Difference" } - {MUL "Unsigned Multiply" } - {MULPD "Multiply Packed Double-Precision Floating-Point Values" } - {MULPS "Multiply Packed Single-Precision Floating-Point Values" } - {MULSD "Multiply Scalar Double-Precision Floating-Point Value" } - {MULSS "Multiply Scalar Single-Precision Floating-Point Values" } - {MULX "Unsigned Multiply Without Affecting Flags" } - {MWAIT "Monitor Wait" } - {NEG "Two's Complement Negation" } - {NOP "No Operation" } - {NOT "One's Complement Negation" } - {OR "Logical Inclusive OR" } - {ORPD "Bitwise Logical OR of Packed Double Precision Floating-Point Values" } - {ORPS "Bitwise Logical OR of Packed Single Precision Floating-Point Values" } - {OUT "Output to Port" } - {OUTS "Output String to Port" } - {OUTSB "Output String to Port" } - {OUTSD "Output String to Port" } - {OUTSW "Output String to Port" } - {PABSB "Packed Absolute Value" } - {PABSD "Packed Absolute Value" } - {PABSQ "Packed Absolute Value" } - {PABSW "Packed Absolute Value" } - {PACKSSDW "Pack with Signed Saturation" } - {PACKSSWB "Pack with Signed Saturation" } - {PACKUSDW "Pack with Unsigned Saturation" } - {PACKUSWB "Pack with Unsigned Saturation" } - {PADDB "Add Packed Integers" } - {PADDD "Add Packed Integers" } - {PADDQ "Add Packed Integers" } - {PADDSB "Add Packed Signed Integers with Signed Saturation" } - {PADDSW "Add Packed Signed Integers with Signed Saturation" } - {PADDUSB "Add Packed Unsigned Integers with Unsigned Saturation" } - {PADDUSW "Add Packed Unsigned Integers with Unsigned Saturation" } - {PADDW "Add Packed Integers" } - {PALIGNR "Packed Align Right" } - {PAND "Logical AND" } - {PANDN "Logical AND NOT" } - {PAUSE "Spin Loop Hint" } - {PAVGB "Average Packed Integers" } - {PAVGW "Average Packed Integers" } - {PBLENDVB "Variable Blend Packed Bytes" } - {PBLENDW "Blend Packed Words" } - {PCLMULQDQ "Carry-Less Multiplication Quadword" } - {PCMPEQB "Compare Packed Data for Equal" } - {PCMPEQD "Compare Packed Data for Equal" } - {PCMPEQQ "Compare Packed Qword Data for Equal" } - {PCMPEQW "Compare Packed Data for Equal" } - {PCMPESTRI "Packed Compare Explicit Length Strings, Return Index" } - {PCMPESTRM "Packed Compare Explicit Length Strings, Return Mask" } - {PCMPGTB "Compare Packed Signed Integers for Greater Than" } - {PCMPGTD "Compare Packed Signed Integers for Greater Than" } - {PCMPGTQ "Compare Packed Data for Greater Than" } - {PCMPGTW "Compare Packed Signed Integers for Greater Than" } - {PCMPISTRI "Packed Compare Implicit Length Strings, Return Index" } - {PCMPISTRM "Packed Compare Implicit Length Strings, Return Mask" } - {PCONFIG "Platform Configuration" } - {PDEP "Parallel Bits Deposit" } - {PEXT "Parallel Bits Extract" } - {PEXTRB "Extract Byte/Dword/Qword" } - {PEXTRD "Extract Byte/Dword/Qword" } - {PEXTRQ "Extract Byte/Dword/Qword" } - {PEXTRW "Extract Word" } - {PHADDD "Packed Horizontal Add" } - {PHADDSW "Packed Horizontal Add and Saturate" } - {PHADDW "Packed Horizontal Add" } - {PHMINPOSUW "Packed Horizontal Word Minimum" } - {PHSUBD "Packed Horizontal Subtract" } - {PHSUBSW "Packed Horizontal Subtract and Saturate" } - {PHSUBW "Packed Horizontal Subtract" } - {PINSRB "Insert Byte/Dword/Qword" } - {PINSRD "Insert Byte/Dword/Qword" } - {PINSRQ "Insert Byte/Dword/Qword" } - {PINSRW "Insert Word" } - {PMADDUBSW "Multiply and Add Packed Signed and Unsigned Bytes" } - {PMADDWD "Multiply and Add Packed Integers" } - {PMAXSB "Maximum of Packed Signed Integers" } - {PMAXSD "Maximum of Packed Signed Integers" } - {PMAXSQ "Maximum of Packed Signed Integers" } - {PMAXSW "Maximum of Packed Signed Integers" } - {PMAXUB "Maximum of Packed Unsigned Integers" } - {PMAXUD "Maximum of Packed Unsigned Integers" } - {PMAXUQ "Maximum of Packed Unsigned Integers" } - {PMAXUW "Maximum of Packed Unsigned Integers" } - {PMINSB "Minimum of Packed Signed Integers" } - {PMINSD "Minimum of Packed Signed Integers" } - {PMINSQ "Minimum of Packed Signed Integers" } - {PMINSW "Minimum of Packed Signed Integers" } - {PMINUB "Minimum of Packed Unsigned Integers" } - {PMINUD "Minimum of Packed Unsigned Integers" } - {PMINUQ "Minimum of Packed Unsigned Integers" } - {PMINUW "Minimum of Packed Unsigned Integers" } - {PMOVMSKB "Move Byte Mask" } - {PMOVSX "Packed Move with Sign Extend" } - {PMOVZX "Packed Move with Zero Extend" } - {PMULDQ "Multiply Packed Doubleword Integers" } - {PMULHRSW "Packed Multiply High with Round and Scale" } - {PMULHUW "Multiply Packed Unsigned Integers and Store High Result" } - {PMULHW "Multiply Packed Signed Integers and Store High Result" } - {PMULLD "Multiply Packed Integers and Store Low Result" } - {PMULLQ "Multiply Packed Integers and Store Low Result" } - {PMULLW "Multiply Packed Signed Integers and Store Low Result" } - {PMULUDQ "Multiply Packed Unsigned Doubleword Integers" } - {POP "Pop a Value from the Stack" } - {POPA "Pop All General-Purpose Registers" } - {POPAD "Pop All General-Purpose Registers" } - {POPCNT "Return the Count of Number of Bits Set to 1" } - {POPF "Pop Stack into EFLAGS Register" } - {POPFD "Pop Stack into EFLAGS Register" } - {POPFQ "Pop Stack into EFLAGS Register" } - {POR "Bitwise Logical OR" } - {PREFETCHW "Prefetch Data into Caches in Anticipation of a Write" } - {PREFETCHh "Prefetch Data Into Caches" } - {PSADBW "Compute Sum of Absolute Differences" } - {PSHUFB "Packed Shuffle Bytes" } - {PSHUFD "Shuffle Packed Doublewords" } - {PSHUFHW "Shuffle Packed High Words" } - {PSHUFLW "Shuffle Packed Low Words" } - {PSHUFW "Shuffle Packed Words" } - {PSIGNB "Packed SIGN" } - {PSIGND "Packed SIGN" } - {PSIGNW "Packed SIGN" } - {PSLLD "Shift Packed Data Left Logical" } - {PSLLDQ "Shift Double Quadword Left Logical" } - {PSLLQ "Shift Packed Data Left Logical" } - {PSLLW "Shift Packed Data Left Logical" } - {PSRAD "Shift Packed Data Right Arithmetic" } - {PSRAQ "Shift Packed Data Right Arithmetic" } - {PSRAW "Shift Packed Data Right Arithmetic" } - {PSRLD "Shift Packed Data Right Logical" } - {PSRLDQ "Shift Double Quadword Right Logical" } - {PSRLQ "Shift Packed Data Right Logical" } - {PSRLW "Shift Packed Data Right Logical" } - {PSUBB "Subtract Packed Integers" } - {PSUBD "Subtract Packed Integers" } - {PSUBQ "Subtract Packed Quadword Integers" } - {PSUBSB "Subtract Packed Signed Integers with Signed Saturation" } - {PSUBSW "Subtract Packed Signed Integers with Signed Saturation" } - {PSUBUSB "Subtract Packed Unsigned Integers with Unsigned Saturation" } - {PSUBUSW "Subtract Packed Unsigned Integers with Unsigned Saturation" } - {PSUBW "Subtract Packed Integers" } - {PTEST "Logical Compare" } - {PTWRITE "Write Data to a Processor Trace Packet" } - {PUNPCKHBW "Unpack High Data" } - {PUNPCKHDQ "Unpack High Data" } - {PUNPCKHQDQ "Unpack High Data" } - {PUNPCKHWD "Unpack High Data" } - {PUNPCKLBW "Unpack Low Data" } - {PUNPCKLDQ "Unpack Low Data" } - {PUNPCKLQDQ "Unpack Low Data" } - {PUNPCKLWD "Unpack Low Data" } - {PUSH "Push Word, Doubleword or Quadword Onto the Stack" } - {PUSHA "Push All General-Purpose Registers" } - {PUSHAD "Push All General-Purpose Registers" } - {PUSHF "Push EFLAGS Register onto the Stack" } - {PUSHFD "Push EFLAGS Register onto the Stack" } - {PUSHFQ "Push EFLAGS Register onto the Stack" } - {PXOR "Logical Exclusive OR" } - {RCL "Rotate" } - {RCPPS "Compute Reciprocals of Packed Single-Precision Floating-Point Values" } - {RCPSS "Compute Reciprocal of Scalar Single-Precision Floating-Point Values" } - {RCR "Rotate" } - {RDFSBASE "Read FS/GS Segment Base" } - {RDGSBASE "Read FS/GS Segment Base" } - {RDMSR "Read from Model Specific Register" } - {RDPID "Read Processor ID" } - {RDPKRU "Read Protection Key Rights for User Pages" } - {RDPMC "Read Performance-Monitoring Counters" } - {RDRAND "Read Random Number" } - {RDSEED "Read Random SEED" } - {RDSSPD "Read Shadow Stack Pointer" } - {RDSSPQ "Read Shadow Stack Pointer" } - {RDTSC "Read Time-Stamp Counter" } - {RDTSCP "Read Time-Stamp Counter and Processor ID" } - {REP "Repeat String Operation Prefix" } - {REPE "Repeat String Operation Prefix" } - {REPNE "Repeat String Operation Prefix" } - {REPNZ "Repeat String Operation Prefix" } - {REPZ "Repeat String Operation Prefix" } - {RET "Return from Procedure" } - {ROL "Rotate" } - {ROR "Rotate" } - {RORX "Rotate Right Logical Without Affecting Flags" } - {ROUNDPD "Round Packed Double Precision Floating-Point Values" } - {ROUNDPS "Round Packed Single Precision Floating-Point Values" } - {ROUNDSD "Round Scalar Double Precision Floating-Point Values" } - {ROUNDSS "Round Scalar Single Precision Floating-Point Values" } - {RSM "Resume from System Management Mode" } - {RSQRTPS "Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values" } - {RSQRTSS "Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value" } - {RSTORSSP "Restore Saved Shadow Stack Pointer" } - {SAHF "Store AH into Flags" } - {SAL "Shift" } - {SAR "Shift" } - {SARX "Shift Without Affecting Flags" } - {SAVEPREVSSP "Save Previous Shadow Stack Pointer" } - {SBB "Integer Subtraction with Borrow" } - {SCAS "Scan String" } - {SCASB "Scan String" } - {SCASD "Scan String" } - {SCASW "Scan String" } - {SERIALIZE "Serialize Instruction Execution" } - {SETSSBSY "Mark Shadow Stack Busy" } - {SETcc "Set Byte on Condition" } - {SFENCE "Store Fence" } - {SGDT "Store Global Descriptor Table Register" } - {SHA1MSG1 "Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords" } - {SHA1MSG2 "Perform a Final Calculation for the Next Four SHA1 Message Dwords" } - {SHA1NEXTE "Calculate SHA1 State Variable E after Four Rounds" } - {SHA1RNDS4 "Perform Four Rounds of SHA1 Operation" } - {SHA256MSG1 "Perform an Intermediate Calculation for the Next Four SHA256 Message Dwords" } - {SHA256MSG2 "Perform a Final Calculation for the Next Four SHA256 Message Dwords" } - {SHA256RNDS2 "Perform Two Rounds of SHA256 Operation" } - {SHL "Shift" } - {SHLD "Double Precision Shift Left" } - {SHLX "Shift Without Affecting Flags" } - {SHR "Shift" } - {SHRD "Double Precision Shift Right" } - {SHRX "Shift Without Affecting Flags" } - {SHUFPD "Packed Interleave Shuffle of Pairs of Double-Precision Floating-Point Values" } - {SHUFPS "Packed Interleave Shuffle of Quadruplets of Single-Precision Floating-Point Values" } - {SIDT "Store Interrupt Descriptor Table Register" } - {SLDT "Store Local Descriptor Table Register" } - {SMSW "Store Machine Status Word" } - {SQRTPD "Square Root of Double-Precision Floating-Point Values" } - {SQRTPS "Square Root of Single-Precision Floating-Point Values" } - {SQRTSD "Compute Square Root of Scalar Double-Precision Floating-Point Value" } - {SQRTSS "Compute Square Root of Scalar Single-Precision Value" } - {STAC "Set AC Flag in EFLAGS Register" } - {STC "Set Carry Flag" } - {STD "Set Direction Flag" } - {STI "Set Interrupt Flag" } - {STMXCSR "Store MXCSR Register State" } - {STOS "Store String" } - {STOSB "Store String" } - {STOSD "Store String" } - {STOSQ "Store String" } - {STOSW "Store String" } - {STR "Store Task Register" } - {SUB "Subtract" } - {SUBPD "Subtract Packed Double-Precision Floating-Point Values" } - {SUBPS "Subtract Packed Single-Precision Floating-Point Values" } - {SUBSD "Subtract Scalar Double-Precision Floating-Point Value" } - {SUBSS "Subtract Scalar Single-Precision Floating-Point Value" } - {SWAPGS "Swap GS Base Register" } - {SYSCALL "Fast System Call" } - {SYSENTER "Fast System Call" } - {SYSEXIT "Fast Return from Fast System Call" } - {SYSRET "Return From Fast System Call" } - {TEST "Logical Compare" } - {TPAUSE "Timed PAUSE" } - {TZCNT "Count the Number of Trailing Zero Bits" } - {UCOMISD "Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS" } - {UCOMISS "Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS" } - {UD "Undefined Instruction" } - {UMONITOR "User Level Set Up Monitor Address" } - {UMWAIT "User Level Monitor Wait" } - {UNPCKHPD "Unpack and Interleave High Packed Double-Precision Floating-Point Values" } - {UNPCKHPS "Unpack and Interleave High Packed Single-Precision Floating-Point Values" } - {UNPCKLPD "Unpack and Interleave Low Packed Double-Precision Floating-Point Values" } - {UNPCKLPS "Unpack and Interleave Low Packed Single-Precision Floating-Point Values" } - {VALIGND "Align Doubleword/Quadword Vectors" } - {VALIGNQ "Align Doubleword/Quadword Vectors" } - {VBLENDMPD "Blend Float64/Float32 Vectors Using an OpMask Control" } - {VBLENDMPS "Blend Float64/Float32 Vectors Using an OpMask Control" } - {VBROADCAST "Load with Broadcast Floating-Point Data" } - {VCOMPRESSPD "Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory" } - {VCOMPRESSPS "Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory" } - {VCOMPRESSW "Store Sparse Packed Byte/Word Integer Values into Dense Memory/Register" } - {VCVTNE2PS2BF16 "Convert Two Packed Single Data to One Packed BF16 Data" } - {VCVTNEPS2BF16 "Convert Packed Single Data to Packed BF16 Data" } - {VCVTPD2QQ "Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers" } - {VCVTPD2UDQ "Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers" } - {VCVTPD2UQQ "Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers" } - {VCVTPH2PS "Convert 16-bit FP values to Single-Precision FP values" } - {VCVTPS2PH "Convert Single-Precision FP value to 16-bit FP value" } - {VCVTPS2QQ "Convert Packed Single Precision Floating-Point Values to Packed Signed Quadword Integer Values" } - {VCVTPS2UDQ "Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values" } - {VCVTPS2UQQ "Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values" } - {VCVTQQ2PD "Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values" } - {VCVTQQ2PS "Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values" } - {VCVTSD2USI "Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer" } - {VCVTSS2USI "Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer" } - {VCVTTPD2QQ "Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers" } - {VCVTTPD2UDQ "Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers" } - {VCVTTPD2UQQ "Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers" } - {VCVTTPS2QQ "Convert with Truncation Packed Single Precision Floating-Point Values to Packed Signed Quadword Integer Values" } - {VCVTTPS2UDQ "Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values" } - {VCVTTPS2UQQ "Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values" } - {VCVTTSD2USI "Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer" } - {VCVTTSS2USI "Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer" } - {VCVTUDQ2PD "Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values" } - {VCVTUDQ2PS "Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values" } - {VCVTUQQ2PD "Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values" } - {VCVTUQQ2PS "Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values" } - {VCVTUSI2SD "Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value" } - {VCVTUSI2SS "Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value" } - {VDBPSADBW "Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes" } - {VDPBF16PS "Dot Product of BF16 Pairs Accumulated into Packed Single Precision" } - {VERR "Verify a Segment for Reading or Writing" } - {VERW "Verify a Segment for Reading or Writing" } - {VEXPANDPD "Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory" } - {VEXPANDPS "Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory" } - {VEXTRACTF128 "Extr act Packed Floating-Point Values" } - {VEXTRACTF32x4 "Extr act Packed Floating-Point Values" } - {VEXTRACTF32x8 "Extr act Packed Floating-Point Values" } - {VEXTRACTF64x2 "Extr act Packed Floating-Point Values" } - {VEXTRACTF64x4 "Extr act Packed Floating-Point Values" } - {VEXTRACTI128 "Extract packed Integer Values" } - {VEXTRACTI32x4 "Extract packed Integer Values" } - {VEXTRACTI32x8 "Extract packed Integer Values" } - {VEXTRACTI64x2 "Extract packed Integer Values" } - {VEXTRACTI64x4 "Extract packed Integer Values" } - {VFIXUPIMMPD "Fix Up Special Packed Float64 Values" } - {VFIXUPIMMPS "Fix Up Special Packed Float32 Values" } - {VFIXUPIMMSD "Fix Up Special Scalar Float64 Value" } - {VFIXUPIMMSS "Fix Up Special Scalar Float32 Value" } - {VFMADD132PD "Fused Multiply-Add of Packed Double- Precision Floating-Point Values" } - {VFMADD132PS "Fused Multiply-Add of Packed Single- Precision Floating-Point Values" } - {VFMADD132SD "Fused Multiply-Add of Scalar Double- Precision Floating-Point Values" } - {VFMADD132SS "Fused Multiply-Add of Scalar Single-Precision Floating-Point Values" } - {VFMADD213PD "Fused Multiply-Add of Packed Double- Precision Floating-Point Values" } - {VFMADD213PS "Fused Multiply-Add of Packed Single- Precision Floating-Point Values" } - {VFMADD213SD "Fused Multiply-Add of Scalar Double- Precision Floating-Point Values" } - {VFMADD213SS "Fused Multiply-Add of Scalar Single-Precision Floating-Point Values" } - {VFMADD231PD "Fused Multiply-Add of Packed Double- Precision Floating-Point Values" } - {VFMADD231PS "Fused Multiply-Add of Packed Single- Precision Floating-Point Values" } - {VFMADD231SD "Fused Multiply-Add of Scalar Double- Precision Floating-Point Values" } - {VFMADD231SS "Fused Multiply-Add of Scalar Single-Precision Floating-Point Values" } - {VFMADDSUB132PD "Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values" } - {VFMADDSUB132PS "Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values" } - {VFMADDSUB213PD "Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values" } - {VFMADDSUB213PS "Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values" } - {VFMADDSUB231PD "Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values" } - {VFMADDSUB231PS "Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values" } - {VFMSUB132PD "Fused Multiply-Subtract of Packed Double- Precision Floating-Point Values" } - {VFMSUB132PS "Fused Multiply-Subtract of Packed Single- Precision Floating-Point Values" } - {VFMSUB132SD "Fused Multiply-Subtract of Scalar Double- Precision Floating-Point Values" } - {VFMSUB132SS "Fused Multiply-Subtract of Scalar Single- Precision Floating-Point Values" } - {VFMSUB213PD "Fused Multiply-Subtract of Packed Double- Precision Floating-Point Values" } - {VFMSUB213PS "Fused Multiply-Subtract of Packed Single- Precision Floating-Point Values" } - {VFMSUB213SD "Fused Multiply-Subtract of Scalar Double- Precision Floating-Point Values" } - {VFMSUB213SS "Fused Multiply-Subtract of Scalar Single- Precision Floating-Point Values" } - {VFMSUB231PD "Fused Multiply-Subtract of Packed Double- Precision Floating-Point Values" } - {VFMSUB231PS "Fused Multiply-Subtract of Packed Single- Precision Floating-Point Values" } - {VFMSUB231SD "Fused Multiply-Subtract of Scalar Double- Precision Floating-Point Values" } - {VFMSUB231SS "Fused Multiply-Subtract of Scalar Single- Precision Floating-Point Values" } - {VFMSUBADD132PD "Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values" } - {VFMSUBADD132PS "Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values" } - {VFMSUBADD213PD "Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values" } - {VFMSUBADD213PS "Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values" } - {VFMSUBADD231PD "Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values" } - {VFMSUBADD231PS "Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values" } - {VFNMADD132PD "Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values" } - {VFNMADD132PS "Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values" } - {VFNMADD132SD "Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values" } - {VFNMADD132SS "Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values" } - {VFNMADD213PD "Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values" } - {VFNMADD213PS "Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values" } - {VFNMADD213SD "Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values" } - {VFNMADD213SS "Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values" } - {VFNMADD231PD "Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values" } - {VFNMADD231PS "Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values" } - {VFNMADD231SD "Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values" } - {VFNMADD231SS "Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values" } - {VFNMSUB132PD "Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values" } - {VFNMSUB132PS "Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values" } - {VFNMSUB132SD "Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values" } - {VFNMSUB132SS "Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values" } - {VFNMSUB213PD "Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values" } - {VFNMSUB213PS "Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values" } - {VFNMSUB213SD "Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values" } - {VFNMSUB213SS "Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values" } - {VFNMSUB231PD "Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values" } - {VFNMSUB231PS "Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values" } - {VFNMSUB231SD "Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values" } - {VFNMSUB231SS "Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values" } - {VFPCLASSPD "Tests Types Of a Packed Float64 Values" } - {VFPCLASSPS "Tests Types Of a Packed Float32 Values" } - {VFPCLASSSD "Tests Types Of a Scalar Float64 Values" } - {VFPCLASSSS "Tests Types Of a Scalar Float32 Values" } - {VGATHERDPD "Gather Packed DP FP Values Using Signed Dword/Qword Indices" } - {VGATHERDPS "Gather Packed SP FP values Using Signed Dword/Qword Indices" } - {VGATHERQPD "Gather Packed DP FP Values Using Signed Dword/Qword Indices" } - {VGATHERQPS "Gather Packed SP FP values Using Signed Dword/Qword Indices" } - {VGETEXPPD "Convert Exponents of Packed DP FP Values to DP FP Values" } - {VGETEXPPS "Convert Exponents of Packed SP FP Values to SP FP Values" } - {VGETEXPSD "Convert Exponents of Scalar DP FP Values to DP FP Value" } - {VGETEXPSS "Convert Exponents of Scalar SP FP Values to SP FP Value" } - {VGETMANTPD "Extract Float64 Vector of Normalized Mantissas from Float64 Vector" } - {VGETMANTPS "Extract Float32 Vector of Normalized Mantissas from Float32 Vector" } - {VGETMANTSD "Extract Float64 of Normalized Mantissas from Float64 Scalar" } - {VGETMANTSS "Extract Float32 Vector of Normalized Mantissa from Float32 Vector" } - {VINSERTF128 "Insert Packed Floating-Point Values" } - {VINSERTF32x4 "Insert Packed Floating-Point Values" } - {VINSERTF32x8 "Insert Packed Floating-Point Values" } - {VINSERTF64x2 "Insert Packed Floating-Point Values" } - {VINSERTF64x4 "Insert Packed Floating-Point Values" } - {VINSERTI128 "Insert Packed Integer Values" } - {VINSERTI32x4 "Insert Packed Integer Values" } - {VINSERTI32x8 "Insert Packed Integer Values" } - {VINSERTI64x2 "Insert Packed Integer Values" } - {VINSERTI64x4 "Insert Packed Integer Values" } - {VMASKMOV "Conditional SIMD Packed Loads and Stores" } - {VMOVDQA32 "Move Aligned Packed Integer Values" } - {VMOVDQA64 "Move Aligned Packed Integer Values" } - {VMOVDQU16 "Move Unaligned Packed Integer Values" } - {VMOVDQU32 "Move Unaligned Packed Integer Values" } - {VMOVDQU64 "Move Unaligned Packed Integer Values" } - {VMOVDQU8 "Move Unaligned Packed Integer Values" } - {VP2INTERSECTD "Compute Intersection Between DWORDS/QUADWORDS to a Pair of Mask Registers" } - {VP2INTERSECTQ "Compute Intersection Between DWORDS/QUADWORDS to a Pair of Mask Registers" } - {VPBLENDD "Blend Packed Dwords" } - {VPBLENDMB "Blend Byte/Word Vectors Using an Opmask Control" } - {VPBLENDMD "Blend Int32/Int64 Vectors Using an OpMask Control" } - {VPBLENDMQ "Blend Int32/Int64 Vectors Using an OpMask Control" } - {VPBLENDMW "Blend Byte/Word Vectors Using an Opmask Control" } - {VPBROADCAST "Load Integer and Broadcast" } - {VPBROADCASTB "Load with Broadcast Integer Data from General Purpose Register" } - {VPBROADCASTD "Load with Broadcast Integer Data from General Purpose Register" } - {VPBROADCASTM "Broadcast Mask to Vector Register" } - {VPBROADCASTQ "Load with Broadcast Integer Data from General Purpose Register" } - {VPBROADCASTW "Load with Broadcast Integer Data from General Purpose Register" } - {VPCMPB "Compare Packed Byte Values Into Mask" } - {VPCMPD "Compare Packed Integer Values into Mask" } - {VPCMPQ "Compare Packed Integer Values into Mask" } - {VPCMPUB "Compare Packed Byte Values Into Mask" } - {VPCMPUD "Compare Packed Integer Values into Mask" } - {VPCMPUQ "Compare Packed Integer Values into Mask" } - {VPCMPUW "Compare Packed Word Values Into Mask" } - {VPCMPW "Compare Packed Word Values Into Mask" } - {VPCOMPRESSB "Store Sparse Packed Byte/Word Integer Values into Dense Memory/Register" } - {VPCOMPRESSD "Store Sparse Packed Doubleword Integer Values into Dense Memory/Register" } - {VPCOMPRESSQ "Store Sparse Packed Quadword Integer Values into Dense Memory/Register" } - {VPCONFLICTD "Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense Memory/ Register" } - {VPCONFLICTQ "Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense Memory/ Register" } - {VPDPBUSD "Multiply and Add Unsigned and Signed Bytes" } - {VPDPBUSDS "Multiply and Add Unsigned and Signed Bytes with Saturation" } - {VPDPWSSD "Multiply and Add Signed Word Integers" } - {VPDPWSSDS "Multiply and Add Signed Word Integers with Saturation" } - {VPERM2F128 "Permute Floating-Point Values" } - {VPERM2I128 "Permute Integer Values" } - {VPERMB "Permute Packed Bytes Elements" } - {VPERMD "Permute Packed Doublewords/Words Elements" } - {VPERMI2B "Full Permute of Bytes from Two Tables Overwriting the Index" } - {VPERMI2D "Full Permute From Two Tables Overwriting the Index" } - {VPERMI2PD "Full Permute From Two Tables Overwriting the Index" } - {VPERMI2PS "Full Permute From Two Tables Overwriting the Index" } - {VPERMI2Q "Full Permute From Two Tables Overwriting the Index" } - {VPERMI2W "Full Permute From Two Tables Overwriting the Index" } - {VPERMILPD "Permute In-Lane of Pairs of Double-Precision Floating-Point Values" } - {VPERMILPS "Permute In-Lane of Quadruples of Single-Precision Floating-Point Values" } - {VPERMPD "Permute Double-Precision Floating-Point Elements" } - {VPERMPS "Permute Single-Precision Floating-Point Elements" } - {VPERMQ "Qwords Element Permutation" } - {VPERMT2B "Full Permute of Bytes from Two Tables Overwriting a Table" } - {VPERMT2D "Full Permute from Two Tables Overwriting one Table" } - {VPERMT2PD "Full Permute from Two Tables Overwriting one Table" } - {VPERMT2PS "Full Permute from Two Tables Overwriting one Table" } - {VPERMT2Q "Full Permute from Two Tables Overwriting one Table" } - {VPERMT2W "Full Permute from Two Tables Overwriting one Table" } - {VPERMW "Permute Packed Doublewords/Words Elements" } - {VPEXPANDB "Expand Byte/Word Values" } - {VPEXPANDD "Load Sparse Packed Doubleword Integer Values from Dense Memory / Register" } - {VPEXPANDQ "Load Sparse Packed Quadword Integer Values from Dense Memory / Register" } - {VPEXPANDW "Expand Byte/Word Values" } - {VPGATHERDD "Gather Packed Dword Values Using Signed Dword/Qword Indices" } - {VPGATHERDQ "Gather Packed Dword, Packed Qword with Signed Dword Indices" } - {VPGATHERQD "Gather Packed Dword Values Using Signed Dword/Qword Indices" } - {VPGATHERQQ "Gather Packed Qword Values Using Signed Dword/Qword Indices" } - {VPLZCNTD "Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values" } - {VPLZCNTQ "Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values" } - {VPMADD52HUQ "Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to 64-bit Accumulators" } - {VPMADD52LUQ "Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Qword Accumulators" } - {VPMASKMOV "Conditional SIMD Integer Packed Loads and Stores" } - {VPMOVB2M "Convert a Vector Register to a Mask" } - {VPMOVD2M "Convert a Vector Register to a Mask" } - {VPMOVDB "Down Convert DWord to Byte" } - {VPMOVDW "Down Convert DWord to Word" } - {VPMOVM2B "Convert a Mask Register to a Vector Register" } - {VPMOVM2D "Convert a Mask Register to a Vector Register" } - {VPMOVM2Q "Convert a Mask Register to a Vector Register" } - {VPMOVM2W "Convert a Mask Register to a Vector Register" } - {VPMOVQ2M "Convert a Vector Register to a Mask" } - {VPMOVQB "Down Convert QWord to Byte" } - {VPMOVQD "Down Convert QWord to DWord" } - {VPMOVQW "Down Convert QWord to Word" } - {VPMOVSDB "Down Convert DWord to Byte" } - {VPMOVSDW "Down Convert DWord to Word" } - {VPMOVSQB "Down Convert QWord to Byte" } - {VPMOVSQD "Down Convert QWord to DWord" } - {VPMOVSQW "Down Convert QWord to Word" } - {VPMOVSWB "Down Convert Word to Byte" } - {VPMOVUSDB "Down Convert DWord to Byte" } - {VPMOVUSDW "Down Convert DWord to Word" } - {VPMOVUSQB "Down Convert QWord to Byte" } - {VPMOVUSQD "Down Convert QWord to DWord" } - {VPMOVUSQW "Down Convert QWord to Word" } - {VPMOVUSWB "Down Convert Word to Byte" } - {VPMOVW2M "Convert a Vector Register to a Mask" } - {VPMOVWB "Down Convert Word to Byte" } - {VPMULTISHIFTQB "Select Packed Unaligned Bytes from Quadword Sources" } - {VPOPCNT "Return the Count of Number of Bits Set to 1 in BYTE/WORD/DWORD/QWORD" } - {VPROLD "Bit Rotate Left" } - {VPROLQ "Bit Rotate Left" } - {VPROLVD "Bit Rotate Left" } - {VPROLVQ "Bit Rotate Left" } - {VPRORD "Bit Rotate Right" } - {VPRORQ "Bit Rotate Right" } - {VPRORVD "Bit Rotate Right" } - {VPRORVQ "Bit Rotate Right" } - {VPSCATTERDD "Scatter Packed Dword, Packed Qword with Signed Dword, Signed Qword Indices" } - {VPSCATTERDQ "Scatter Packed Dword, Packed Qword with Signed Dword, Signed Qword Indices" } - {VPSCATTERQD "Scatter Packed Dword, Packed Qword with Signed Dword, Signed Qword Indices" } - {VPSCATTERQQ "Scatter Packed Dword, Packed Qword with Signed Dword, Signed Qword Indices" } - {VPSHLD "Concatenate and Shift Packed Data Left Logical" } - {VPSHLDV "Concatenate and Variable Shift Packed Data Left Logical" } - {VPSHRD "Concatenate and Shift Packed Data Right Logical" } - {VPSHRDV "Concatenate and Variable Shift Packed Data Right Logical" } - {VPSHUFBITQMB "Shuffle Bits from Quadword Elements Using Byte Indexes into Mask" } - {VPSLLVD "Variable Bit Shift Left Logical" } - {VPSLLVQ "Variable Bit Shift Left Logical" } - {VPSLLVW "Variable Bit Shift Left Logical" } - {VPSRAVD "Variable Bit Shift Right Arithmetic" } - {VPSRAVQ "Variable Bit Shift Right Arithmetic" } - {VPSRAVW "Variable Bit Shift Right Arithmetic" } - {VPSRLVD "Variable Bit Shift Right Logical" } - {VPSRLVQ "Variable Bit Shift Right Logical" } - {VPSRLVW "Variable Bit Shift Right Logical" } - {VPTERNLOGD "Bitwise Ternary Logic" } - {VPTERNLOGQ "Bitwise Ternary Logic" } - {VPTESTMB "Logical AND and Set Mask" } - {VPTESTMD "Logical AND and Set Mask" } - {VPTESTMQ "Logical AND and Set Mask" } - {VPTESTMW "Logical AND and Set Mask" } - {VPTESTNMB "Logical NAND and Set" } - {VPTESTNMD "Logical NAND and Set" } - {VPTESTNMQ "Logical NAND and Set" } - {VPTESTNMW "Logical NAND and Set" } - {VRANGEPD "Range Restriction Calculation For Packed Pairs of Float64 Values" } - {VRANGEPS "Range Restriction Calculation For Packed Pairs of Float32 Values" } - {VRANGESD "Range Restriction Calculation From a pair of Scalar Float64 Values" } - {VRANGESS "Range Restriction Calculation From a Pair of Scalar Float32 Values" } - {VRCP14PD "Compute Approximate Reciprocals of Packed Float64 Values" } - {VRCP14PS "Compute Approximate Reciprocals of Packed Float32 Values" } - {VRCP14SD "Compute Approximate Reciprocal of Scalar Float64 Value" } - {VRCP14SS "Compute Approximate Reciprocal of Scalar Float32 Value" } - {VREDUCEPD "Perform Reduction Transformation on Packed Float64 Values" } - {VREDUCEPS "Perform Reduction Transformation on Packed Float32 Values" } - {VREDUCESD "Perform a Reduction Transformation on a Scalar Float64 Value" } - {VREDUCESS "Perform a Reduction Transformation on a Scalar Float32 Value" } - {VRNDSCALEPD "Round Packed Float64 Values To Include A Given Number Of Fraction Bits" } - {VRNDSCALEPS "Round Packed Float32 Values To Include A Given Number Of Fraction Bits" } - {VRNDSCALESD "Round Scalar Float64 Value To Include A Given Number Of Fraction Bits" } - {VRNDSCALESS "Round Scalar Float32 Value To Include A Given Number Of Fraction Bits" } - {VRSQRT14PD "Compute Approximate Reciprocals of Square Roots of Packed Float64 Values" } - {VRSQRT14PS "Compute Approximate Reciprocals of Square Roots of Packed Float32 Values" } - {VRSQRT14SD "Compute Approximate Reciprocal of Square Root of Scalar Float64 Value" } - {VRSQRT14SS "Compute Approximate Reciprocal of Square Root of Scalar Float32 Value" } - {VSCALEFPD "Scale Packed Float64 Values With Float64 Values" } - {VSCALEFPS "Scale Packed Float32 Values With Float32 Values" } - {VSCALEFSD "Scale Scalar Float64 Values With Float64 Values" } - {VSCALEFSS "Scale Scalar Float32 Value With Float32 Value" } - {VSCATTERDPD "Scatter Packed Single, Packed Double with Signed Dword and Qword Indices" } - {VSCATTERDPS "Scatter Packed Single, Packed Double with Signed Dword and Qword Indices" } - {VSCATTERQPD "Scatter Packed Single, Packed Double with Signed Dword and Qword Indices" } - {VSCATTERQPS "Scatter Packed Single, Packed Double with Signed Dword and Qword Indices" } - {VSHUFF32x4 "Shuffle Packed Values at 128-bit Granularity" } - {VSHUFF64x2 "Shuffle Packed Values at 128-bit Granularity" } - {VSHUFI32x4 "Shuffle Packed Values at 128-bit Granularity" } - {VSHUFI64x2 "Shuffle Packed Values at 128-bit Granularity" } - {VTESTPD "Packed Bit Test" } - {VTESTPS "Packed Bit Test" } - {VZEROALL "Zero XMM, YMM and ZMM Registers" } - {VZEROUPPER "Zero Upper Bits of YMM and ZMM Registers" } - {WAIT "Wait" } - {WBINVD "Write Back and Invalidate Cache" } - {WBNOINVD "Write Back and Do Not Invalidate Cache" } - {WRFSBASE "Write FS/GS Segment Base" } - {WRGSBASE "Write FS/GS Segment Base" } - {WRMSR "Write to Model Specific Register" } - {WRPKRU "Write Data to User Page Key Register" } - {WRSSD "Write to Shadow Stack" } - {WRSSQ "Write to Shadow Stack" } - {WRUSSD "Write to User Shadow Stack" } - {WRUSSQ "Write to User Shadow Stack" } - {XABORT "Transactional Abort" } - {XACQUIRE "Hardware Lock Elision Prefix Hints" } - {XADD "Exchange and Add" } - {XBEGIN "Transactional Begin" } - {XCHG "Exchange Register/Memory with Register" } - {XEND "Transactional End" } - {XGETBV "Get Value of Extended Control Register" } - {XLAT "Table Look-up Translation" } - {XLATB "Table Look-up Translation" } - {XOR "Logical Exclusive OR" } - {XORPD "Bitwise Logical XOR of Packed Double Precision Floating-Point Values" } - {XORPS "Bitwise Logical XOR of Packed Single Precision Floating-Point Values" } - {XRELEASE "Hardware Lock Elision Prefix Hints" } - {XRSTOR "Restore Processor Extended States" } - {XRSTORS "Restore Processor Extended States Supervisor" } - {XSAVE "Save Processor Extended States" } - {XSAVEC "Save Processor Extended States with Compaction" } - {XSAVEOPT "Save Processor Extended States Optimized" } - {XSAVES "Save Processor Extended States Supervisor" } - {XSETBV "Set Extended Control Register" } - {XTEST "Test If In Transactional Execution" } - - //- rjf: sgx - {ENCLS "Execute an Enclave System Function of Specified Leaf Number" } - {ENCLS "[EADD] Add a Page to an Uninitialized Enclave" } - {ENCLS "[EAUG] Add a Page to an Initialized Enclave" } - {ENCLS "[EBLOCK] Mark a page in EPC as Blocked" } - {ENCLS "[ECREATE] Create an SECS page in the Enclave Page Cache" } - {ENCLS "[EDBGRD] Read From a Debug Enclave" } - {ENCLS "[EDBGWR] Write to a Debug Enclave" } - {ENCLS "[EEXTEND] Extend Uninitialized Enclave Measurement by 256 Bytes" } - {ENCLS "[EINIT] Initialize an Enclave for Execution" } - {ENCLS "[ELDBC] Load an EPC Page and Mark its State" } - {ENCLS "[ELDB] Load an EPC Page and Mark its State" } - {ENCLS "[ELDUC] Load an EPC Page and Mark its State" } - {ENCLS "[ELDU] Load an EPC Page and Mark its State" } - {ENCLS "[EMODPR] Restrict the Permissions of an EPC Page" } - {ENCLS "[EMODT] Change the Type of an EPC Page" } - {ENCLS "[EPA] Add Version Array" } - {ENCLS "[ERDINFO] Read Type and Status Information About an EPC Page" } - {ENCLS "[EREMOVE] Remove a page from the EPC" } - {ENCLS "[ETRACKC] Activates EBLOCK Checks" } - {ENCLS "[ETRACK] Activates EBLOCK Checks" } - {ENCLS "[EWB] Invalidate an EPC Page and Write out to Main Memory" } - {ENCLU "Execute an Enclave User Function of Specified Leaf Number" } - {ENCLU "[EACCEPTCOPY] Initialize a Pending Page" } - {ENCLU "[EACCEPT] Accept Changes to an EPC Page" } - {ENCLU "[EENTER] Enters an Enclave" } - {ENCLU "[EEXIT] Exits an Enclave" } - {ENCLU "[EGETKEY] Retrieves a Cryptographic Key" } - {ENCLU "[EMODPE] Extend an EPC Page Permissions" } - {ENCLU "[EREPORT] Create a Cryptographic Report of the Enclave" } - {ENCLU "[ERESUME] Re-Enters an Enclave" } - {ENCLV "Execute an Enclave VMM Function of Specified Leaf Number" } - - //- rjf: vmx - {INVEPT "Invalidate Translations Derived from EPT" } - {INVVPID "Invalidate Translations Based on VPID" } - {VMCALL "Call to VM Monitor" } - {VMCLEAR "Clear Virtual-Machine Control Structure" } - {VMFUNC "Invoke VM function" } - {VMLAUNCH "Launch/Resume Virtual Machine" } - {VMPTRLD "Load Pointer to Virtual-Machine Control Structure" } - {VMPTRST "Store Pointer to Virtual-Machine Control Structure" } - {VMREAD "Read Field from Virtual-Machine Control Structure" } - {VMRESUME "Launch/Resume Virtual Machine" } - {VMWRITE "Write Field to Virtual-Machine Control Structure" } - {VMXOFF "Leave VMX Operation" } - {VMXON "Enter VMX Operation" } - - //- rjf: xeon phi - {PREFETCHWT1 "Prefetch Vector Data Into Caches with Intent to Write and T1 Hint" } - {V4FMADDPS "Packed Single-Precision Floating-Point Fused Multiply-Add (4-iterations)" } - {V4FMADDSS "Scalar Single-Precision Floating-Point Fused Multiply-Add (4-iterations)" } - {V4FNMADDPS "Packed Single-Precision Floating-Point Fused Multiply-Add (4-iterations)" } - {V4FNMADDSS "Scalar Single-Precision Floating-Point Fused Multiply-Add (4-iterations)" } - {VEXP2PD "Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error"} - {VEXP2PS "Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error"} - {VGATHERPF0DPD "Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint" } - {VGATHERPF0DPS "Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint" } - {VGATHERPF0QPD "Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint" } - {VGATHERPF0QPS "Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint" } - {VGATHERPF1DPD "Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint" } - {VGATHERPF1DPS "Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint" } - {VGATHERPF1QPD "Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint" } - {VGATHERPF1QPS "Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint" } - {VP4DPWSSD "Dot Product of Signed Words with Dword Accumulation (4-iterations)" } - {VP4DPWSSDS "Dot Product of Signed Words with Dword Accumulation and Saturation (4-iterations)" } - {VRCP28PD "Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error" } - {VRCP28PS "Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error" } - {VRCP28SD "Approximation to the Reciprocal of Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error" } - {VRCP28SS "Approximation to the Reciprocal of Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error" } - {VRSQRT28PD "Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error"} - {VRSQRT28PS "Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error"} - {VRSQRT28SD "Approximation to the Reciprocal Square Root of Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error"} - {VRSQRT28SS "Approximation to the Reciprocal Square Root of Scalar Single-Precision Floating- Point Value with Less Than 2^-28 Relative Error"} - {VSCATTERPF0DPD "Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write" } - {VSCATTERPF0DPS "Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write" } - {VSCATTERPF0QPD "Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write" } - {VSCATTERPF0QPS "Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write" } - {VSCATTERPF1DPD "Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write" } - {VSCATTERPF1DPS "Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write" } - {VSCATTERPF1QPD "Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write" } - {VSCATTERPF1QPS "Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write" } - -} - //////////////////////////////// //~ rjf: Developer Toggles @@ -1844,18 +759,6 @@ DF_DevToggleTable: @expand(DF_IconTable a) `str8_lit_comp("$(a.text)")`; } -//- rjf: instruction metadata table - -@gen -{ - ``; - `struct{String8 mnemonic; String8 summary;} df_g_inst_table_x64[] =`; - `{`; - @expand(DF_InstTableX64 a) `{str8_lit_comp("$(a.name)"), str8_lit_comp("$(a.summary)")},`; - `};`; - ``; -} - //- rjf: developer toggles @gen diff --git a/src/df/core/generated/df_core.meta.h b/src/df/core/generated/df_core.meta.h index 045f9737..dc27b9c5 100644 --- a/src/df/core/generated/df_core.meta.h +++ b/src/df/core/generated/df_core.meta.h @@ -438,1079 +438,6 @@ DF_CORE_VIEW_RULE_VIZ_BLOCK_PROD_FUNCTION_DEF(disasm); DF_CORE_VIEW_RULE_VIZ_BLOCK_PROD_FUNCTION_DEF(graph); DF_CORE_VIEW_RULE_VIZ_BLOCK_PROD_FUNCTION_DEF(bitmap); DF_CORE_VIEW_RULE_VIZ_BLOCK_PROD_FUNCTION_DEF(geo); - -struct{String8 mnemonic; String8 summary;} df_g_inst_table_x64[] = -{ -{str8_lit_comp("AAA"), str8_lit_comp("ASCII Adjust After Addition")}, -{str8_lit_comp("AAD"), str8_lit_comp("ASCII Adjust AX Before Division")}, -{str8_lit_comp("AAM"), str8_lit_comp("ASCII Adjust AX After Multiply")}, -{str8_lit_comp("AAS"), str8_lit_comp("ASCII Adjust AL After Subtraction")}, -{str8_lit_comp("ADC"), str8_lit_comp("Add with Carry")}, -{str8_lit_comp("ADCX"), str8_lit_comp("Unsigned Integer Addition of Two Operands with Carry Flag")}, -{str8_lit_comp("ADD"), str8_lit_comp("Add")}, -{str8_lit_comp("ADDPD"), str8_lit_comp("Add Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("ADDPS"), str8_lit_comp("Add Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("ADDSD"), str8_lit_comp("Add Scalar Double-Precision Floating-Point Values")}, -{str8_lit_comp("ADDSS"), str8_lit_comp("Add Scalar Single-Precision Floating-Point Values")}, -{str8_lit_comp("ADDSUBPD"), str8_lit_comp("Packed Double-FP Add/Subtract")}, -{str8_lit_comp("ADDSUBPS"), str8_lit_comp("Packed Single-FP Add/Subtract")}, -{str8_lit_comp("ADOX"), str8_lit_comp("Unsigned Integer Addition of Two Operands with Overflow Flag")}, -{str8_lit_comp("AESDEC"), str8_lit_comp("Perform One Round of an AES Decryption Flow")}, -{str8_lit_comp("AESDEC128KL"), str8_lit_comp("Perform Ten Rounds of AES Decryption Flow with Key Locker Using 128-Bit Key")}, -{str8_lit_comp("AESDEC256KL"), str8_lit_comp("Perform 14 Rounds of AES Decryption Flow with Key Locker Using 256-Bit Key")}, -{str8_lit_comp("AESDECLAST"), str8_lit_comp("Perform Last Round of an AES Decryption Flow")}, -{str8_lit_comp("AESDECWIDE128KL"), str8_lit_comp("Perform Ten Rounds of AES Decryption Flow with Key Locker on 8 Blocks Using 128-Bit Key")}, -{str8_lit_comp("AESDECWIDE256KL"), str8_lit_comp("Perform 14 Rounds of AES Decryption Flow with Key Locker on 8 Blocks Using 256-Bit Key")}, -{str8_lit_comp("AESENC"), str8_lit_comp("Perform One Round of an AES Encryption Flow")}, -{str8_lit_comp("AESENC128KL"), str8_lit_comp("Perform Ten Rounds of AES Encryption Flow with Key Locker Using 128-Bit Key")}, -{str8_lit_comp("AESENC256KL"), str8_lit_comp("Perform 14 Rounds of AES Encryption Flow with Key Locker Using 256-Bit Key")}, -{str8_lit_comp("AESENCLAST"), str8_lit_comp("Perform Last Round of an AES Encryption Flow")}, -{str8_lit_comp("AESENCWIDE128KL"), str8_lit_comp("Perform Ten Rounds of AES Encryption Flow with Key Locker on 8 Blocks Using 128-Bit Key")}, -{str8_lit_comp("AESENCWIDE256KL"), str8_lit_comp("Perform 14 Rounds of AES Encryption Flow with Key Locker on 8 Blocks Using 256-Bit Key")}, -{str8_lit_comp("AESIMC"), str8_lit_comp("Perform the AES InvMixColumn Transformation")}, -{str8_lit_comp("AESKEYGENASSIST"), str8_lit_comp("AES Round Key Generation Assist")}, -{str8_lit_comp("AND"), str8_lit_comp("Logical AND")}, -{str8_lit_comp("ANDN"), str8_lit_comp("Logical AND NOT")}, -{str8_lit_comp("ANDNPD"), str8_lit_comp("Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values")}, -{str8_lit_comp("ANDNPS"), str8_lit_comp("Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values")}, -{str8_lit_comp("ANDPD"), str8_lit_comp("Bitwise Logical AND of Packed Double Precision Floating-Point Values")}, -{str8_lit_comp("ANDPS"), str8_lit_comp("Bitwise Logical AND of Packed Single Precision Floating-Point Values")}, -{str8_lit_comp("ARPL"), str8_lit_comp("Adjust RPL Field of Segment Selector")}, -{str8_lit_comp("BEXTR"), str8_lit_comp("Bit Field Extract")}, -{str8_lit_comp("BLENDPD"), str8_lit_comp("Blend Packed Double Precision Floating-Point Values")}, -{str8_lit_comp("BLENDPS"), str8_lit_comp("Blend Packed Single Precision Floating-Point Values")}, -{str8_lit_comp("BLENDVPD"), str8_lit_comp("Variable Blend Packed Double Precision Floating-Point Values")}, -{str8_lit_comp("BLENDVPS"), str8_lit_comp("Variable Blend Packed Single Precision Floating-Point Values")}, -{str8_lit_comp("BLSI"), str8_lit_comp("Extract Lowest Set Isolated Bit")}, -{str8_lit_comp("BLSMSK"), str8_lit_comp("Get Mask Up to Lowest Set Bit")}, -{str8_lit_comp("BLSR"), str8_lit_comp("Reset Lowest Set Bit")}, -{str8_lit_comp("BNDCL"), str8_lit_comp("Check Lower Bound")}, -{str8_lit_comp("BNDCN"), str8_lit_comp("Check Upper Bound")}, -{str8_lit_comp("BNDCU"), str8_lit_comp("Check Upper Bound")}, -{str8_lit_comp("BNDLDX"), str8_lit_comp("Load Extended Bounds Using Address Translation")}, -{str8_lit_comp("BNDMK"), str8_lit_comp("Make Bounds")}, -{str8_lit_comp("BNDMOV"), str8_lit_comp("Move Bounds")}, -{str8_lit_comp("BNDSTX"), str8_lit_comp("Store Extended Bounds Using Address Translation")}, -{str8_lit_comp("BOUND"), str8_lit_comp("Check Array Index Against Bounds")}, -{str8_lit_comp("BSF"), str8_lit_comp("Bit Scan Forward")}, -{str8_lit_comp("BSR"), str8_lit_comp("Bit Scan Reverse")}, -{str8_lit_comp("BSWAP"), str8_lit_comp("Byte Swap")}, -{str8_lit_comp("BT"), str8_lit_comp("Bit Test")}, -{str8_lit_comp("BTC"), str8_lit_comp("Bit Test and Complement")}, -{str8_lit_comp("BTR"), str8_lit_comp("Bit Test and Reset")}, -{str8_lit_comp("BTS"), str8_lit_comp("Bit Test and Set")}, -{str8_lit_comp("BZHI"), str8_lit_comp("Zero High Bits Starting with Specified Bit Position")}, -{str8_lit_comp("CALL"), str8_lit_comp("Call Procedure")}, -{str8_lit_comp("CBW"), str8_lit_comp("Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword")}, -{str8_lit_comp("CDQ"), str8_lit_comp("Convert Word to Doubleword/Convert Doubleword to Quadword")}, -{str8_lit_comp("CDQE"), str8_lit_comp("Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword")}, -{str8_lit_comp("CLAC"), str8_lit_comp("Clear AC Flag in EFLAGS Register")}, -{str8_lit_comp("CLC"), str8_lit_comp("Clear Carry Flag")}, -{str8_lit_comp("CLD"), str8_lit_comp("Clear Direction Flag")}, -{str8_lit_comp("CLDEMOTE"), str8_lit_comp("Cache Line Demote")}, -{str8_lit_comp("CLFLUSH"), str8_lit_comp("Flush Cache Line")}, -{str8_lit_comp("CLFLUSHOPT"), str8_lit_comp("Flush Cache Line Optimized")}, -{str8_lit_comp("CLI"), str8_lit_comp("Clear Interrupt Flag")}, -{str8_lit_comp("CLRSSBSY"), str8_lit_comp("Clear Busy Flag in a Supervisor Shadow Stack Token")}, -{str8_lit_comp("CLTS"), str8_lit_comp("Clear Task-Switched Flag in CR0")}, -{str8_lit_comp("CLWB"), str8_lit_comp("Cache Line Write Back")}, -{str8_lit_comp("CMC"), str8_lit_comp("Complement Carry Flag")}, -{str8_lit_comp("CMOVcc"), str8_lit_comp("Conditional Move")}, -{str8_lit_comp("CMP"), str8_lit_comp("Compare Two Operands")}, -{str8_lit_comp("CMPPD"), str8_lit_comp("Compare Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("CMPPS"), str8_lit_comp("Compare Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("CMPS"), str8_lit_comp("Compare String Operands")}, -{str8_lit_comp("CMPSB"), str8_lit_comp("Compare String Operands")}, -{str8_lit_comp("CMPSD"), str8_lit_comp("Compare String Operands")}, -{str8_lit_comp("CMPSQ"), str8_lit_comp("Compare String Operands")}, -{str8_lit_comp("CMPSS"), str8_lit_comp("Compare Scalar Single-Precision Floating-Point Value")}, -{str8_lit_comp("CMPSW"), str8_lit_comp("Compare String Operands")}, -{str8_lit_comp("CMPXCHG"), str8_lit_comp("Compare and Exchange")}, -{str8_lit_comp("CMPXCHG16B"), str8_lit_comp("Compare and Exchange Bytes")}, -{str8_lit_comp("CMPXCHG8B"), str8_lit_comp("Compare and Exchange Bytes")}, -{str8_lit_comp("COMISD"), str8_lit_comp("Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS")}, -{str8_lit_comp("COMISS"), str8_lit_comp("Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS")}, -{str8_lit_comp("CPUID"), str8_lit_comp("CPU Identification")}, -{str8_lit_comp("CQO"), str8_lit_comp("Convert Word to Doubleword/Convert Doubleword to Quadword")}, -{str8_lit_comp("CRC32"), str8_lit_comp("Accumulate CRC32 Value")}, -{str8_lit_comp("CVTDQ2PD"), str8_lit_comp("Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("CVTDQ2PS"), str8_lit_comp("Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("CVTPD2DQ"), str8_lit_comp("Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers")}, -{str8_lit_comp("CVTPD2PI"), str8_lit_comp("Convert Packed Double-Precision FP Values to Packed Dword Integers")}, -{str8_lit_comp("CVTPD2PS"), str8_lit_comp("Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("CVTPI2PD"), str8_lit_comp("Convert Packed Dword Integers to Packed Double-Precision FP Values")}, -{str8_lit_comp("CVTPI2PS"), str8_lit_comp("Convert Packed Dword Integers to Packed Single-Precision FP Values")}, -{str8_lit_comp("CVTPS2DQ"), str8_lit_comp("Convert Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values")}, -{str8_lit_comp("CVTPS2PD"), str8_lit_comp("Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("CVTPS2PI"), str8_lit_comp("Convert Packed Single-Precision FP Values to Packed Dword Integers")}, -{str8_lit_comp("CVTSD2SI"), str8_lit_comp("Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer")}, -{str8_lit_comp("CVTSD2SS"), str8_lit_comp("Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value")}, -{str8_lit_comp("CVTSI2SD"), str8_lit_comp("Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value")}, -{str8_lit_comp("CVTSI2SS"), str8_lit_comp("Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value")}, -{str8_lit_comp("CVTSS2SD"), str8_lit_comp("Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value")}, -{str8_lit_comp("CVTSS2SI"), str8_lit_comp("Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer")}, -{str8_lit_comp("CVTTPD2DQ"), str8_lit_comp("Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers")}, -{str8_lit_comp("CVTTPD2PI"), str8_lit_comp("Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers")}, -{str8_lit_comp("CVTTPS2DQ"), str8_lit_comp("Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values")}, -{str8_lit_comp("CVTTPS2PI"), str8_lit_comp("Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers")}, -{str8_lit_comp("CVTTSD2SI"), str8_lit_comp("Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed Integer")}, -{str8_lit_comp("CVTTSS2SI"), str8_lit_comp("Convert with Truncation Scalar Single-Precision Floating-Point Value to Integer")}, -{str8_lit_comp("CWD"), str8_lit_comp("Convert Word to Doubleword/Convert Doubleword to Quadword")}, -{str8_lit_comp("CWDE"), str8_lit_comp("Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword")}, -{str8_lit_comp("DAA"), str8_lit_comp("Decimal Adjust AL after Addition")}, -{str8_lit_comp("DAS"), str8_lit_comp("Decimal Adjust AL after Subtraction")}, -{str8_lit_comp("DEC"), str8_lit_comp("Decrement by 1")}, -{str8_lit_comp("DIV"), str8_lit_comp("Unsigned Divide")}, -{str8_lit_comp("DIVPD"), str8_lit_comp("Divide Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("DIVPS"), str8_lit_comp("Divide Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("DIVSD"), str8_lit_comp("Divide Scalar Double-Precision Floating-Point Value")}, -{str8_lit_comp("DIVSS"), str8_lit_comp("Divide Scalar Single-Precision Floating-Point Values")}, -{str8_lit_comp("DPPD"), str8_lit_comp("Dot Product of Packed Double Precision Floating-Point Values")}, -{str8_lit_comp("DPPS"), str8_lit_comp("Dot Product of Packed Single Precision Floating-Point Values")}, -{str8_lit_comp("EMMS"), str8_lit_comp("Empty MMX Technology State")}, -{str8_lit_comp("ENCODEKEY128"), str8_lit_comp("Encode 128-Bit Key with Key Locker")}, -{str8_lit_comp("ENCODEKEY256"), str8_lit_comp("Encode 256-Bit Key with Key Locker")}, -{str8_lit_comp("ENDBR32"), str8_lit_comp("Terminate an Indirect Branch in 32-bit and Compatibility Mode")}, -{str8_lit_comp("ENDBR64"), str8_lit_comp("Terminate an Indirect Branch in 64-bit Mode")}, -{str8_lit_comp("ENTER"), str8_lit_comp("Make Stack Frame for Procedure Parameters")}, -{str8_lit_comp("EXTRACTPS"), str8_lit_comp("Extract Packed Floating-Point Values")}, -{str8_lit_comp("F2XM1"), str8_lit_comp("Compute 2x–1")}, -{str8_lit_comp("FABS"), str8_lit_comp("Absolute Value")}, -{str8_lit_comp("FADD"), str8_lit_comp("Add")}, -{str8_lit_comp("FADDP"), str8_lit_comp("Add")}, -{str8_lit_comp("FBLD"), str8_lit_comp("Load Binary Coded Decimal")}, -{str8_lit_comp("FBSTP"), str8_lit_comp("Store BCD Integer and Pop")}, -{str8_lit_comp("FCHS"), str8_lit_comp("Change Sign")}, -{str8_lit_comp("FCLEX"), str8_lit_comp("Clear Exceptions")}, -{str8_lit_comp("FCMOVcc"), str8_lit_comp("Floating-Point Conditional Move")}, -{str8_lit_comp("FCOM"), str8_lit_comp("Compare Floating Point Values")}, -{str8_lit_comp("FCOMI"), str8_lit_comp("Compare Floating Point Values and Set EFLAGS")}, -{str8_lit_comp("FCOMIP"), str8_lit_comp("Compare Floating Point Values and Set EFLAGS")}, -{str8_lit_comp("FCOMP"), str8_lit_comp("Compare Floating Point Values")}, -{str8_lit_comp("FCOMPP"), str8_lit_comp("Compare Floating Point Values")}, -{str8_lit_comp("FCOS"), str8_lit_comp("Cosine")}, -{str8_lit_comp("FDECSTP"), str8_lit_comp("Decrement Stack-Top Pointer")}, -{str8_lit_comp("FDIV"), str8_lit_comp("Divide")}, -{str8_lit_comp("FDIVP"), str8_lit_comp("Divide")}, -{str8_lit_comp("FDIVR"), str8_lit_comp("Reverse Divide")}, -{str8_lit_comp("FDIVRP"), str8_lit_comp("Reverse Divide")}, -{str8_lit_comp("FFREE"), str8_lit_comp("Free Floating-Point Register")}, -{str8_lit_comp("FIADD"), str8_lit_comp("Add")}, -{str8_lit_comp("FICOM"), str8_lit_comp("Compare Integer")}, -{str8_lit_comp("FICOMP"), str8_lit_comp("Compare Integer")}, -{str8_lit_comp("FIDIV"), str8_lit_comp("Divide")}, -{str8_lit_comp("FIDIVR"), str8_lit_comp("Reverse Divide")}, -{str8_lit_comp("FILD"), str8_lit_comp("Load Integer")}, -{str8_lit_comp("FIMUL"), str8_lit_comp("Multiply")}, -{str8_lit_comp("FINCSTP"), str8_lit_comp("Increment Stack-Top Pointer")}, -{str8_lit_comp("FINIT"), str8_lit_comp("Initialize Floating-Point Unit")}, -{str8_lit_comp("FIST"), str8_lit_comp("Store Integer")}, -{str8_lit_comp("FISTP"), str8_lit_comp("Store Integer")}, -{str8_lit_comp("FISTTP"), str8_lit_comp("Store Integer with Truncation")}, -{str8_lit_comp("FISUB"), str8_lit_comp("Subtract")}, -{str8_lit_comp("FISUBR"), str8_lit_comp("Reverse Subtract")}, -{str8_lit_comp("FLD"), str8_lit_comp("Load Floating Point Value")}, -{str8_lit_comp("FLD1"), str8_lit_comp("Load Constant")}, -{str8_lit_comp("FLDCW"), str8_lit_comp("Load x87 FPU Control Word")}, -{str8_lit_comp("FLDENV"), str8_lit_comp("Load x87 FPU Environment")}, -{str8_lit_comp("FLDL2E"), str8_lit_comp("Load Constant")}, -{str8_lit_comp("FLDL2T"), str8_lit_comp("Load Constant")}, -{str8_lit_comp("FLDLG2"), str8_lit_comp("Load Constant")}, -{str8_lit_comp("FLDLN2"), str8_lit_comp("Load Constant")}, -{str8_lit_comp("FLDPI"), str8_lit_comp("Load Constant")}, -{str8_lit_comp("FLDZ"), str8_lit_comp("Load Constant")}, -{str8_lit_comp("FMUL"), str8_lit_comp("Multiply")}, -{str8_lit_comp("FMULP"), str8_lit_comp("Multiply")}, -{str8_lit_comp("FNCLEX"), str8_lit_comp("Clear Exceptions")}, -{str8_lit_comp("FNINIT"), str8_lit_comp("Initialize Floating-Point Unit")}, -{str8_lit_comp("FNOP"), str8_lit_comp("No Operation")}, -{str8_lit_comp("FNSAVE"), str8_lit_comp("Store x87 FPU State")}, -{str8_lit_comp("FNSTCW"), str8_lit_comp("Store x87 FPU Control Word")}, -{str8_lit_comp("FNSTENV"), str8_lit_comp("Store x87 FPU Environment")}, -{str8_lit_comp("FNSTSW"), str8_lit_comp("Store x87 FPU Status Word")}, -{str8_lit_comp("FPATAN"), str8_lit_comp("Partial Arctangent")}, -{str8_lit_comp("FPREM"), str8_lit_comp("Partial Remainder")}, -{str8_lit_comp("FPREM1"), str8_lit_comp("Partial Remainder")}, -{str8_lit_comp("FPTAN"), str8_lit_comp("Partial Tangent")}, -{str8_lit_comp("FRNDINT"), str8_lit_comp("Round to Integer")}, -{str8_lit_comp("FRSTOR"), str8_lit_comp("Restore x87 FPU State")}, -{str8_lit_comp("FSAVE"), str8_lit_comp("Store x87 FPU State")}, -{str8_lit_comp("FSCALE"), str8_lit_comp("Scale")}, -{str8_lit_comp("FSIN"), str8_lit_comp("Sine")}, -{str8_lit_comp("FSINCOS"), str8_lit_comp("Sine and Cosine")}, -{str8_lit_comp("FSQRT"), str8_lit_comp("Square Root")}, -{str8_lit_comp("FST"), str8_lit_comp("Store Floating Point Value")}, -{str8_lit_comp("FSTCW"), str8_lit_comp("Store x87 FPU Control Word")}, -{str8_lit_comp("FSTENV"), str8_lit_comp("Store x87 FPU Environment")}, -{str8_lit_comp("FSTP"), str8_lit_comp("Store Floating Point Value")}, -{str8_lit_comp("FSTSW"), str8_lit_comp("Store x87 FPU Status Word")}, -{str8_lit_comp("FSUB"), str8_lit_comp("Subtract")}, -{str8_lit_comp("FSUBP"), str8_lit_comp("Subtract")}, -{str8_lit_comp("FSUBR"), str8_lit_comp("Reverse Subtract")}, -{str8_lit_comp("FSUBRP"), str8_lit_comp("Reverse Subtract")}, -{str8_lit_comp("FTST"), str8_lit_comp("TEST")}, -{str8_lit_comp("FUCOM"), str8_lit_comp("Unordered Compare Floating Point Values")}, -{str8_lit_comp("FUCOMI"), str8_lit_comp("Compare Floating Point Values and Set EFLAGS")}, -{str8_lit_comp("FUCOMIP"), str8_lit_comp("Compare Floating Point Values and Set EFLAGS")}, -{str8_lit_comp("FUCOMP"), str8_lit_comp("Unordered Compare Floating Point Values")}, -{str8_lit_comp("FUCOMPP"), str8_lit_comp("Unordered Compare Floating Point Values")}, -{str8_lit_comp("FWAIT"), str8_lit_comp("Wait")}, -{str8_lit_comp("FXAM"), str8_lit_comp("Examine Floating-Point")}, -{str8_lit_comp("FXCH"), str8_lit_comp("Exchange Register Contents")}, -{str8_lit_comp("FXRSTOR"), str8_lit_comp("Restore x87 FPU, MMX, XMM, and MXCSR State")}, -{str8_lit_comp("FXSAVE"), str8_lit_comp("Save x87 FPU, MMX Technology, and SSE State")}, -{str8_lit_comp("FXTRACT"), str8_lit_comp("Extract Exponent and Significand")}, -{str8_lit_comp("FYL2X"), str8_lit_comp("Compute y * log2x")}, -{str8_lit_comp("FYL2XP1"), str8_lit_comp("Compute y * log2(x +1)")}, -{str8_lit_comp("GF2P8AFFINEINVQB"), str8_lit_comp("Galois Field Affine Transformation Inverse")}, -{str8_lit_comp("GF2P8AFFINEQB"), str8_lit_comp("Galois Field Affine Transformation")}, -{str8_lit_comp("GF2P8MULB"), str8_lit_comp("Galois Field Multiply Bytes")}, -{str8_lit_comp("HADDPD"), str8_lit_comp("Packed Double-FP Horizontal Add")}, -{str8_lit_comp("HADDPS"), str8_lit_comp("Packed Single-FP Horizontal Add")}, -{str8_lit_comp("HLT"), str8_lit_comp("Halt")}, -{str8_lit_comp("HRESET"), str8_lit_comp("History Reset")}, -{str8_lit_comp("HSUBPD"), str8_lit_comp("Packed Double-FP Horizontal Subtract")}, -{str8_lit_comp("HSUBPS"), str8_lit_comp("Packed Single-FP Horizontal Subtract")}, -{str8_lit_comp("IDIV"), str8_lit_comp("Signed Divide")}, -{str8_lit_comp("IMUL"), str8_lit_comp("Signed Multiply")}, -{str8_lit_comp("IN"), str8_lit_comp("Input from Port")}, -{str8_lit_comp("INC"), str8_lit_comp("Increment by 1")}, -{str8_lit_comp("INCSSPD"), str8_lit_comp("Increment Shadow Stack Pointer")}, -{str8_lit_comp("INCSSPQ"), str8_lit_comp("Increment Shadow Stack Pointer")}, -{str8_lit_comp("INS"), str8_lit_comp("Input from Port to String")}, -{str8_lit_comp("INSB"), str8_lit_comp("Input from Port to String")}, -{str8_lit_comp("INSD"), str8_lit_comp("Input from Port to String")}, -{str8_lit_comp("INSERTPS"), str8_lit_comp("Insert Scalar Single-Precision Floating-Point Value")}, -{str8_lit_comp("INSW"), str8_lit_comp("Input from Port to String")}, -{str8_lit_comp("INT"), str8_lit_comp("Call to Interrupt Procedure")}, -{str8_lit_comp("INT1"), str8_lit_comp("Call to Interrupt Procedure")}, -{str8_lit_comp("INT3"), str8_lit_comp("Call to Interrupt Procedure")}, -{str8_lit_comp("INTO"), str8_lit_comp("Call to Interrupt Procedure")}, -{str8_lit_comp("INVD"), str8_lit_comp("Invalidate Internal Caches")}, -{str8_lit_comp("INVLPG"), str8_lit_comp("Invalidate TLB Entries")}, -{str8_lit_comp("INVPCID"), str8_lit_comp("Invalidate Process-Context Identifier")}, -{str8_lit_comp("IRET"), str8_lit_comp("Interrupt Return")}, -{str8_lit_comp("IRETD"), str8_lit_comp("Interrupt Return")}, -{str8_lit_comp("IRETQ"), str8_lit_comp("Interrupt Return")}, -{str8_lit_comp("JMP"), str8_lit_comp("Jump")}, -{str8_lit_comp("Jcc"), str8_lit_comp("Jump if Condition Is Met")}, -{str8_lit_comp("KADDB"), str8_lit_comp("ADD Two Masks")}, -{str8_lit_comp("KADDD"), str8_lit_comp("ADD Two Masks")}, -{str8_lit_comp("KADDQ"), str8_lit_comp("ADD Two Masks")}, -{str8_lit_comp("KADDW"), str8_lit_comp("ADD Two Masks")}, -{str8_lit_comp("KANDB"), str8_lit_comp("Bitwise Logical AND Masks")}, -{str8_lit_comp("KANDD"), str8_lit_comp("Bitwise Logical AND Masks")}, -{str8_lit_comp("KANDNB"), str8_lit_comp("Bitwise Logical AND NOT Masks")}, -{str8_lit_comp("KANDND"), str8_lit_comp("Bitwise Logical AND NOT Masks")}, -{str8_lit_comp("KANDNQ"), str8_lit_comp("Bitwise Logical AND NOT Masks")}, -{str8_lit_comp("KANDNW"), str8_lit_comp("Bitwise Logical AND NOT Masks")}, -{str8_lit_comp("KANDQ"), str8_lit_comp("Bitwise Logical AND Masks")}, -{str8_lit_comp("KANDW"), str8_lit_comp("Bitwise Logical AND Masks")}, -{str8_lit_comp("KMOVB"), str8_lit_comp("Move from and to Mask Registers")}, -{str8_lit_comp("KMOVD"), str8_lit_comp("Move from and to Mask Registers")}, -{str8_lit_comp("KMOVQ"), str8_lit_comp("Move from and to Mask Registers")}, -{str8_lit_comp("KMOVW"), str8_lit_comp("Move from and to Mask Registers")}, -{str8_lit_comp("KNOTB"), str8_lit_comp("NOT Mask Register")}, -{str8_lit_comp("KNOTD"), str8_lit_comp("NOT Mask Register")}, -{str8_lit_comp("KNOTQ"), str8_lit_comp("NOT Mask Register")}, -{str8_lit_comp("KNOTW"), str8_lit_comp("NOT Mask Register")}, -{str8_lit_comp("KORB"), str8_lit_comp("Bitwise Logical OR Masks")}, -{str8_lit_comp("KORD"), str8_lit_comp("Bitwise Logical OR Masks")}, -{str8_lit_comp("KORQ"), str8_lit_comp("Bitwise Logical OR Masks")}, -{str8_lit_comp("KORTESTB"), str8_lit_comp("OR Masks And Set Flags")}, -{str8_lit_comp("KORTESTD"), str8_lit_comp("OR Masks And Set Flags")}, -{str8_lit_comp("KORTESTQ"), str8_lit_comp("OR Masks And Set Flags")}, -{str8_lit_comp("KORTESTW"), str8_lit_comp("OR Masks And Set Flags")}, -{str8_lit_comp("KORW"), str8_lit_comp("Bitwise Logical OR Masks")}, -{str8_lit_comp("KSHIFTLB"), str8_lit_comp("Shift Left Mask Registers")}, -{str8_lit_comp("KSHIFTLD"), str8_lit_comp("Shift Left Mask Registers")}, -{str8_lit_comp("KSHIFTLQ"), str8_lit_comp("Shift Left Mask Registers")}, -{str8_lit_comp("KSHIFTLW"), str8_lit_comp("Shift Left Mask Registers")}, -{str8_lit_comp("KSHIFTRB"), str8_lit_comp("Shift Right Mask Registers")}, -{str8_lit_comp("KSHIFTRD"), str8_lit_comp("Shift Right Mask Registers")}, -{str8_lit_comp("KSHIFTRQ"), str8_lit_comp("Shift Right Mask Registers")}, -{str8_lit_comp("KSHIFTRW"), str8_lit_comp("Shift Right Mask Registers")}, -{str8_lit_comp("KTESTB"), str8_lit_comp("Packed Bit Test Masks and Set Flags")}, -{str8_lit_comp("KTESTD"), str8_lit_comp("Packed Bit Test Masks and Set Flags")}, -{str8_lit_comp("KTESTQ"), str8_lit_comp("Packed Bit Test Masks and Set Flags")}, -{str8_lit_comp("KTESTW"), str8_lit_comp("Packed Bit Test Masks and Set Flags")}, -{str8_lit_comp("KUNPCKBW"), str8_lit_comp("Unpack for Mask Registers")}, -{str8_lit_comp("KUNPCKDQ"), str8_lit_comp("Unpack for Mask Registers")}, -{str8_lit_comp("KUNPCKWD"), str8_lit_comp("Unpack for Mask Registers")}, -{str8_lit_comp("KXNORB"), str8_lit_comp("Bitwise Logical XNOR Masks")}, -{str8_lit_comp("KXNORD"), str8_lit_comp("Bitwise Logical XNOR Masks")}, -{str8_lit_comp("KXNORQ"), str8_lit_comp("Bitwise Logical XNOR Masks")}, -{str8_lit_comp("KXNORW"), str8_lit_comp("Bitwise Logical XNOR Masks")}, -{str8_lit_comp("KXORB"), str8_lit_comp("Bitwise Logical XOR Masks")}, -{str8_lit_comp("KXORD"), str8_lit_comp("Bitwise Logical XOR Masks")}, -{str8_lit_comp("KXORQ"), str8_lit_comp("Bitwise Logical XOR Masks")}, -{str8_lit_comp("KXORW"), str8_lit_comp("Bitwise Logical XOR Masks")}, -{str8_lit_comp("LAHF"), str8_lit_comp("Load Status Flags into AH Register")}, -{str8_lit_comp("LAR"), str8_lit_comp("Load Access Rights Byte")}, -{str8_lit_comp("LDDQU"), str8_lit_comp("Load Unaligned Integer 128 Bits")}, -{str8_lit_comp("LDMXCSR"), str8_lit_comp("Load MXCSR Register")}, -{str8_lit_comp("LDS"), str8_lit_comp("Load Far Pointer")}, -{str8_lit_comp("LEA"), str8_lit_comp("Load Effective Address")}, -{str8_lit_comp("LEAVE"), str8_lit_comp("High Level Procedure Exit")}, -{str8_lit_comp("LES"), str8_lit_comp("Load Far Pointer")}, -{str8_lit_comp("LFENCE"), str8_lit_comp("Load Fence")}, -{str8_lit_comp("LFS"), str8_lit_comp("Load Far Pointer")}, -{str8_lit_comp("LGDT"), str8_lit_comp("Load Global/Interrupt Descriptor Table Register")}, -{str8_lit_comp("LGS"), str8_lit_comp("Load Far Pointer")}, -{str8_lit_comp("LIDT"), str8_lit_comp("Load Global/Interrupt Descriptor Table Register")}, -{str8_lit_comp("LLDT"), str8_lit_comp("Load Local Descriptor Table Register")}, -{str8_lit_comp("LMSW"), str8_lit_comp("Load Machine Status Word")}, -{str8_lit_comp("LOADIWKEY"), str8_lit_comp("Load Internal Wrapping Key with Key Locker")}, -{str8_lit_comp("LOCK"), str8_lit_comp("Assert LOCK# Signal Prefix")}, -{str8_lit_comp("LODS"), str8_lit_comp("Load String")}, -{str8_lit_comp("LODSB"), str8_lit_comp("Load String")}, -{str8_lit_comp("LODSD"), str8_lit_comp("Load String")}, -{str8_lit_comp("LODSQ"), str8_lit_comp("Load String")}, -{str8_lit_comp("LODSW"), str8_lit_comp("Load String")}, -{str8_lit_comp("LOOP"), str8_lit_comp("Loop According to ECX Counter")}, -{str8_lit_comp("LOOPcc"), str8_lit_comp("Loop According to ECX Counter")}, -{str8_lit_comp("LSL"), str8_lit_comp("Load Segment Limit")}, -{str8_lit_comp("LSS"), str8_lit_comp("Load Far Pointer")}, -{str8_lit_comp("LTR"), str8_lit_comp("Load Task Register")}, -{str8_lit_comp("LZCNT"), str8_lit_comp("Count the Number of Leading Zero Bits")}, -{str8_lit_comp("MASKMOVDQU"), str8_lit_comp("Store Selected Bytes of Double Quadword")}, -{str8_lit_comp("MASKMOVQ"), str8_lit_comp("Store Selected Bytes of Quadword")}, -{str8_lit_comp("MAXPD"), str8_lit_comp("Maximum of Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("MAXPS"), str8_lit_comp("Maximum of Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("MAXSD"), str8_lit_comp("Return Maximum Scalar Double-Precision Floating-Point Value")}, -{str8_lit_comp("MAXSS"), str8_lit_comp("Return Maximum Scalar Single-Precision Floating-Point Value")}, -{str8_lit_comp("MFENCE"), str8_lit_comp("Memory Fence")}, -{str8_lit_comp("MINPD"), str8_lit_comp("Minimum of Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("MINPS"), str8_lit_comp("Minimum of Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("MINSD"), str8_lit_comp("Return Minimum Scalar Double-Precision Floating-Point Value")}, -{str8_lit_comp("MINSS"), str8_lit_comp("Return Minimum Scalar Single-Precision Floating-Point Value")}, -{str8_lit_comp("MONITOR"), str8_lit_comp("Set Up Monitor Address")}, -{str8_lit_comp("MOV"), str8_lit_comp("Move")}, -{str8_lit_comp("MOVAPD"), str8_lit_comp("Move Aligned Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("MOVAPS"), str8_lit_comp("Move Aligned Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("MOVBE"), str8_lit_comp("Move Data After Swapping Bytes")}, -{str8_lit_comp("MOVD"), str8_lit_comp("Move Doubleword/Move Quadword")}, -{str8_lit_comp("MOVDDUP"), str8_lit_comp("Replicate Double FP Values")}, -{str8_lit_comp("MOVDIR64B"), str8_lit_comp("Move 64 Bytes as Direct Store")}, -{str8_lit_comp("MOVDIRI"), str8_lit_comp("Move Doubleword as Direct Store")}, -{str8_lit_comp("MOVDQ2Q"), str8_lit_comp("Move Quadword from XMM to MMX Technology Register")}, -{str8_lit_comp("MOVDQA"), str8_lit_comp("Move Aligned Packed Integer Values")}, -{str8_lit_comp("MOVDQU"), str8_lit_comp("Move Unaligned Packed Integer Values")}, -{str8_lit_comp("MOVHLPS"), str8_lit_comp("Move Packed Single-Precision Floating-Point Values High to Low")}, -{str8_lit_comp("MOVHPD"), str8_lit_comp("Move High Packed Double-Precision Floating-Point Value")}, -{str8_lit_comp("MOVHPS"), str8_lit_comp("Move High Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("MOVLHPS"), str8_lit_comp("Move Packed Single-Precision Floating-Point Values Low to High")}, -{str8_lit_comp("MOVLPD"), str8_lit_comp("Move Low Packed Double-Precision Floating-Point Value")}, -{str8_lit_comp("MOVLPS"), str8_lit_comp("Move Low Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("MOVMSKPD"), str8_lit_comp("Extract Packed Double-Precision Floating-Point Sign Mask")}, -{str8_lit_comp("MOVMSKPS"), str8_lit_comp("Extract Packed Single-Precision Floating-Point Sign Mask")}, -{str8_lit_comp("MOVNTDQ"), str8_lit_comp("Store Packed Integers Using Non-Temporal Hint")}, -{str8_lit_comp("MOVNTDQA"), str8_lit_comp("Load Double Quadword Non-Temporal Aligned Hint")}, -{str8_lit_comp("MOVNTI"), str8_lit_comp("Store Doubleword Using Non-Temporal Hint")}, -{str8_lit_comp("MOVNTPD"), str8_lit_comp("Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint")}, -{str8_lit_comp("MOVNTPS"), str8_lit_comp("Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint")}, -{str8_lit_comp("MOVNTQ"), str8_lit_comp("Store of Quadword Using Non-Temporal Hint")}, -{str8_lit_comp("MOVQ"), str8_lit_comp("Move Doubleword/Move Quadword")}, -{str8_lit_comp("MOVQ2DQ"), str8_lit_comp("Move Quadword from MMX Technology to XMM Register")}, -{str8_lit_comp("MOVS"), str8_lit_comp("Move Data from String to String")}, -{str8_lit_comp("MOVSB"), str8_lit_comp("Move Data from String to String")}, -{str8_lit_comp("MOVSD"), str8_lit_comp("Move Data from String to String")}, -{str8_lit_comp("MOVSHDUP"), str8_lit_comp("Replicate Single FP Values")}, -{str8_lit_comp("MOVSLDUP"), str8_lit_comp("Replicate Single FP Values")}, -{str8_lit_comp("MOVSQ"), str8_lit_comp("Move Data from String to String")}, -{str8_lit_comp("MOVSS"), str8_lit_comp("Move or Merge Scalar Single-Precision Floating-Point Value")}, -{str8_lit_comp("MOVSW"), str8_lit_comp("Move Data from String to String")}, -{str8_lit_comp("MOVSX"), str8_lit_comp("Move with Sign-Extension")}, -{str8_lit_comp("MOVSXD"), str8_lit_comp("Move with Sign-Extension")}, -{str8_lit_comp("MOVUPD"), str8_lit_comp("Move Unaligned Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("MOVUPS"), str8_lit_comp("Move Unaligned Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("MOVZX"), str8_lit_comp("Move with Zero-Extend")}, -{str8_lit_comp("MPSADBW"), str8_lit_comp("Compute Multiple Packed Sums of Absolute Difference")}, -{str8_lit_comp("MUL"), str8_lit_comp("Unsigned Multiply")}, -{str8_lit_comp("MULPD"), str8_lit_comp("Multiply Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("MULPS"), str8_lit_comp("Multiply Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("MULSD"), str8_lit_comp("Multiply Scalar Double-Precision Floating-Point Value")}, -{str8_lit_comp("MULSS"), str8_lit_comp("Multiply Scalar Single-Precision Floating-Point Values")}, -{str8_lit_comp("MULX"), str8_lit_comp("Unsigned Multiply Without Affecting Flags")}, -{str8_lit_comp("MWAIT"), str8_lit_comp("Monitor Wait")}, -{str8_lit_comp("NEG"), str8_lit_comp("Two's Complement Negation")}, -{str8_lit_comp("NOP"), str8_lit_comp("No Operation")}, -{str8_lit_comp("NOT"), str8_lit_comp("One's Complement Negation")}, -{str8_lit_comp("OR"), str8_lit_comp("Logical Inclusive OR")}, -{str8_lit_comp("ORPD"), str8_lit_comp("Bitwise Logical OR of Packed Double Precision Floating-Point Values")}, -{str8_lit_comp("ORPS"), str8_lit_comp("Bitwise Logical OR of Packed Single Precision Floating-Point Values")}, -{str8_lit_comp("OUT"), str8_lit_comp("Output to Port")}, -{str8_lit_comp("OUTS"), str8_lit_comp("Output String to Port")}, -{str8_lit_comp("OUTSB"), str8_lit_comp("Output String to Port")}, -{str8_lit_comp("OUTSD"), str8_lit_comp("Output String to Port")}, -{str8_lit_comp("OUTSW"), str8_lit_comp("Output String to Port")}, -{str8_lit_comp("PABSB"), str8_lit_comp("Packed Absolute Value")}, -{str8_lit_comp("PABSD"), str8_lit_comp("Packed Absolute Value")}, -{str8_lit_comp("PABSQ"), str8_lit_comp("Packed Absolute Value")}, -{str8_lit_comp("PABSW"), str8_lit_comp("Packed Absolute Value")}, -{str8_lit_comp("PACKSSDW"), str8_lit_comp("Pack with Signed Saturation")}, -{str8_lit_comp("PACKSSWB"), str8_lit_comp("Pack with Signed Saturation")}, -{str8_lit_comp("PACKUSDW"), str8_lit_comp("Pack with Unsigned Saturation")}, -{str8_lit_comp("PACKUSWB"), str8_lit_comp("Pack with Unsigned Saturation")}, -{str8_lit_comp("PADDB"), str8_lit_comp("Add Packed Integers")}, -{str8_lit_comp("PADDD"), str8_lit_comp("Add Packed Integers")}, -{str8_lit_comp("PADDQ"), str8_lit_comp("Add Packed Integers")}, -{str8_lit_comp("PADDSB"), str8_lit_comp("Add Packed Signed Integers with Signed Saturation")}, -{str8_lit_comp("PADDSW"), str8_lit_comp("Add Packed Signed Integers with Signed Saturation")}, -{str8_lit_comp("PADDUSB"), str8_lit_comp("Add Packed Unsigned Integers with Unsigned Saturation")}, -{str8_lit_comp("PADDUSW"), str8_lit_comp("Add Packed Unsigned Integers with Unsigned Saturation")}, -{str8_lit_comp("PADDW"), str8_lit_comp("Add Packed Integers")}, -{str8_lit_comp("PALIGNR"), str8_lit_comp("Packed Align Right")}, -{str8_lit_comp("PAND"), str8_lit_comp("Logical AND")}, -{str8_lit_comp("PANDN"), str8_lit_comp("Logical AND NOT")}, -{str8_lit_comp("PAUSE"), str8_lit_comp("Spin Loop Hint")}, -{str8_lit_comp("PAVGB"), str8_lit_comp("Average Packed Integers")}, -{str8_lit_comp("PAVGW"), str8_lit_comp("Average Packed Integers")}, -{str8_lit_comp("PBLENDVB"), str8_lit_comp("Variable Blend Packed Bytes")}, -{str8_lit_comp("PBLENDW"), str8_lit_comp("Blend Packed Words")}, -{str8_lit_comp("PCLMULQDQ"), str8_lit_comp("Carry-Less Multiplication Quadword")}, -{str8_lit_comp("PCMPEQB"), str8_lit_comp("Compare Packed Data for Equal")}, -{str8_lit_comp("PCMPEQD"), str8_lit_comp("Compare Packed Data for Equal")}, -{str8_lit_comp("PCMPEQQ"), str8_lit_comp("Compare Packed Qword Data for Equal")}, -{str8_lit_comp("PCMPEQW"), str8_lit_comp("Compare Packed Data for Equal")}, -{str8_lit_comp("PCMPESTRI"), str8_lit_comp("Packed Compare Explicit Length Strings, Return Index")}, -{str8_lit_comp("PCMPESTRM"), str8_lit_comp("Packed Compare Explicit Length Strings, Return Mask")}, -{str8_lit_comp("PCMPGTB"), str8_lit_comp("Compare Packed Signed Integers for Greater Than")}, -{str8_lit_comp("PCMPGTD"), str8_lit_comp("Compare Packed Signed Integers for Greater Than")}, -{str8_lit_comp("PCMPGTQ"), str8_lit_comp("Compare Packed Data for Greater Than")}, -{str8_lit_comp("PCMPGTW"), str8_lit_comp("Compare Packed Signed Integers for Greater Than")}, -{str8_lit_comp("PCMPISTRI"), str8_lit_comp("Packed Compare Implicit Length Strings, Return Index")}, -{str8_lit_comp("PCMPISTRM"), str8_lit_comp("Packed Compare Implicit Length Strings, Return Mask")}, -{str8_lit_comp("PCONFIG"), str8_lit_comp("Platform Configuration")}, -{str8_lit_comp("PDEP"), str8_lit_comp("Parallel Bits Deposit")}, -{str8_lit_comp("PEXT"), str8_lit_comp("Parallel Bits Extract")}, -{str8_lit_comp("PEXTRB"), str8_lit_comp("Extract Byte/Dword/Qword")}, -{str8_lit_comp("PEXTRD"), str8_lit_comp("Extract Byte/Dword/Qword")}, -{str8_lit_comp("PEXTRQ"), str8_lit_comp("Extract Byte/Dword/Qword")}, -{str8_lit_comp("PEXTRW"), str8_lit_comp("Extract Word")}, -{str8_lit_comp("PHADDD"), str8_lit_comp("Packed Horizontal Add")}, -{str8_lit_comp("PHADDSW"), str8_lit_comp("Packed Horizontal Add and Saturate")}, -{str8_lit_comp("PHADDW"), str8_lit_comp("Packed Horizontal Add")}, -{str8_lit_comp("PHMINPOSUW"), str8_lit_comp("Packed Horizontal Word Minimum")}, -{str8_lit_comp("PHSUBD"), str8_lit_comp("Packed Horizontal Subtract")}, -{str8_lit_comp("PHSUBSW"), str8_lit_comp("Packed Horizontal Subtract and Saturate")}, -{str8_lit_comp("PHSUBW"), str8_lit_comp("Packed Horizontal Subtract")}, -{str8_lit_comp("PINSRB"), str8_lit_comp("Insert Byte/Dword/Qword")}, -{str8_lit_comp("PINSRD"), str8_lit_comp("Insert Byte/Dword/Qword")}, -{str8_lit_comp("PINSRQ"), str8_lit_comp("Insert Byte/Dword/Qword")}, -{str8_lit_comp("PINSRW"), str8_lit_comp("Insert Word")}, -{str8_lit_comp("PMADDUBSW"), str8_lit_comp("Multiply and Add Packed Signed and Unsigned Bytes")}, -{str8_lit_comp("PMADDWD"), str8_lit_comp("Multiply and Add Packed Integers")}, -{str8_lit_comp("PMAXSB"), str8_lit_comp("Maximum of Packed Signed Integers")}, -{str8_lit_comp("PMAXSD"), str8_lit_comp("Maximum of Packed Signed Integers")}, -{str8_lit_comp("PMAXSQ"), str8_lit_comp("Maximum of Packed Signed Integers")}, -{str8_lit_comp("PMAXSW"), str8_lit_comp("Maximum of Packed Signed Integers")}, -{str8_lit_comp("PMAXUB"), str8_lit_comp("Maximum of Packed Unsigned Integers")}, -{str8_lit_comp("PMAXUD"), str8_lit_comp("Maximum of Packed Unsigned Integers")}, -{str8_lit_comp("PMAXUQ"), str8_lit_comp("Maximum of Packed Unsigned Integers")}, -{str8_lit_comp("PMAXUW"), str8_lit_comp("Maximum of Packed Unsigned Integers")}, -{str8_lit_comp("PMINSB"), str8_lit_comp("Minimum of Packed Signed Integers")}, -{str8_lit_comp("PMINSD"), str8_lit_comp("Minimum of Packed Signed Integers")}, -{str8_lit_comp("PMINSQ"), str8_lit_comp("Minimum of Packed Signed Integers")}, -{str8_lit_comp("PMINSW"), str8_lit_comp("Minimum of Packed Signed Integers")}, -{str8_lit_comp("PMINUB"), str8_lit_comp("Minimum of Packed Unsigned Integers")}, -{str8_lit_comp("PMINUD"), str8_lit_comp("Minimum of Packed Unsigned Integers")}, -{str8_lit_comp("PMINUQ"), str8_lit_comp("Minimum of Packed Unsigned Integers")}, -{str8_lit_comp("PMINUW"), str8_lit_comp("Minimum of Packed Unsigned Integers")}, -{str8_lit_comp("PMOVMSKB"), str8_lit_comp("Move Byte Mask")}, -{str8_lit_comp("PMOVSX"), str8_lit_comp("Packed Move with Sign Extend")}, -{str8_lit_comp("PMOVZX"), str8_lit_comp("Packed Move with Zero Extend")}, -{str8_lit_comp("PMULDQ"), str8_lit_comp("Multiply Packed Doubleword Integers")}, -{str8_lit_comp("PMULHRSW"), str8_lit_comp("Packed Multiply High with Round and Scale")}, -{str8_lit_comp("PMULHUW"), str8_lit_comp("Multiply Packed Unsigned Integers and Store High Result")}, -{str8_lit_comp("PMULHW"), str8_lit_comp("Multiply Packed Signed Integers and Store High Result")}, -{str8_lit_comp("PMULLD"), str8_lit_comp("Multiply Packed Integers and Store Low Result")}, -{str8_lit_comp("PMULLQ"), str8_lit_comp("Multiply Packed Integers and Store Low Result")}, -{str8_lit_comp("PMULLW"), str8_lit_comp("Multiply Packed Signed Integers and Store Low Result")}, -{str8_lit_comp("PMULUDQ"), str8_lit_comp("Multiply Packed Unsigned Doubleword Integers")}, -{str8_lit_comp("POP"), str8_lit_comp("Pop a Value from the Stack")}, -{str8_lit_comp("POPA"), str8_lit_comp("Pop All General-Purpose Registers")}, -{str8_lit_comp("POPAD"), str8_lit_comp("Pop All General-Purpose Registers")}, -{str8_lit_comp("POPCNT"), str8_lit_comp("Return the Count of Number of Bits Set to 1")}, -{str8_lit_comp("POPF"), str8_lit_comp("Pop Stack into EFLAGS Register")}, -{str8_lit_comp("POPFD"), str8_lit_comp("Pop Stack into EFLAGS Register")}, -{str8_lit_comp("POPFQ"), str8_lit_comp("Pop Stack into EFLAGS Register")}, -{str8_lit_comp("POR"), str8_lit_comp("Bitwise Logical OR")}, -{str8_lit_comp("PREFETCHW"), str8_lit_comp("Prefetch Data into Caches in Anticipation of a Write")}, -{str8_lit_comp("PREFETCHh"), str8_lit_comp("Prefetch Data Into Caches")}, -{str8_lit_comp("PSADBW"), str8_lit_comp("Compute Sum of Absolute Differences")}, -{str8_lit_comp("PSHUFB"), str8_lit_comp("Packed Shuffle Bytes")}, -{str8_lit_comp("PSHUFD"), str8_lit_comp("Shuffle Packed Doublewords")}, -{str8_lit_comp("PSHUFHW"), str8_lit_comp("Shuffle Packed High Words")}, -{str8_lit_comp("PSHUFLW"), str8_lit_comp("Shuffle Packed Low Words")}, -{str8_lit_comp("PSHUFW"), str8_lit_comp("Shuffle Packed Words")}, -{str8_lit_comp("PSIGNB"), str8_lit_comp("Packed SIGN")}, -{str8_lit_comp("PSIGND"), str8_lit_comp("Packed SIGN")}, -{str8_lit_comp("PSIGNW"), str8_lit_comp("Packed SIGN")}, -{str8_lit_comp("PSLLD"), str8_lit_comp("Shift Packed Data Left Logical")}, -{str8_lit_comp("PSLLDQ"), str8_lit_comp("Shift Double Quadword Left Logical")}, -{str8_lit_comp("PSLLQ"), str8_lit_comp("Shift Packed Data Left Logical")}, -{str8_lit_comp("PSLLW"), str8_lit_comp("Shift Packed Data Left Logical")}, -{str8_lit_comp("PSRAD"), str8_lit_comp("Shift Packed Data Right Arithmetic")}, -{str8_lit_comp("PSRAQ"), str8_lit_comp("Shift Packed Data Right Arithmetic")}, -{str8_lit_comp("PSRAW"), str8_lit_comp("Shift Packed Data Right Arithmetic")}, -{str8_lit_comp("PSRLD"), str8_lit_comp("Shift Packed Data Right Logical")}, -{str8_lit_comp("PSRLDQ"), str8_lit_comp("Shift Double Quadword Right Logical")}, -{str8_lit_comp("PSRLQ"), str8_lit_comp("Shift Packed Data Right Logical")}, -{str8_lit_comp("PSRLW"), str8_lit_comp("Shift Packed Data Right Logical")}, -{str8_lit_comp("PSUBB"), str8_lit_comp("Subtract Packed Integers")}, -{str8_lit_comp("PSUBD"), str8_lit_comp("Subtract Packed Integers")}, -{str8_lit_comp("PSUBQ"), str8_lit_comp("Subtract Packed Quadword Integers")}, -{str8_lit_comp("PSUBSB"), str8_lit_comp("Subtract Packed Signed Integers with Signed Saturation")}, -{str8_lit_comp("PSUBSW"), str8_lit_comp("Subtract Packed Signed Integers with Signed Saturation")}, -{str8_lit_comp("PSUBUSB"), str8_lit_comp("Subtract Packed Unsigned Integers with Unsigned Saturation")}, -{str8_lit_comp("PSUBUSW"), str8_lit_comp("Subtract Packed Unsigned Integers with Unsigned Saturation")}, -{str8_lit_comp("PSUBW"), str8_lit_comp("Subtract Packed Integers")}, -{str8_lit_comp("PTEST"), str8_lit_comp("Logical Compare")}, -{str8_lit_comp("PTWRITE"), str8_lit_comp("Write Data to a Processor Trace Packet")}, -{str8_lit_comp("PUNPCKHBW"), str8_lit_comp("Unpack High Data")}, -{str8_lit_comp("PUNPCKHDQ"), str8_lit_comp("Unpack High Data")}, -{str8_lit_comp("PUNPCKHQDQ"), str8_lit_comp("Unpack High Data")}, -{str8_lit_comp("PUNPCKHWD"), str8_lit_comp("Unpack High Data")}, -{str8_lit_comp("PUNPCKLBW"), str8_lit_comp("Unpack Low Data")}, -{str8_lit_comp("PUNPCKLDQ"), str8_lit_comp("Unpack Low Data")}, -{str8_lit_comp("PUNPCKLQDQ"), str8_lit_comp("Unpack Low Data")}, -{str8_lit_comp("PUNPCKLWD"), str8_lit_comp("Unpack Low Data")}, -{str8_lit_comp("PUSH"), str8_lit_comp("Push Word, Doubleword or Quadword Onto the Stack")}, -{str8_lit_comp("PUSHA"), str8_lit_comp("Push All General-Purpose Registers")}, -{str8_lit_comp("PUSHAD"), str8_lit_comp("Push All General-Purpose Registers")}, -{str8_lit_comp("PUSHF"), str8_lit_comp("Push EFLAGS Register onto the Stack")}, -{str8_lit_comp("PUSHFD"), str8_lit_comp("Push EFLAGS Register onto the Stack")}, -{str8_lit_comp("PUSHFQ"), str8_lit_comp("Push EFLAGS Register onto the Stack")}, -{str8_lit_comp("PXOR"), str8_lit_comp("Logical Exclusive OR")}, -{str8_lit_comp("RCL"), str8_lit_comp("Rotate")}, -{str8_lit_comp("RCPPS"), str8_lit_comp("Compute Reciprocals of Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("RCPSS"), str8_lit_comp("Compute Reciprocal of Scalar Single-Precision Floating-Point Values")}, -{str8_lit_comp("RCR"), str8_lit_comp("Rotate")}, -{str8_lit_comp("RDFSBASE"), str8_lit_comp("Read FS/GS Segment Base")}, -{str8_lit_comp("RDGSBASE"), str8_lit_comp("Read FS/GS Segment Base")}, -{str8_lit_comp("RDMSR"), str8_lit_comp("Read from Model Specific Register")}, -{str8_lit_comp("RDPID"), str8_lit_comp("Read Processor ID")}, -{str8_lit_comp("RDPKRU"), str8_lit_comp("Read Protection Key Rights for User Pages")}, -{str8_lit_comp("RDPMC"), str8_lit_comp("Read Performance-Monitoring Counters")}, -{str8_lit_comp("RDRAND"), str8_lit_comp("Read Random Number")}, -{str8_lit_comp("RDSEED"), str8_lit_comp("Read Random SEED")}, -{str8_lit_comp("RDSSPD"), str8_lit_comp("Read Shadow Stack Pointer")}, -{str8_lit_comp("RDSSPQ"), str8_lit_comp("Read Shadow Stack Pointer")}, -{str8_lit_comp("RDTSC"), str8_lit_comp("Read Time-Stamp Counter")}, -{str8_lit_comp("RDTSCP"), str8_lit_comp("Read Time-Stamp Counter and Processor ID")}, -{str8_lit_comp("REP"), str8_lit_comp("Repeat String Operation Prefix")}, -{str8_lit_comp("REPE"), str8_lit_comp("Repeat String Operation Prefix")}, -{str8_lit_comp("REPNE"), str8_lit_comp("Repeat String Operation Prefix")}, -{str8_lit_comp("REPNZ"), str8_lit_comp("Repeat String Operation Prefix")}, -{str8_lit_comp("REPZ"), str8_lit_comp("Repeat String Operation Prefix")}, -{str8_lit_comp("RET"), str8_lit_comp("Return from Procedure")}, -{str8_lit_comp("ROL"), str8_lit_comp("Rotate")}, -{str8_lit_comp("ROR"), str8_lit_comp("Rotate")}, -{str8_lit_comp("RORX"), str8_lit_comp("Rotate Right Logical Without Affecting Flags")}, -{str8_lit_comp("ROUNDPD"), str8_lit_comp("Round Packed Double Precision Floating-Point Values")}, -{str8_lit_comp("ROUNDPS"), str8_lit_comp("Round Packed Single Precision Floating-Point Values")}, -{str8_lit_comp("ROUNDSD"), str8_lit_comp("Round Scalar Double Precision Floating-Point Values")}, -{str8_lit_comp("ROUNDSS"), str8_lit_comp("Round Scalar Single Precision Floating-Point Values")}, -{str8_lit_comp("RSM"), str8_lit_comp("Resume from System Management Mode")}, -{str8_lit_comp("RSQRTPS"), str8_lit_comp("Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("RSQRTSS"), str8_lit_comp("Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value")}, -{str8_lit_comp("RSTORSSP"), str8_lit_comp("Restore Saved Shadow Stack Pointer")}, -{str8_lit_comp("SAHF"), str8_lit_comp("Store AH into Flags")}, -{str8_lit_comp("SAL"), str8_lit_comp("Shift")}, -{str8_lit_comp("SAR"), str8_lit_comp("Shift")}, -{str8_lit_comp("SARX"), str8_lit_comp("Shift Without Affecting Flags")}, -{str8_lit_comp("SAVEPREVSSP"), str8_lit_comp("Save Previous Shadow Stack Pointer")}, -{str8_lit_comp("SBB"), str8_lit_comp("Integer Subtraction with Borrow")}, -{str8_lit_comp("SCAS"), str8_lit_comp("Scan String")}, -{str8_lit_comp("SCASB"), str8_lit_comp("Scan String")}, -{str8_lit_comp("SCASD"), str8_lit_comp("Scan String")}, -{str8_lit_comp("SCASW"), str8_lit_comp("Scan String")}, -{str8_lit_comp("SERIALIZE"), str8_lit_comp("Serialize Instruction Execution")}, -{str8_lit_comp("SETSSBSY"), str8_lit_comp("Mark Shadow Stack Busy")}, -{str8_lit_comp("SETcc"), str8_lit_comp("Set Byte on Condition")}, -{str8_lit_comp("SFENCE"), str8_lit_comp("Store Fence")}, -{str8_lit_comp("SGDT"), str8_lit_comp("Store Global Descriptor Table Register")}, -{str8_lit_comp("SHA1MSG1"), str8_lit_comp("Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords")}, -{str8_lit_comp("SHA1MSG2"), str8_lit_comp("Perform a Final Calculation for the Next Four SHA1 Message Dwords")}, -{str8_lit_comp("SHA1NEXTE"), str8_lit_comp("Calculate SHA1 State Variable E after Four Rounds")}, -{str8_lit_comp("SHA1RNDS4"), str8_lit_comp("Perform Four Rounds of SHA1 Operation")}, -{str8_lit_comp("SHA256MSG1"), str8_lit_comp("Perform an Intermediate Calculation for the Next Four SHA256 Message Dwords")}, -{str8_lit_comp("SHA256MSG2"), str8_lit_comp("Perform a Final Calculation for the Next Four SHA256 Message Dwords")}, -{str8_lit_comp("SHA256RNDS2"), str8_lit_comp("Perform Two Rounds of SHA256 Operation")}, -{str8_lit_comp("SHL"), str8_lit_comp("Shift")}, -{str8_lit_comp("SHLD"), str8_lit_comp("Double Precision Shift Left")}, -{str8_lit_comp("SHLX"), str8_lit_comp("Shift Without Affecting Flags")}, -{str8_lit_comp("SHR"), str8_lit_comp("Shift")}, -{str8_lit_comp("SHRD"), str8_lit_comp("Double Precision Shift Right")}, -{str8_lit_comp("SHRX"), str8_lit_comp("Shift Without Affecting Flags")}, -{str8_lit_comp("SHUFPD"), str8_lit_comp("Packed Interleave Shuffle of Pairs of Double-Precision Floating-Point Values")}, -{str8_lit_comp("SHUFPS"), str8_lit_comp("Packed Interleave Shuffle of Quadruplets of Single-Precision Floating-Point Values")}, -{str8_lit_comp("SIDT"), str8_lit_comp("Store Interrupt Descriptor Table Register")}, -{str8_lit_comp("SLDT"), str8_lit_comp("Store Local Descriptor Table Register")}, -{str8_lit_comp("SMSW"), str8_lit_comp("Store Machine Status Word")}, -{str8_lit_comp("SQRTPD"), str8_lit_comp("Square Root of Double-Precision Floating-Point Values")}, -{str8_lit_comp("SQRTPS"), str8_lit_comp("Square Root of Single-Precision Floating-Point Values")}, -{str8_lit_comp("SQRTSD"), str8_lit_comp("Compute Square Root of Scalar Double-Precision Floating-Point Value")}, -{str8_lit_comp("SQRTSS"), str8_lit_comp("Compute Square Root of Scalar Single-Precision Value")}, -{str8_lit_comp("STAC"), str8_lit_comp("Set AC Flag in EFLAGS Register")}, -{str8_lit_comp("STC"), str8_lit_comp("Set Carry Flag")}, -{str8_lit_comp("STD"), str8_lit_comp("Set Direction Flag")}, -{str8_lit_comp("STI"), str8_lit_comp("Set Interrupt Flag")}, -{str8_lit_comp("STMXCSR"), str8_lit_comp("Store MXCSR Register State")}, -{str8_lit_comp("STOS"), str8_lit_comp("Store String")}, -{str8_lit_comp("STOSB"), str8_lit_comp("Store String")}, -{str8_lit_comp("STOSD"), str8_lit_comp("Store String")}, -{str8_lit_comp("STOSQ"), str8_lit_comp("Store String")}, -{str8_lit_comp("STOSW"), str8_lit_comp("Store String")}, -{str8_lit_comp("STR"), str8_lit_comp("Store Task Register")}, -{str8_lit_comp("SUB"), str8_lit_comp("Subtract")}, -{str8_lit_comp("SUBPD"), str8_lit_comp("Subtract Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("SUBPS"), str8_lit_comp("Subtract Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("SUBSD"), str8_lit_comp("Subtract Scalar Double-Precision Floating-Point Value")}, -{str8_lit_comp("SUBSS"), str8_lit_comp("Subtract Scalar Single-Precision Floating-Point Value")}, -{str8_lit_comp("SWAPGS"), str8_lit_comp("Swap GS Base Register")}, -{str8_lit_comp("SYSCALL"), str8_lit_comp("Fast System Call")}, -{str8_lit_comp("SYSENTER"), str8_lit_comp("Fast System Call")}, -{str8_lit_comp("SYSEXIT"), str8_lit_comp("Fast Return from Fast System Call")}, -{str8_lit_comp("SYSRET"), str8_lit_comp("Return From Fast System Call")}, -{str8_lit_comp("TEST"), str8_lit_comp("Logical Compare")}, -{str8_lit_comp("TPAUSE"), str8_lit_comp("Timed PAUSE")}, -{str8_lit_comp("TZCNT"), str8_lit_comp("Count the Number of Trailing Zero Bits")}, -{str8_lit_comp("UCOMISD"), str8_lit_comp("Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS")}, -{str8_lit_comp("UCOMISS"), str8_lit_comp("Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS")}, -{str8_lit_comp("UD"), str8_lit_comp("Undefined Instruction")}, -{str8_lit_comp("UMONITOR"), str8_lit_comp("User Level Set Up Monitor Address")}, -{str8_lit_comp("UMWAIT"), str8_lit_comp("User Level Monitor Wait")}, -{str8_lit_comp("UNPCKHPD"), str8_lit_comp("Unpack and Interleave High Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("UNPCKHPS"), str8_lit_comp("Unpack and Interleave High Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("UNPCKLPD"), str8_lit_comp("Unpack and Interleave Low Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("UNPCKLPS"), str8_lit_comp("Unpack and Interleave Low Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("VALIGND"), str8_lit_comp("Align Doubleword/Quadword Vectors")}, -{str8_lit_comp("VALIGNQ"), str8_lit_comp("Align Doubleword/Quadword Vectors")}, -{str8_lit_comp("VBLENDMPD"), str8_lit_comp("Blend Float64/Float32 Vectors Using an OpMask Control")}, -{str8_lit_comp("VBLENDMPS"), str8_lit_comp("Blend Float64/Float32 Vectors Using an OpMask Control")}, -{str8_lit_comp("VBROADCAST"), str8_lit_comp("Load with Broadcast Floating-Point Data")}, -{str8_lit_comp("VCOMPRESSPD"), str8_lit_comp("Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory")}, -{str8_lit_comp("VCOMPRESSPS"), str8_lit_comp("Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory")}, -{str8_lit_comp("VCOMPRESSW"), str8_lit_comp("Store Sparse Packed Byte/Word Integer Values into Dense Memory/Register")}, -{str8_lit_comp("VCVTNE2PS2BF16"), str8_lit_comp("Convert Two Packed Single Data to One Packed BF16 Data")}, -{str8_lit_comp("VCVTNEPS2BF16"), str8_lit_comp("Convert Packed Single Data to Packed BF16 Data")}, -{str8_lit_comp("VCVTPD2QQ"), str8_lit_comp("Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers")}, -{str8_lit_comp("VCVTPD2UDQ"), str8_lit_comp("Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers")}, -{str8_lit_comp("VCVTPD2UQQ"), str8_lit_comp("Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers")}, -{str8_lit_comp("VCVTPH2PS"), str8_lit_comp("Convert 16-bit FP values to Single-Precision FP values")}, -{str8_lit_comp("VCVTPS2PH"), str8_lit_comp("Convert Single-Precision FP value to 16-bit FP value")}, -{str8_lit_comp("VCVTPS2QQ"), str8_lit_comp("Convert Packed Single Precision Floating-Point Values to Packed Signed Quadword Integer Values")}, -{str8_lit_comp("VCVTPS2UDQ"), str8_lit_comp("Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values")}, -{str8_lit_comp("VCVTPS2UQQ"), str8_lit_comp("Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values")}, -{str8_lit_comp("VCVTQQ2PD"), str8_lit_comp("Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("VCVTQQ2PS"), str8_lit_comp("Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("VCVTSD2USI"), str8_lit_comp("Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer")}, -{str8_lit_comp("VCVTSS2USI"), str8_lit_comp("Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer")}, -{str8_lit_comp("VCVTTPD2QQ"), str8_lit_comp("Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers")}, -{str8_lit_comp("VCVTTPD2UDQ"), str8_lit_comp("Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers")}, -{str8_lit_comp("VCVTTPD2UQQ"), str8_lit_comp("Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers")}, -{str8_lit_comp("VCVTTPS2QQ"), str8_lit_comp("Convert with Truncation Packed Single Precision Floating-Point Values to Packed Signed Quadword Integer Values")}, -{str8_lit_comp("VCVTTPS2UDQ"), str8_lit_comp("Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values")}, -{str8_lit_comp("VCVTTPS2UQQ"), str8_lit_comp("Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values")}, -{str8_lit_comp("VCVTTSD2USI"), str8_lit_comp("Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer")}, -{str8_lit_comp("VCVTTSS2USI"), str8_lit_comp("Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer")}, -{str8_lit_comp("VCVTUDQ2PD"), str8_lit_comp("Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("VCVTUDQ2PS"), str8_lit_comp("Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("VCVTUQQ2PD"), str8_lit_comp("Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("VCVTUQQ2PS"), str8_lit_comp("Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("VCVTUSI2SD"), str8_lit_comp("Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value")}, -{str8_lit_comp("VCVTUSI2SS"), str8_lit_comp("Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value")}, -{str8_lit_comp("VDBPSADBW"), str8_lit_comp("Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes")}, -{str8_lit_comp("VDPBF16PS"), str8_lit_comp("Dot Product of BF16 Pairs Accumulated into Packed Single Precision")}, -{str8_lit_comp("VERR"), str8_lit_comp("Verify a Segment for Reading or Writing")}, -{str8_lit_comp("VERW"), str8_lit_comp("Verify a Segment for Reading or Writing")}, -{str8_lit_comp("VEXPANDPD"), str8_lit_comp("Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory")}, -{str8_lit_comp("VEXPANDPS"), str8_lit_comp("Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory")}, -{str8_lit_comp("VEXTRACTF128"), str8_lit_comp("Extr act Packed Floating-Point Values")}, -{str8_lit_comp("VEXTRACTF32x4"), str8_lit_comp("Extr act Packed Floating-Point Values")}, -{str8_lit_comp("VEXTRACTF32x8"), str8_lit_comp("Extr act Packed Floating-Point Values")}, -{str8_lit_comp("VEXTRACTF64x2"), str8_lit_comp("Extr act Packed Floating-Point Values")}, -{str8_lit_comp("VEXTRACTF64x4"), str8_lit_comp("Extr act Packed Floating-Point Values")}, -{str8_lit_comp("VEXTRACTI128"), str8_lit_comp("Extract packed Integer Values")}, -{str8_lit_comp("VEXTRACTI32x4"), str8_lit_comp("Extract packed Integer Values")}, -{str8_lit_comp("VEXTRACTI32x8"), str8_lit_comp("Extract packed Integer Values")}, -{str8_lit_comp("VEXTRACTI64x2"), str8_lit_comp("Extract packed Integer Values")}, -{str8_lit_comp("VEXTRACTI64x4"), str8_lit_comp("Extract packed Integer Values")}, -{str8_lit_comp("VFIXUPIMMPD"), str8_lit_comp("Fix Up Special Packed Float64 Values")}, -{str8_lit_comp("VFIXUPIMMPS"), str8_lit_comp("Fix Up Special Packed Float32 Values")}, -{str8_lit_comp("VFIXUPIMMSD"), str8_lit_comp("Fix Up Special Scalar Float64 Value")}, -{str8_lit_comp("VFIXUPIMMSS"), str8_lit_comp("Fix Up Special Scalar Float32 Value")}, -{str8_lit_comp("VFMADD132PD"), str8_lit_comp("Fused Multiply-Add of Packed Double- Precision Floating-Point Values")}, -{str8_lit_comp("VFMADD132PS"), str8_lit_comp("Fused Multiply-Add of Packed Single- Precision Floating-Point Values")}, -{str8_lit_comp("VFMADD132SD"), str8_lit_comp("Fused Multiply-Add of Scalar Double- Precision Floating-Point Values")}, -{str8_lit_comp("VFMADD132SS"), str8_lit_comp("Fused Multiply-Add of Scalar Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFMADD213PD"), str8_lit_comp("Fused Multiply-Add of Packed Double- Precision Floating-Point Values")}, -{str8_lit_comp("VFMADD213PS"), str8_lit_comp("Fused Multiply-Add of Packed Single- Precision Floating-Point Values")}, -{str8_lit_comp("VFMADD213SD"), str8_lit_comp("Fused Multiply-Add of Scalar Double- Precision Floating-Point Values")}, -{str8_lit_comp("VFMADD213SS"), str8_lit_comp("Fused Multiply-Add of Scalar Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFMADD231PD"), str8_lit_comp("Fused Multiply-Add of Packed Double- Precision Floating-Point Values")}, -{str8_lit_comp("VFMADD231PS"), str8_lit_comp("Fused Multiply-Add of Packed Single- Precision Floating-Point Values")}, -{str8_lit_comp("VFMADD231SD"), str8_lit_comp("Fused Multiply-Add of Scalar Double- Precision Floating-Point Values")}, -{str8_lit_comp("VFMADD231SS"), str8_lit_comp("Fused Multiply-Add of Scalar Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFMADDSUB132PD"), str8_lit_comp("Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("VFMADDSUB132PS"), str8_lit_comp("Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFMADDSUB213PD"), str8_lit_comp("Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("VFMADDSUB213PS"), str8_lit_comp("Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFMADDSUB231PD"), str8_lit_comp("Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("VFMADDSUB231PS"), str8_lit_comp("Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFMSUB132PD"), str8_lit_comp("Fused Multiply-Subtract of Packed Double- Precision Floating-Point Values")}, -{str8_lit_comp("VFMSUB132PS"), str8_lit_comp("Fused Multiply-Subtract of Packed Single- Precision Floating-Point Values")}, -{str8_lit_comp("VFMSUB132SD"), str8_lit_comp("Fused Multiply-Subtract of Scalar Double- Precision Floating-Point Values")}, -{str8_lit_comp("VFMSUB132SS"), str8_lit_comp("Fused Multiply-Subtract of Scalar Single- Precision Floating-Point Values")}, -{str8_lit_comp("VFMSUB213PD"), str8_lit_comp("Fused Multiply-Subtract of Packed Double- Precision Floating-Point Values")}, -{str8_lit_comp("VFMSUB213PS"), str8_lit_comp("Fused Multiply-Subtract of Packed Single- Precision Floating-Point Values")}, -{str8_lit_comp("VFMSUB213SD"), str8_lit_comp("Fused Multiply-Subtract of Scalar Double- Precision Floating-Point Values")}, -{str8_lit_comp("VFMSUB213SS"), str8_lit_comp("Fused Multiply-Subtract of Scalar Single- Precision Floating-Point Values")}, -{str8_lit_comp("VFMSUB231PD"), str8_lit_comp("Fused Multiply-Subtract of Packed Double- Precision Floating-Point Values")}, -{str8_lit_comp("VFMSUB231PS"), str8_lit_comp("Fused Multiply-Subtract of Packed Single- Precision Floating-Point Values")}, -{str8_lit_comp("VFMSUB231SD"), str8_lit_comp("Fused Multiply-Subtract of Scalar Double- Precision Floating-Point Values")}, -{str8_lit_comp("VFMSUB231SS"), str8_lit_comp("Fused Multiply-Subtract of Scalar Single- Precision Floating-Point Values")}, -{str8_lit_comp("VFMSUBADD132PD"), str8_lit_comp("Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("VFMSUBADD132PS"), str8_lit_comp("Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFMSUBADD213PD"), str8_lit_comp("Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("VFMSUBADD213PS"), str8_lit_comp("Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFMSUBADD231PD"), str8_lit_comp("Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("VFMSUBADD231PS"), str8_lit_comp("Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMADD132PD"), str8_lit_comp("Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMADD132PS"), str8_lit_comp("Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMADD132SD"), str8_lit_comp("Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMADD132SS"), str8_lit_comp("Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMADD213PD"), str8_lit_comp("Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMADD213PS"), str8_lit_comp("Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMADD213SD"), str8_lit_comp("Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMADD213SS"), str8_lit_comp("Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMADD231PD"), str8_lit_comp("Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMADD231PS"), str8_lit_comp("Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMADD231SD"), str8_lit_comp("Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMADD231SS"), str8_lit_comp("Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMSUB132PD"), str8_lit_comp("Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMSUB132PS"), str8_lit_comp("Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMSUB132SD"), str8_lit_comp("Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMSUB132SS"), str8_lit_comp("Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMSUB213PD"), str8_lit_comp("Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMSUB213PS"), str8_lit_comp("Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMSUB213SD"), str8_lit_comp("Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMSUB213SS"), str8_lit_comp("Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMSUB231PD"), str8_lit_comp("Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMSUB231PS"), str8_lit_comp("Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMSUB231SD"), str8_lit_comp("Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values")}, -{str8_lit_comp("VFNMSUB231SS"), str8_lit_comp("Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values")}, -{str8_lit_comp("VFPCLASSPD"), str8_lit_comp("Tests Types Of a Packed Float64 Values")}, -{str8_lit_comp("VFPCLASSPS"), str8_lit_comp("Tests Types Of a Packed Float32 Values")}, -{str8_lit_comp("VFPCLASSSD"), str8_lit_comp("Tests Types Of a Scalar Float64 Values")}, -{str8_lit_comp("VFPCLASSSS"), str8_lit_comp("Tests Types Of a Scalar Float32 Values")}, -{str8_lit_comp("VGATHERDPD"), str8_lit_comp("Gather Packed DP FP Values Using Signed Dword/Qword Indices")}, -{str8_lit_comp("VGATHERDPS"), str8_lit_comp("Gather Packed SP FP values Using Signed Dword/Qword Indices")}, -{str8_lit_comp("VGATHERQPD"), str8_lit_comp("Gather Packed DP FP Values Using Signed Dword/Qword Indices")}, -{str8_lit_comp("VGATHERQPS"), str8_lit_comp("Gather Packed SP FP values Using Signed Dword/Qword Indices")}, -{str8_lit_comp("VGETEXPPD"), str8_lit_comp("Convert Exponents of Packed DP FP Values to DP FP Values")}, -{str8_lit_comp("VGETEXPPS"), str8_lit_comp("Convert Exponents of Packed SP FP Values to SP FP Values")}, -{str8_lit_comp("VGETEXPSD"), str8_lit_comp("Convert Exponents of Scalar DP FP Values to DP FP Value")}, -{str8_lit_comp("VGETEXPSS"), str8_lit_comp("Convert Exponents of Scalar SP FP Values to SP FP Value")}, -{str8_lit_comp("VGETMANTPD"), str8_lit_comp("Extract Float64 Vector of Normalized Mantissas from Float64 Vector")}, -{str8_lit_comp("VGETMANTPS"), str8_lit_comp("Extract Float32 Vector of Normalized Mantissas from Float32 Vector")}, -{str8_lit_comp("VGETMANTSD"), str8_lit_comp("Extract Float64 of Normalized Mantissas from Float64 Scalar")}, -{str8_lit_comp("VGETMANTSS"), str8_lit_comp("Extract Float32 Vector of Normalized Mantissa from Float32 Vector")}, -{str8_lit_comp("VINSERTF128"), str8_lit_comp("Insert Packed Floating-Point Values")}, -{str8_lit_comp("VINSERTF32x4"), str8_lit_comp("Insert Packed Floating-Point Values")}, -{str8_lit_comp("VINSERTF32x8"), str8_lit_comp("Insert Packed Floating-Point Values")}, -{str8_lit_comp("VINSERTF64x2"), str8_lit_comp("Insert Packed Floating-Point Values")}, -{str8_lit_comp("VINSERTF64x4"), str8_lit_comp("Insert Packed Floating-Point Values")}, -{str8_lit_comp("VINSERTI128"), str8_lit_comp("Insert Packed Integer Values")}, -{str8_lit_comp("VINSERTI32x4"), str8_lit_comp("Insert Packed Integer Values")}, -{str8_lit_comp("VINSERTI32x8"), str8_lit_comp("Insert Packed Integer Values")}, -{str8_lit_comp("VINSERTI64x2"), str8_lit_comp("Insert Packed Integer Values")}, -{str8_lit_comp("VINSERTI64x4"), str8_lit_comp("Insert Packed Integer Values")}, -{str8_lit_comp("VMASKMOV"), str8_lit_comp("Conditional SIMD Packed Loads and Stores")}, -{str8_lit_comp("VMOVDQA32"), str8_lit_comp("Move Aligned Packed Integer Values")}, -{str8_lit_comp("VMOVDQA64"), str8_lit_comp("Move Aligned Packed Integer Values")}, -{str8_lit_comp("VMOVDQU16"), str8_lit_comp("Move Unaligned Packed Integer Values")}, -{str8_lit_comp("VMOVDQU32"), str8_lit_comp("Move Unaligned Packed Integer Values")}, -{str8_lit_comp("VMOVDQU64"), str8_lit_comp("Move Unaligned Packed Integer Values")}, -{str8_lit_comp("VMOVDQU8"), str8_lit_comp("Move Unaligned Packed Integer Values")}, -{str8_lit_comp("VP2INTERSECTD"), str8_lit_comp("Compute Intersection Between DWORDS/QUADWORDS to a Pair of Mask Registers")}, -{str8_lit_comp("VP2INTERSECTQ"), str8_lit_comp("Compute Intersection Between DWORDS/QUADWORDS to a Pair of Mask Registers")}, -{str8_lit_comp("VPBLENDD"), str8_lit_comp("Blend Packed Dwords")}, -{str8_lit_comp("VPBLENDMB"), str8_lit_comp("Blend Byte/Word Vectors Using an Opmask Control")}, -{str8_lit_comp("VPBLENDMD"), str8_lit_comp("Blend Int32/Int64 Vectors Using an OpMask Control")}, -{str8_lit_comp("VPBLENDMQ"), str8_lit_comp("Blend Int32/Int64 Vectors Using an OpMask Control")}, -{str8_lit_comp("VPBLENDMW"), str8_lit_comp("Blend Byte/Word Vectors Using an Opmask Control")}, -{str8_lit_comp("VPBROADCAST"), str8_lit_comp("Load Integer and Broadcast")}, -{str8_lit_comp("VPBROADCASTB"), str8_lit_comp("Load with Broadcast Integer Data from General Purpose Register")}, -{str8_lit_comp("VPBROADCASTD"), str8_lit_comp("Load with Broadcast Integer Data from General Purpose Register")}, -{str8_lit_comp("VPBROADCASTM"), str8_lit_comp("Broadcast Mask to Vector Register")}, -{str8_lit_comp("VPBROADCASTQ"), str8_lit_comp("Load with Broadcast Integer Data from General Purpose Register")}, -{str8_lit_comp("VPBROADCASTW"), str8_lit_comp("Load with Broadcast Integer Data from General Purpose Register")}, -{str8_lit_comp("VPCMPB"), str8_lit_comp("Compare Packed Byte Values Into Mask")}, -{str8_lit_comp("VPCMPD"), str8_lit_comp("Compare Packed Integer Values into Mask")}, -{str8_lit_comp("VPCMPQ"), str8_lit_comp("Compare Packed Integer Values into Mask")}, -{str8_lit_comp("VPCMPUB"), str8_lit_comp("Compare Packed Byte Values Into Mask")}, -{str8_lit_comp("VPCMPUD"), str8_lit_comp("Compare Packed Integer Values into Mask")}, -{str8_lit_comp("VPCMPUQ"), str8_lit_comp("Compare Packed Integer Values into Mask")}, -{str8_lit_comp("VPCMPUW"), str8_lit_comp("Compare Packed Word Values Into Mask")}, -{str8_lit_comp("VPCMPW"), str8_lit_comp("Compare Packed Word Values Into Mask")}, -{str8_lit_comp("VPCOMPRESSB"), str8_lit_comp("Store Sparse Packed Byte/Word Integer Values into Dense Memory/Register")}, -{str8_lit_comp("VPCOMPRESSD"), str8_lit_comp("Store Sparse Packed Doubleword Integer Values into Dense Memory/Register")}, -{str8_lit_comp("VPCOMPRESSQ"), str8_lit_comp("Store Sparse Packed Quadword Integer Values into Dense Memory/Register")}, -{str8_lit_comp("VPCONFLICTD"), str8_lit_comp("Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense Memory/ Register")}, -{str8_lit_comp("VPCONFLICTQ"), str8_lit_comp("Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense Memory/ Register")}, -{str8_lit_comp("VPDPBUSD"), str8_lit_comp("Multiply and Add Unsigned and Signed Bytes")}, -{str8_lit_comp("VPDPBUSDS"), str8_lit_comp("Multiply and Add Unsigned and Signed Bytes with Saturation")}, -{str8_lit_comp("VPDPWSSD"), str8_lit_comp("Multiply and Add Signed Word Integers")}, -{str8_lit_comp("VPDPWSSDS"), str8_lit_comp("Multiply and Add Signed Word Integers with Saturation")}, -{str8_lit_comp("VPERM2F128"), str8_lit_comp("Permute Floating-Point Values")}, -{str8_lit_comp("VPERM2I128"), str8_lit_comp("Permute Integer Values")}, -{str8_lit_comp("VPERMB"), str8_lit_comp("Permute Packed Bytes Elements")}, -{str8_lit_comp("VPERMD"), str8_lit_comp("Permute Packed Doublewords/Words Elements")}, -{str8_lit_comp("VPERMI2B"), str8_lit_comp("Full Permute of Bytes from Two Tables Overwriting the Index")}, -{str8_lit_comp("VPERMI2D"), str8_lit_comp("Full Permute From Two Tables Overwriting the Index")}, -{str8_lit_comp("VPERMI2PD"), str8_lit_comp("Full Permute From Two Tables Overwriting the Index")}, -{str8_lit_comp("VPERMI2PS"), str8_lit_comp("Full Permute From Two Tables Overwriting the Index")}, -{str8_lit_comp("VPERMI2Q"), str8_lit_comp("Full Permute From Two Tables Overwriting the Index")}, -{str8_lit_comp("VPERMI2W"), str8_lit_comp("Full Permute From Two Tables Overwriting the Index")}, -{str8_lit_comp("VPERMILPD"), str8_lit_comp("Permute In-Lane of Pairs of Double-Precision Floating-Point Values")}, -{str8_lit_comp("VPERMILPS"), str8_lit_comp("Permute In-Lane of Quadruples of Single-Precision Floating-Point Values")}, -{str8_lit_comp("VPERMPD"), str8_lit_comp("Permute Double-Precision Floating-Point Elements")}, -{str8_lit_comp("VPERMPS"), str8_lit_comp("Permute Single-Precision Floating-Point Elements")}, -{str8_lit_comp("VPERMQ"), str8_lit_comp("Qwords Element Permutation")}, -{str8_lit_comp("VPERMT2B"), str8_lit_comp("Full Permute of Bytes from Two Tables Overwriting a Table")}, -{str8_lit_comp("VPERMT2D"), str8_lit_comp("Full Permute from Two Tables Overwriting one Table")}, -{str8_lit_comp("VPERMT2PD"), str8_lit_comp("Full Permute from Two Tables Overwriting one Table")}, -{str8_lit_comp("VPERMT2PS"), str8_lit_comp("Full Permute from Two Tables Overwriting one Table")}, -{str8_lit_comp("VPERMT2Q"), str8_lit_comp("Full Permute from Two Tables Overwriting one Table")}, -{str8_lit_comp("VPERMT2W"), str8_lit_comp("Full Permute from Two Tables Overwriting one Table")}, -{str8_lit_comp("VPERMW"), str8_lit_comp("Permute Packed Doublewords/Words Elements")}, -{str8_lit_comp("VPEXPANDB"), str8_lit_comp("Expand Byte/Word Values")}, -{str8_lit_comp("VPEXPANDD"), str8_lit_comp("Load Sparse Packed Doubleword Integer Values from Dense Memory / Register")}, -{str8_lit_comp("VPEXPANDQ"), str8_lit_comp("Load Sparse Packed Quadword Integer Values from Dense Memory / Register")}, -{str8_lit_comp("VPEXPANDW"), str8_lit_comp("Expand Byte/Word Values")}, -{str8_lit_comp("VPGATHERDD"), str8_lit_comp("Gather Packed Dword Values Using Signed Dword/Qword Indices")}, -{str8_lit_comp("VPGATHERDQ"), str8_lit_comp("Gather Packed Dword, Packed Qword with Signed Dword Indices")}, -{str8_lit_comp("VPGATHERQD"), str8_lit_comp("Gather Packed Dword Values Using Signed Dword/Qword Indices")}, -{str8_lit_comp("VPGATHERQQ"), str8_lit_comp("Gather Packed Qword Values Using Signed Dword/Qword Indices")}, -{str8_lit_comp("VPLZCNTD"), str8_lit_comp("Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values")}, -{str8_lit_comp("VPLZCNTQ"), str8_lit_comp("Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values")}, -{str8_lit_comp("VPMADD52HUQ"), str8_lit_comp("Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to 64-bit Accumulators")}, -{str8_lit_comp("VPMADD52LUQ"), str8_lit_comp("Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Qword Accumulators")}, -{str8_lit_comp("VPMASKMOV"), str8_lit_comp("Conditional SIMD Integer Packed Loads and Stores")}, -{str8_lit_comp("VPMOVB2M"), str8_lit_comp("Convert a Vector Register to a Mask")}, -{str8_lit_comp("VPMOVD2M"), str8_lit_comp("Convert a Vector Register to a Mask")}, -{str8_lit_comp("VPMOVDB"), str8_lit_comp("Down Convert DWord to Byte")}, -{str8_lit_comp("VPMOVDW"), str8_lit_comp("Down Convert DWord to Word")}, -{str8_lit_comp("VPMOVM2B"), str8_lit_comp("Convert a Mask Register to a Vector Register")}, -{str8_lit_comp("VPMOVM2D"), str8_lit_comp("Convert a Mask Register to a Vector Register")}, -{str8_lit_comp("VPMOVM2Q"), str8_lit_comp("Convert a Mask Register to a Vector Register")}, -{str8_lit_comp("VPMOVM2W"), str8_lit_comp("Convert a Mask Register to a Vector Register")}, -{str8_lit_comp("VPMOVQ2M"), str8_lit_comp("Convert a Vector Register to a Mask")}, -{str8_lit_comp("VPMOVQB"), str8_lit_comp("Down Convert QWord to Byte")}, -{str8_lit_comp("VPMOVQD"), str8_lit_comp("Down Convert QWord to DWord")}, -{str8_lit_comp("VPMOVQW"), str8_lit_comp("Down Convert QWord to Word")}, -{str8_lit_comp("VPMOVSDB"), str8_lit_comp("Down Convert DWord to Byte")}, -{str8_lit_comp("VPMOVSDW"), str8_lit_comp("Down Convert DWord to Word")}, -{str8_lit_comp("VPMOVSQB"), str8_lit_comp("Down Convert QWord to Byte")}, -{str8_lit_comp("VPMOVSQD"), str8_lit_comp("Down Convert QWord to DWord")}, -{str8_lit_comp("VPMOVSQW"), str8_lit_comp("Down Convert QWord to Word")}, -{str8_lit_comp("VPMOVSWB"), str8_lit_comp("Down Convert Word to Byte")}, -{str8_lit_comp("VPMOVUSDB"), str8_lit_comp("Down Convert DWord to Byte")}, -{str8_lit_comp("VPMOVUSDW"), str8_lit_comp("Down Convert DWord to Word")}, -{str8_lit_comp("VPMOVUSQB"), str8_lit_comp("Down Convert QWord to Byte")}, -{str8_lit_comp("VPMOVUSQD"), str8_lit_comp("Down Convert QWord to DWord")}, -{str8_lit_comp("VPMOVUSQW"), str8_lit_comp("Down Convert QWord to Word")}, -{str8_lit_comp("VPMOVUSWB"), str8_lit_comp("Down Convert Word to Byte")}, -{str8_lit_comp("VPMOVW2M"), str8_lit_comp("Convert a Vector Register to a Mask")}, -{str8_lit_comp("VPMOVWB"), str8_lit_comp("Down Convert Word to Byte")}, -{str8_lit_comp("VPMULTISHIFTQB"), str8_lit_comp("Select Packed Unaligned Bytes from Quadword Sources")}, -{str8_lit_comp("VPOPCNT"), str8_lit_comp("Return the Count of Number of Bits Set to 1 in BYTE/WORD/DWORD/QWORD")}, -{str8_lit_comp("VPROLD"), str8_lit_comp("Bit Rotate Left")}, -{str8_lit_comp("VPROLQ"), str8_lit_comp("Bit Rotate Left")}, -{str8_lit_comp("VPROLVD"), str8_lit_comp("Bit Rotate Left")}, -{str8_lit_comp("VPROLVQ"), str8_lit_comp("Bit Rotate Left")}, -{str8_lit_comp("VPRORD"), str8_lit_comp("Bit Rotate Right")}, -{str8_lit_comp("VPRORQ"), str8_lit_comp("Bit Rotate Right")}, -{str8_lit_comp("VPRORVD"), str8_lit_comp("Bit Rotate Right")}, -{str8_lit_comp("VPRORVQ"), str8_lit_comp("Bit Rotate Right")}, -{str8_lit_comp("VPSCATTERDD"), str8_lit_comp("Scatter Packed Dword, Packed Qword with Signed Dword, Signed Qword Indices")}, -{str8_lit_comp("VPSCATTERDQ"), str8_lit_comp("Scatter Packed Dword, Packed Qword with Signed Dword, Signed Qword Indices")}, -{str8_lit_comp("VPSCATTERQD"), str8_lit_comp("Scatter Packed Dword, Packed Qword with Signed Dword, Signed Qword Indices")}, -{str8_lit_comp("VPSCATTERQQ"), str8_lit_comp("Scatter Packed Dword, Packed Qword with Signed Dword, Signed Qword Indices")}, -{str8_lit_comp("VPSHLD"), str8_lit_comp("Concatenate and Shift Packed Data Left Logical")}, -{str8_lit_comp("VPSHLDV"), str8_lit_comp("Concatenate and Variable Shift Packed Data Left Logical")}, -{str8_lit_comp("VPSHRD"), str8_lit_comp("Concatenate and Shift Packed Data Right Logical")}, -{str8_lit_comp("VPSHRDV"), str8_lit_comp("Concatenate and Variable Shift Packed Data Right Logical")}, -{str8_lit_comp("VPSHUFBITQMB"), str8_lit_comp("Shuffle Bits from Quadword Elements Using Byte Indexes into Mask")}, -{str8_lit_comp("VPSLLVD"), str8_lit_comp("Variable Bit Shift Left Logical")}, -{str8_lit_comp("VPSLLVQ"), str8_lit_comp("Variable Bit Shift Left Logical")}, -{str8_lit_comp("VPSLLVW"), str8_lit_comp("Variable Bit Shift Left Logical")}, -{str8_lit_comp("VPSRAVD"), str8_lit_comp("Variable Bit Shift Right Arithmetic")}, -{str8_lit_comp("VPSRAVQ"), str8_lit_comp("Variable Bit Shift Right Arithmetic")}, -{str8_lit_comp("VPSRAVW"), str8_lit_comp("Variable Bit Shift Right Arithmetic")}, -{str8_lit_comp("VPSRLVD"), str8_lit_comp("Variable Bit Shift Right Logical")}, -{str8_lit_comp("VPSRLVQ"), str8_lit_comp("Variable Bit Shift Right Logical")}, -{str8_lit_comp("VPSRLVW"), str8_lit_comp("Variable Bit Shift Right Logical")}, -{str8_lit_comp("VPTERNLOGD"), str8_lit_comp("Bitwise Ternary Logic")}, -{str8_lit_comp("VPTERNLOGQ"), str8_lit_comp("Bitwise Ternary Logic")}, -{str8_lit_comp("VPTESTMB"), str8_lit_comp("Logical AND and Set Mask")}, -{str8_lit_comp("VPTESTMD"), str8_lit_comp("Logical AND and Set Mask")}, -{str8_lit_comp("VPTESTMQ"), str8_lit_comp("Logical AND and Set Mask")}, -{str8_lit_comp("VPTESTMW"), str8_lit_comp("Logical AND and Set Mask")}, -{str8_lit_comp("VPTESTNMB"), str8_lit_comp("Logical NAND and Set")}, -{str8_lit_comp("VPTESTNMD"), str8_lit_comp("Logical NAND and Set")}, -{str8_lit_comp("VPTESTNMQ"), str8_lit_comp("Logical NAND and Set")}, -{str8_lit_comp("VPTESTNMW"), str8_lit_comp("Logical NAND and Set")}, -{str8_lit_comp("VRANGEPD"), str8_lit_comp("Range Restriction Calculation For Packed Pairs of Float64 Values")}, -{str8_lit_comp("VRANGEPS"), str8_lit_comp("Range Restriction Calculation For Packed Pairs of Float32 Values")}, -{str8_lit_comp("VRANGESD"), str8_lit_comp("Range Restriction Calculation From a pair of Scalar Float64 Values")}, -{str8_lit_comp("VRANGESS"), str8_lit_comp("Range Restriction Calculation From a Pair of Scalar Float32 Values")}, -{str8_lit_comp("VRCP14PD"), str8_lit_comp("Compute Approximate Reciprocals of Packed Float64 Values")}, -{str8_lit_comp("VRCP14PS"), str8_lit_comp("Compute Approximate Reciprocals of Packed Float32 Values")}, -{str8_lit_comp("VRCP14SD"), str8_lit_comp("Compute Approximate Reciprocal of Scalar Float64 Value")}, -{str8_lit_comp("VRCP14SS"), str8_lit_comp("Compute Approximate Reciprocal of Scalar Float32 Value")}, -{str8_lit_comp("VREDUCEPD"), str8_lit_comp("Perform Reduction Transformation on Packed Float64 Values")}, -{str8_lit_comp("VREDUCEPS"), str8_lit_comp("Perform Reduction Transformation on Packed Float32 Values")}, -{str8_lit_comp("VREDUCESD"), str8_lit_comp("Perform a Reduction Transformation on a Scalar Float64 Value")}, -{str8_lit_comp("VREDUCESS"), str8_lit_comp("Perform a Reduction Transformation on a Scalar Float32 Value")}, -{str8_lit_comp("VRNDSCALEPD"), str8_lit_comp("Round Packed Float64 Values To Include A Given Number Of Fraction Bits")}, -{str8_lit_comp("VRNDSCALEPS"), str8_lit_comp("Round Packed Float32 Values To Include A Given Number Of Fraction Bits")}, -{str8_lit_comp("VRNDSCALESD"), str8_lit_comp("Round Scalar Float64 Value To Include A Given Number Of Fraction Bits")}, -{str8_lit_comp("VRNDSCALESS"), str8_lit_comp("Round Scalar Float32 Value To Include A Given Number Of Fraction Bits")}, -{str8_lit_comp("VRSQRT14PD"), str8_lit_comp("Compute Approximate Reciprocals of Square Roots of Packed Float64 Values")}, -{str8_lit_comp("VRSQRT14PS"), str8_lit_comp("Compute Approximate Reciprocals of Square Roots of Packed Float32 Values")}, -{str8_lit_comp("VRSQRT14SD"), str8_lit_comp("Compute Approximate Reciprocal of Square Root of Scalar Float64 Value")}, -{str8_lit_comp("VRSQRT14SS"), str8_lit_comp("Compute Approximate Reciprocal of Square Root of Scalar Float32 Value")}, -{str8_lit_comp("VSCALEFPD"), str8_lit_comp("Scale Packed Float64 Values With Float64 Values")}, -{str8_lit_comp("VSCALEFPS"), str8_lit_comp("Scale Packed Float32 Values With Float32 Values")}, -{str8_lit_comp("VSCALEFSD"), str8_lit_comp("Scale Scalar Float64 Values With Float64 Values")}, -{str8_lit_comp("VSCALEFSS"), str8_lit_comp("Scale Scalar Float32 Value With Float32 Value")}, -{str8_lit_comp("VSCATTERDPD"), str8_lit_comp("Scatter Packed Single, Packed Double with Signed Dword and Qword Indices")}, -{str8_lit_comp("VSCATTERDPS"), str8_lit_comp("Scatter Packed Single, Packed Double with Signed Dword and Qword Indices")}, -{str8_lit_comp("VSCATTERQPD"), str8_lit_comp("Scatter Packed Single, Packed Double with Signed Dword and Qword Indices")}, -{str8_lit_comp("VSCATTERQPS"), str8_lit_comp("Scatter Packed Single, Packed Double with Signed Dword and Qword Indices")}, -{str8_lit_comp("VSHUFF32x4"), str8_lit_comp("Shuffle Packed Values at 128-bit Granularity")}, -{str8_lit_comp("VSHUFF64x2"), str8_lit_comp("Shuffle Packed Values at 128-bit Granularity")}, -{str8_lit_comp("VSHUFI32x4"), str8_lit_comp("Shuffle Packed Values at 128-bit Granularity")}, -{str8_lit_comp("VSHUFI64x2"), str8_lit_comp("Shuffle Packed Values at 128-bit Granularity")}, -{str8_lit_comp("VTESTPD"), str8_lit_comp("Packed Bit Test")}, -{str8_lit_comp("VTESTPS"), str8_lit_comp("Packed Bit Test")}, -{str8_lit_comp("VZEROALL"), str8_lit_comp("Zero XMM, YMM and ZMM Registers")}, -{str8_lit_comp("VZEROUPPER"), str8_lit_comp("Zero Upper Bits of YMM and ZMM Registers")}, -{str8_lit_comp("WAIT"), str8_lit_comp("Wait")}, -{str8_lit_comp("WBINVD"), str8_lit_comp("Write Back and Invalidate Cache")}, -{str8_lit_comp("WBNOINVD"), str8_lit_comp("Write Back and Do Not Invalidate Cache")}, -{str8_lit_comp("WRFSBASE"), str8_lit_comp("Write FS/GS Segment Base")}, -{str8_lit_comp("WRGSBASE"), str8_lit_comp("Write FS/GS Segment Base")}, -{str8_lit_comp("WRMSR"), str8_lit_comp("Write to Model Specific Register")}, -{str8_lit_comp("WRPKRU"), str8_lit_comp("Write Data to User Page Key Register")}, -{str8_lit_comp("WRSSD"), str8_lit_comp("Write to Shadow Stack")}, -{str8_lit_comp("WRSSQ"), str8_lit_comp("Write to Shadow Stack")}, -{str8_lit_comp("WRUSSD"), str8_lit_comp("Write to User Shadow Stack")}, -{str8_lit_comp("WRUSSQ"), str8_lit_comp("Write to User Shadow Stack")}, -{str8_lit_comp("XABORT"), str8_lit_comp("Transactional Abort")}, -{str8_lit_comp("XACQUIRE"), str8_lit_comp("Hardware Lock Elision Prefix Hints")}, -{str8_lit_comp("XADD"), str8_lit_comp("Exchange and Add")}, -{str8_lit_comp("XBEGIN"), str8_lit_comp("Transactional Begin")}, -{str8_lit_comp("XCHG"), str8_lit_comp("Exchange Register/Memory with Register")}, -{str8_lit_comp("XEND"), str8_lit_comp("Transactional End")}, -{str8_lit_comp("XGETBV"), str8_lit_comp("Get Value of Extended Control Register")}, -{str8_lit_comp("XLAT"), str8_lit_comp("Table Look-up Translation")}, -{str8_lit_comp("XLATB"), str8_lit_comp("Table Look-up Translation")}, -{str8_lit_comp("XOR"), str8_lit_comp("Logical Exclusive OR")}, -{str8_lit_comp("XORPD"), str8_lit_comp("Bitwise Logical XOR of Packed Double Precision Floating-Point Values")}, -{str8_lit_comp("XORPS"), str8_lit_comp("Bitwise Logical XOR of Packed Single Precision Floating-Point Values")}, -{str8_lit_comp("XRELEASE"), str8_lit_comp("Hardware Lock Elision Prefix Hints")}, -{str8_lit_comp("XRSTOR"), str8_lit_comp("Restore Processor Extended States")}, -{str8_lit_comp("XRSTORS"), str8_lit_comp("Restore Processor Extended States Supervisor")}, -{str8_lit_comp("XSAVE"), str8_lit_comp("Save Processor Extended States")}, -{str8_lit_comp("XSAVEC"), str8_lit_comp("Save Processor Extended States with Compaction")}, -{str8_lit_comp("XSAVEOPT"), str8_lit_comp("Save Processor Extended States Optimized")}, -{str8_lit_comp("XSAVES"), str8_lit_comp("Save Processor Extended States Supervisor")}, -{str8_lit_comp("XSETBV"), str8_lit_comp("Set Extended Control Register")}, -{str8_lit_comp("XTEST"), str8_lit_comp("Test If In Transactional Execution")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("Execute an Enclave System Function of Specified Leaf Number")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[EADD] Add a Page to an Uninitialized Enclave")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[EAUG] Add a Page to an Initialized Enclave")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[EBLOCK] Mark a page in EPC as Blocked")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[ECREATE] Create an SECS page in the Enclave Page Cache")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[EDBGRD] Read From a Debug Enclave")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[EDBGWR] Write to a Debug Enclave")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[EEXTEND] Extend Uninitialized Enclave Measurement by 256 Bytes")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[EINIT] Initialize an Enclave for Execution")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[ELDBC] Load an EPC Page and Mark its State")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[ELDB] Load an EPC Page and Mark its State")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[ELDUC] Load an EPC Page and Mark its State")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[ELDU] Load an EPC Page and Mark its State")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[EMODPR] Restrict the Permissions of an EPC Page")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[EMODT] Change the Type of an EPC Page")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[EPA] Add Version Array")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[ERDINFO] Read Type and Status Information About an EPC Page")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[EREMOVE] Remove a page from the EPC")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[ETRACKC] Activates EBLOCK Checks")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[ETRACK] Activates EBLOCK Checks")}, -{str8_lit_comp("ENCLS"), str8_lit_comp("[EWB] Invalidate an EPC Page and Write out to Main Memory")}, -{str8_lit_comp("ENCLU"), str8_lit_comp("Execute an Enclave User Function of Specified Leaf Number")}, -{str8_lit_comp("ENCLU"), str8_lit_comp("[EACCEPTCOPY] Initialize a Pending Page")}, -{str8_lit_comp("ENCLU"), str8_lit_comp("[EACCEPT] Accept Changes to an EPC Page")}, -{str8_lit_comp("ENCLU"), str8_lit_comp("[EENTER] Enters an Enclave")}, -{str8_lit_comp("ENCLU"), str8_lit_comp("[EEXIT] Exits an Enclave")}, -{str8_lit_comp("ENCLU"), str8_lit_comp("[EGETKEY] Retrieves a Cryptographic Key")}, -{str8_lit_comp("ENCLU"), str8_lit_comp("[EMODPE] Extend an EPC Page Permissions")}, -{str8_lit_comp("ENCLU"), str8_lit_comp("[EREPORT] Create a Cryptographic Report of the Enclave")}, -{str8_lit_comp("ENCLU"), str8_lit_comp("[ERESUME] Re-Enters an Enclave")}, -{str8_lit_comp("ENCLV"), str8_lit_comp("Execute an Enclave VMM Function of Specified Leaf Number")}, -{str8_lit_comp("INVEPT"), str8_lit_comp("Invalidate Translations Derived from EPT")}, -{str8_lit_comp("INVVPID"), str8_lit_comp("Invalidate Translations Based on VPID")}, -{str8_lit_comp("VMCALL"), str8_lit_comp("Call to VM Monitor")}, -{str8_lit_comp("VMCLEAR"), str8_lit_comp("Clear Virtual-Machine Control Structure")}, -{str8_lit_comp("VMFUNC"), str8_lit_comp("Invoke VM function")}, -{str8_lit_comp("VMLAUNCH"), str8_lit_comp("Launch/Resume Virtual Machine")}, -{str8_lit_comp("VMPTRLD"), str8_lit_comp("Load Pointer to Virtual-Machine Control Structure")}, -{str8_lit_comp("VMPTRST"), str8_lit_comp("Store Pointer to Virtual-Machine Control Structure")}, -{str8_lit_comp("VMREAD"), str8_lit_comp("Read Field from Virtual-Machine Control Structure")}, -{str8_lit_comp("VMRESUME"), str8_lit_comp("Launch/Resume Virtual Machine")}, -{str8_lit_comp("VMWRITE"), str8_lit_comp("Write Field to Virtual-Machine Control Structure")}, -{str8_lit_comp("VMXOFF"), str8_lit_comp("Leave VMX Operation")}, -{str8_lit_comp("VMXON"), str8_lit_comp("Enter VMX Operation")}, -{str8_lit_comp("PREFETCHWT1"), str8_lit_comp("Prefetch Vector Data Into Caches with Intent to Write and T1 Hint")}, -{str8_lit_comp("V4FMADDPS"), str8_lit_comp("Packed Single-Precision Floating-Point Fused Multiply-Add (4-iterations)")}, -{str8_lit_comp("V4FMADDSS"), str8_lit_comp("Scalar Single-Precision Floating-Point Fused Multiply-Add (4-iterations)")}, -{str8_lit_comp("V4FNMADDPS"), str8_lit_comp("Packed Single-Precision Floating-Point Fused Multiply-Add (4-iterations)")}, -{str8_lit_comp("V4FNMADDSS"), str8_lit_comp("Scalar Single-Precision Floating-Point Fused Multiply-Add (4-iterations)")}, -{str8_lit_comp("VEXP2PD"), str8_lit_comp("Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error")}, -{str8_lit_comp("VEXP2PS"), str8_lit_comp("Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error")}, -{str8_lit_comp("VGATHERPF0DPD"), str8_lit_comp("Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint")}, -{str8_lit_comp("VGATHERPF0DPS"), str8_lit_comp("Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint")}, -{str8_lit_comp("VGATHERPF0QPD"), str8_lit_comp("Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint")}, -{str8_lit_comp("VGATHERPF0QPS"), str8_lit_comp("Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint")}, -{str8_lit_comp("VGATHERPF1DPD"), str8_lit_comp("Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint")}, -{str8_lit_comp("VGATHERPF1DPS"), str8_lit_comp("Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint")}, -{str8_lit_comp("VGATHERPF1QPD"), str8_lit_comp("Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint")}, -{str8_lit_comp("VGATHERPF1QPS"), str8_lit_comp("Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint")}, -{str8_lit_comp("VP4DPWSSD"), str8_lit_comp("Dot Product of Signed Words with Dword Accumulation (4-iterations)")}, -{str8_lit_comp("VP4DPWSSDS"), str8_lit_comp("Dot Product of Signed Words with Dword Accumulation and Saturation (4-iterations)")}, -{str8_lit_comp("VRCP28PD"), str8_lit_comp("Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error")}, -{str8_lit_comp("VRCP28PS"), str8_lit_comp("Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error")}, -{str8_lit_comp("VRCP28SD"), str8_lit_comp("Approximation to the Reciprocal of Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error")}, -{str8_lit_comp("VRCP28SS"), str8_lit_comp("Approximation to the Reciprocal of Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error")}, -{str8_lit_comp("VRSQRT28PD"), str8_lit_comp("Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error")}, -{str8_lit_comp("VRSQRT28PS"), str8_lit_comp("Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error")}, -{str8_lit_comp("VRSQRT28SD"), str8_lit_comp("Approximation to the Reciprocal Square Root of Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error")}, -{str8_lit_comp("VRSQRT28SS"), str8_lit_comp("Approximation to the Reciprocal Square Root of Scalar Single-Precision Floating- Point Value with Less Than 2^-28 Relative Error")}, -{str8_lit_comp("VSCATTERPF0DPD"), str8_lit_comp("Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write")}, -{str8_lit_comp("VSCATTERPF0DPS"), str8_lit_comp("Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write")}, -{str8_lit_comp("VSCATTERPF0QPD"), str8_lit_comp("Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write")}, -{str8_lit_comp("VSCATTERPF0QPS"), str8_lit_comp("Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write")}, -{str8_lit_comp("VSCATTERPF1DPD"), str8_lit_comp("Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write")}, -{str8_lit_comp("VSCATTERPF1DPS"), str8_lit_comp("Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write")}, -{str8_lit_comp("VSCATTERPF1QPD"), str8_lit_comp("Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write")}, -{str8_lit_comp("VSCATTERPF1QPS"), str8_lit_comp("Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write")}, -}; - global B32 DEV_telemetry_capture = 0; global B32 DEV_simulate_lag = 0; global B32 DEV_draw_ui_text_pos = 0;