mirror of
https://github.com/Ed94/pikuma_ps1.git
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212 lines
7.3 KiB
C
212 lines
7.3 KiB
C
#ifdef INTELLISENSE_DIRECTIVES
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# pragma once
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# include "dsl.h"
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# include "gcc_asm.h"
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#endif
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enum {
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/* --- MIPS CPU Registers --- */
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R_0 = 0, R_AT = 1, R_V0 = 2, R_V1 = 3,
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R_A0 = 4, R_A1 = 5, R_A2 = 6, R_A3 = 7,
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R_T0 = 8, R_T1 = 9, R_T2 = 10, R_T3 = 11,
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R_T4 = 12, R_T5 = 13, R_T6 = 14, R_T7 = 15,
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R_S0 = 16, R_S1 = 17, R_S2 = 18, R_S3 = 19,
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R_S4 = 20, R_S5 = 21, R_S6 = 22, R_S7 = 23,
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R_T8 = 24, R_T9 = 25, R_K0 = 26, R_K1 = 27,
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R_GP = 28, R_SP = 29, R_FP = 30, R_RA = 31
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/* Semantic Aliases for MIPS Registers (O32 ABI) */
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, rdiscard = R_0 /* Hardwired to 0 */
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, rret_0 = R_V0 /* Function return value */
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, rret_1 = R_V1 /* Second return value (e.g., 64-bit) */
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, rarg_0 = R_A0 /* First function argument */
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, rarg_1 = R_A1 /* Second function argument */
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, rarg_2 = R_A2 /* Third function argument */
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, rarg_3 = R_A3 /* Fourth function argument */
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, rtmp_0 = R_T0 /* Temporary (Caller saved) */
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, rtmp_1 = R_T1 /* Temporary (Caller saved) */
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, rtmp_2 = R_T2 /* Temporary (Caller saved) */
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, rsaved_0 = R_S0 /* Saved register (Callee saved) */
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, rstack_ptr = R_SP /* Stack Pointer */
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, rret_addr = R_RA /* Return Address (populated by JAL) */
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/* --- MIPS CPU Opcodes (Bits 31-26) --- */
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, op_special = 0x00 /* R-Type instructions (uses FUNCT field) */
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, op_bcond = 0x01 /* Branch on condition */
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, op_j = 0x02 /* Jump */
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, op_jal = 0x03 /* Jump and Link */
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, op_beq = 0x04 /* Branch on Equal */
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, op_bne = 0x05 /* Branch on Not Equal */
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, op_blez = 0x06 /* Branch on Less Than or Equal to Zero */
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, op_bgtz = 0x07 /* Branch on Greater Than Zero */
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, op_addi = 0x08 /* Add Immediate */
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, op_addiu = 0x09 /* Add Immediate Unsigned */
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, op_slti = 0x0A /* Set on Less Than Immediate */
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, op_sltiu = 0x0B /* Set on Less Than Immediate Unsigned */
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, op_andi = 0x0C /* AND Immediate */
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, op_ori = 0x0D /* OR Immediate */
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, op_xori = 0x0E /* XOR Immediate */
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, op_lui = 0x0F /* Load Upper Immediate */
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, op_cop0 = 0x10 /* Coprocessor 0 (System) */
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, op_cop2 = 0x12 /* Coprocessor 2 (GTE) */
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, op_la = 0
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, op_li = 0
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, op_lb = 0x20 /* Load Byte */
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, op_lh = 0x21 /* Load Halfword */
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, op_lw = 0x23 /* Load Word */
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, op_lbu = 0x24 /* Load Byte Unsigned */
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, op_lhu = 0x25 /* Load Halfword Unsigned */
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, op_sb = 0x28 /* Store Byte */
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, op_sh = 0x29 /* Store Halfword */
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, op_sw = 0x2B /* Store Word */
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, op_load_addr = op_la
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, op_load_imm = op_li
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, op_jump = op_j
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, op_jump_nlink = op_jal
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/* --- MIPS CPU Function Codes (Bits 5-0, used when OP == MIPS_OP_SPECIAL) --- */
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, fc_sll = 0x00 /* Shift Word Left Logical */
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, fc_srl = 0x02 /* Shift Word Right Logical */
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, fc_sra = 0x03 /* Shift Word Right Arithmetic */
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, fc_sllv = 0x04 /* Shift Word Left Logical Variable */
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, fc_srlv = 0x06 /* Shift Word Right Logical Variable */
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, fc_srav = 0x07 /* Shift Word Right Arithmetic Variable */
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, fc_jr = 0x08 /* Jump Register */
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, fc_jalr = 0x09 /* Jump and Link Register */
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, fc_syscall = 0x0C /* System Call */
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, fc_break = 0x0D /* Breakpoint */
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, fc_mfhi = 0x10 /* Move From HI */
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, fc_mthi = 0x11 /* Move To HI */
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, fc_mflo = 0x12 /* Move From LO */
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, fc_mtlo = 0x13 /* Move To LO */
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, fc_mult = 0x18 /* Multiply Word */
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, fc_multu = 0x19 /* Multiply Unsigned Word */
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, fc_div = 0x1A /* Divide Word */
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, fc_divu = 0x1B /* Divide Unsigned Word */
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, fc_add = 0x20 /* Add Word */
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, fc_addu = 0x21 /* Add Unsigned Word */
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, fc_sub = 0x22 /* Subtract Word */
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, fc_subu = 0x23 /* Subtract Unsigned Word */
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, fc_and = 0x24 /* AND */
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, fc_or = 0x25 /* OR */
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, fc_xor = 0x26 /* XOR */
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, fc_nor = 0x27 /* NOR */
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, fc_slt = 0x2A /* Set on Less Than */
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, fc_sltu = 0x2B /* Set on Less Than Unsigned */
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, fc_jump_reg = fc_jr
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/* --- Coprocessor 0 (System Control & Exceptions) --- */
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, cop_mf = 0x00 /* Move From Coprocessor */
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, cop_mt = 0x04 /* Move To Coprocessor */
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};
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// Bitfield Packets (Encoders)
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enum { _BitOffsets = 0
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/* Bit Offsets for MIPS Instruction Fields */
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, OPCODE_SHIFT = 26
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, RS_SHIFT = 21
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, RT_SHIFT = 16
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, RD_SHIFT = 11
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, SHAMT_SHIFT = 6 /* Shift Amount */
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, FC_SHIFT = 0
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/* Bit Masks to prevent overflow into adjacent fields */
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, OPCODE_MASK = 0x3F
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, REG_MASK = 0x1F
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, SHAMT_MASK = 0x1F /* Shift Amount */
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, FC_MASK = 0x3F
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, IMM_MASK = 0xFFFF
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};
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#define enc_op(op) (((op) & OPCODE_MASK) << OPCODE_SHIFT)
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#define enc_rs(rs) (((rs) & REG_MASK) << RS_SHIFT)
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#define enc_rt(rt) (((rt) & REG_MASK) << RT_SHIFT)
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#define enc_rd(rd) (((rd) & REG_MASK) << RD_SHIFT)
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#define enc_shamt(shamt) (((shamt) & SHAMT_MASK) << SHAMT_SHIFT)
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#define enc_fc(fc) (((fc) & FC_MASK) << FC_SHIFT)
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#define enc_imm(imm) (((imm) & IMM_MASK))
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/* MIPS R-Type Instruction Format (Register-to-Register) */
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#define enc_r(op, rs, rt, rd, shamt, fc) (enc_op(op) | enc_rs(rs) | enc_rt(rt) | enc_rd(rd) | enc_shamt(shamt) | enc_fc(fc))
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/* MIPS I-Type Instruction Format (Immediate/Constant) */
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#define enc_i(op, rs, rt, imm) (enc_op(op) | enc_rs(rs) | enc_rt(rt) | enc_imm(imm))
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/* COP0 (System) Transfer Format */
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#define enc_cop0_tx(sub, rt, rd) enc_op(op_cop0) | enc_rs(sub) | enc_rt(rt) | enc_rd(rd)
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/* COP0 Return From Exception (rfe) */
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#define enc_rfe() 0x42000010
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#define load_imm(rs,rt,imm) enc_i(op_lw, rs, rt, imm)
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#define store_word(rs,rt,imm) enc_i(op_sw, rs, rt, imm)
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#define add_ui(rs,rt,imm) enc_i(op_addiu, rs, rt, imm)
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#define shift_ll(rs,rt,rd) enc_r(op_special, rs, rt, rd, 0, fc_sll)
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#define jump_reg(rs) enc_r(op_special, rs, R_0, R_0, 0, fc_jr)
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#define jump_nreg(rs,rt,rd) enc_r(op_special, rs, rt, rd, 0, fc_jalr)
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#define nop() shift_ll(rdiscard, rdiscard, rdiscard)
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// FI_ void emit_load_imm(U4 rs, U4 rt, U4 imm) { emit(load_imm()); }
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// Binary Metaprogramming
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typedef U4 const Code;
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#define CodeBlob_(sym) tmpl(codeblob,sym) [] align_(4) =
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// #define def_code_blob(func_name, func_signature, ...) \
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// internal U4 const \
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// tmpl(func_name,blob) [] align(4) \
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// = { \
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// __VA_ARGS__ \
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// }; \
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// internal func_signature func_name = (func_signature)func_name##_blob;
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enum {
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bios_flushcache = 0x44,
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bios_table_addr = 0xA0,
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};
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/* Flushes the Instruction Cache */
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I_
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Code CodeBlob_(mips_flush_icache) {
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add_ui(rstack_ptr, rstack_ptr, -8),
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store_word(rstack_ptr, rret_addr, 4),
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add_ui(rdiscard, rret_0, bios_flushcache), add_ui(rdiscard, rtmp_0, bios_table_addr),
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jump_nreg(rtmp_0, rdiscard, rret_addr),
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nop(), load_imm(rstack_ptr, rret_addr, 4), jump_reg(rret_addr),
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add_ui(rstack_ptr, rstack_ptr, 8)
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};
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FI_ void mips_flush_icache(void) { C_(VoidFn*, codeblob_mips_flush_icache)(); }
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#define clb_system "$2", "$8", "$9", "$31", "memory"
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#define asm_mips_flush_icache() asm volatile( \
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asm_inline( \
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add_ui(rstack_ptr, rstack_ptr, -8) \
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, store_word(rstack_ptr, rret_addr, 4) \
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, add_ui(rdiscard, rret_0, bios_flushcache), add_ui(rdiscard, rtmp_0, bios_table_addr) \
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, jump_nreg(rtmp_0, rdiscard, rret_addr) \
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, nop(), load_imm(rstack_ptr, rret_addr, 4), jump_reg(rret_addr) \
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, add_ui(rstack_ptr, rstack_ptr, 8) \
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) \
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asm_clobber( clb_system ) \
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)
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void test_mips_asm() {
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asm_mips_flush_icache();
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}
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// TAPE & EMITTERS
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