mirror of
https://github.com/Ed94/pikuma_ps1.git
synced 2026-06-01 18:41:13 -07:00
Compare commits
4 Commits
fe4bd6d86d
..
master
| Author | SHA1 | Date | |
|---|---|---|---|
 ed
|
27667a4232 | ||
|
ed
|
11cc936d2d | ||
|
ed
|
679c022625 | ||
|
ed
|
b81221cbf5 |
@@ -0,0 +1,262 @@
|
|||||||
|
#ifdef INTELLISENSE_DIRECTIVES
|
||||||
|
# pragma once
|
||||||
|
# include "dsl.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ============================================================================
|
||||||
|
* INLINE ASSEMBLY BLOB DISPATCHER (UP TO 99 INSTRUCTIONS)
|
||||||
|
* ============================================================================ */
|
||||||
|
|
||||||
|
/* --- 1. The Argument Counter --- */
|
||||||
|
#define _ASM_COUNT_ARGS_IMPL( \
|
||||||
|
_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \
|
||||||
|
_11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \
|
||||||
|
_21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \
|
||||||
|
_31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \
|
||||||
|
_41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \
|
||||||
|
_51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \
|
||||||
|
_61,_62,_63,_64,_65,_66,_67,_68,_69,_70, \
|
||||||
|
_71,_72,_73,_74,_75,_76,_77,_78,_79,_80, \
|
||||||
|
_81,_82,_83,_84,_85,_86,_87,_88,_89,_90, \
|
||||||
|
_91,_92,_93,_94,_95,_96,_97,_98,_99, N, ...) N
|
||||||
|
|
||||||
|
#define _ASM_COUNT_ARGS(...) m_expand(_ASM_COUNT_ARGS_IMPL(__VA_ARGS__, \
|
||||||
|
99, 98, 97, 96, 95, 94, 93, 92, 91, 90, \
|
||||||
|
89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
|
||||||
|
79, 78, 77, 76, 75, 74, 73, 72, 71, 70, \
|
||||||
|
69, 68, 67, 66, 65, 64, 63, 62, 61, 60, \
|
||||||
|
59, 58, 57, 56, 55, 54, 53, 52, 51, 50, \
|
||||||
|
49, 48, 47, 46, 45, 44, 43, 42, 41, 40, \
|
||||||
|
39, 38, 37, 36, 35, 34, 33, 32, 31, 30, \
|
||||||
|
29, 28, 27, 26, 25, 24, 23, 22, 21, 20, \
|
||||||
|
19, 18, 17, 16, 15, 14, 13, 12, 11, 10, \
|
||||||
|
9, 8, 7, 6, 5, 4, 3, 2, 1, 0))
|
||||||
|
|
||||||
|
/* --- 2. String Concatenation Helpers --- */
|
||||||
|
#define _STR1 "%c0"
|
||||||
|
#define _STR2 _STR1 ", %c1"
|
||||||
|
#define _STR3 _STR2 ", %c2"
|
||||||
|
#define _STR4 _STR3 ", %c3"
|
||||||
|
#define _STR5 _STR4 ", %c4"
|
||||||
|
#define _STR6 _STR5 ", %c5"
|
||||||
|
#define _STR7 _STR6 ", %c6"
|
||||||
|
#define _STR8 _STR7 ", %c7"
|
||||||
|
#define _STR9 _STR8 ", %c8"
|
||||||
|
#define _STR10 _STR9 ", %c9"
|
||||||
|
#define _STR11 _STR10 ", %c10"
|
||||||
|
#define _STR12 _STR11 ", %c11"
|
||||||
|
#define _STR13 _STR12 ", %c12"
|
||||||
|
#define _STR14 _STR13 ", %c13"
|
||||||
|
#define _STR15 _STR14 ", %c14"
|
||||||
|
#define _STR16 _STR15 ", %c15"
|
||||||
|
#define _STR17 _STR16 ", %c16"
|
||||||
|
#define _STR18 _STR17 ", %c17"
|
||||||
|
#define _STR19 _STR18 ", %c18"
|
||||||
|
#define _STR20 _STR19 ", %c19"
|
||||||
|
#define _STR21 _STR20 ", %c20"
|
||||||
|
#define _STR22 _STR21 ", %c21"
|
||||||
|
#define _STR23 _STR22 ", %c22"
|
||||||
|
#define _STR24 _STR23 ", %c23"
|
||||||
|
#define _STR25 _STR24 ", %c24"
|
||||||
|
#define _STR26 _STR25 ", %c25"
|
||||||
|
#define _STR27 _STR26 ", %c26"
|
||||||
|
#define _STR28 _STR27 ", %c27"
|
||||||
|
#define _STR29 _STR28 ", %c28"
|
||||||
|
#define _STR30 _STR29 ", %c29"
|
||||||
|
#define _STR31 _STR30 ", %c30"
|
||||||
|
#define _STR32 _STR31 ", %c31"
|
||||||
|
#define _STR33 _STR32 ", %c32"
|
||||||
|
#define _STR34 _STR33 ", %c33"
|
||||||
|
#define _STR35 _STR34 ", %c34"
|
||||||
|
#define _STR36 _STR35 ", %c35"
|
||||||
|
#define _STR37 _STR36 ", %c36"
|
||||||
|
#define _STR38 _STR37 ", %c37"
|
||||||
|
#define _STR39 _STR38 ", %c38"
|
||||||
|
#define _STR40 _STR39 ", %c39"
|
||||||
|
#define _STR41 _STR40 ", %c40"
|
||||||
|
#define _STR42 _STR41 ", %c41"
|
||||||
|
#define _STR43 _STR42 ", %c42"
|
||||||
|
#define _STR44 _STR43 ", %c43"
|
||||||
|
#define _STR45 _STR44 ", %c44"
|
||||||
|
#define _STR46 _STR45 ", %c45"
|
||||||
|
#define _STR47 _STR46 ", %c46"
|
||||||
|
#define _STR48 _STR47 ", %c47"
|
||||||
|
#define _STR49 _STR48 ", %c48"
|
||||||
|
#define _STR50 _STR49 ", %c49"
|
||||||
|
#define _STR51 _STR50 ", %c50"
|
||||||
|
#define _STR52 _STR51 ", %c51"
|
||||||
|
#define _STR53 _STR52 ", %c52"
|
||||||
|
#define _STR54 _STR53 ", %c53"
|
||||||
|
#define _STR55 _STR54 ", %c54"
|
||||||
|
#define _STR56 _STR55 ", %c55"
|
||||||
|
#define _STR57 _STR56 ", %c56"
|
||||||
|
#define _STR58 _STR57 ", %c57"
|
||||||
|
#define _STR59 _STR58 ", %c58"
|
||||||
|
#define _STR60 _STR59 ", %c59"
|
||||||
|
#define _STR61 _STR60 ", %c60"
|
||||||
|
#define _STR62 _STR61 ", %c61"
|
||||||
|
#define _STR63 _STR62 ", %c62"
|
||||||
|
#define _STR64 _STR63 ", %c63"
|
||||||
|
#define _STR65 _STR64 ", %c64"
|
||||||
|
#define _STR66 _STR65 ", %c65"
|
||||||
|
#define _STR67 _STR66 ", %c66"
|
||||||
|
#define _STR68 _STR67 ", %c67"
|
||||||
|
#define _STR69 _STR68 ", %c68"
|
||||||
|
#define _STR70 _STR69 ", %c69"
|
||||||
|
#define _STR71 _STR70 ", %c70"
|
||||||
|
#define _STR72 _STR71 ", %c71"
|
||||||
|
#define _STR73 _STR72 ", %c72"
|
||||||
|
#define _STR74 _STR73 ", %c73"
|
||||||
|
#define _STR75 _STR74 ", %c74"
|
||||||
|
#define _STR76 _STR75 ", %c75"
|
||||||
|
#define _STR77 _STR76 ", %c76"
|
||||||
|
#define _STR78 _STR77 ", %c77"
|
||||||
|
#define _STR79 _STR78 ", %c78"
|
||||||
|
#define _STR80 _STR79 ", %c79"
|
||||||
|
#define _STR81 _STR80 ", %c80"
|
||||||
|
#define _STR82 _STR81 ", %c81"
|
||||||
|
#define _STR83 _STR82 ", %c82"
|
||||||
|
#define _STR84 _STR83 ", %c83"
|
||||||
|
#define _STR85 _STR84 ", %c84"
|
||||||
|
#define _STR86 _STR85 ", %c85"
|
||||||
|
#define _STR87 _STR86 ", %c86"
|
||||||
|
#define _STR88 _STR87 ", %c87"
|
||||||
|
#define _STR89 _STR88 ", %c88"
|
||||||
|
#define _STR90 _STR89 ", %c89"
|
||||||
|
#define _STR91 _STR90 ", %c90"
|
||||||
|
#define _STR92 _STR91 ", %c91"
|
||||||
|
#define _STR93 _STR92 ", %c92"
|
||||||
|
#define _STR94 _STR93 ", %c93"
|
||||||
|
#define _STR95 _STR94 ", %c94"
|
||||||
|
#define _STR96 _STR95 ", %c95"
|
||||||
|
#define _STR97 _STR96 ", %c96"
|
||||||
|
#define _STR98 _STR97 ", %c97"
|
||||||
|
#define _STR99 _STR98 ", %c98"
|
||||||
|
|
||||||
|
/* Utilizing cascading operand strings to compress the payload */
|
||||||
|
#define _OP10 "i"(p0),"i"(p1),"i"(p2),"i"(p3),"i"(p4),"i"(p5),"i"(p6),"i"(p7),"i"(p8),"i"(p9)
|
||||||
|
#define _OP20 _OP10,"i"(p10),"i"(p11),"i"(p12),"i"(p13),"i"(p14),"i"(p15),"i"(p16),"i"(p17),"i"(p18),"i"(p19)
|
||||||
|
#define _OP30 _OP20,"i"(p20),"i"(p21),"i"(p22),"i"(p23),"i"(p24),"i"(p25),"i"(p26),"i"(p27),"i"(p28),"i"(p29)
|
||||||
|
#define _OP40 _OP30,"i"(p30),"i"(p31),"i"(p32),"i"(p33),"i"(p34),"i"(p35),"i"(p36),"i"(p37),"i"(p38),"i"(p39)
|
||||||
|
#define _OP50 _OP40,"i"(p40),"i"(p41),"i"(p42),"i"(p43),"i"(p44),"i"(p45),"i"(p46),"i"(p47),"i"(p48),"i"(p49)
|
||||||
|
#define _OP60 _OP50,"i"(p50),"i"(p51),"i"(p52),"i"(p53),"i"(p54),"i"(p55),"i"(p56),"i"(p57),"i"(p58),"i"(p59)
|
||||||
|
#define _OP70 _OP60,"i"(p60),"i"(p61),"i"(p62),"i"(p63),"i"(p64),"i"(p65),"i"(p66),"i"(p67),"i"(p68),"i"(p69)
|
||||||
|
#define _OP80 _OP70,"i"(p70),"i"(p71),"i"(p72),"i"(p73),"i"(p74),"i"(p75),"i"(p76),"i"(p77),"i"(p78),"i"(p79)
|
||||||
|
#define _OP90 _OP80,"i"(p80),"i"(p81),"i"(p82),"i"(p83),"i"(p84),"i"(p85),"i"(p86),"i"(p87),"i"(p88),"i"(p89)
|
||||||
|
|
||||||
|
/* --- The AST Generators (1 to 99) --- */
|
||||||
|
#define _INL_1(p0) ".word " _STR1 : : "i"(p0)
|
||||||
|
#define _INL_2(p0,p1) ".word " _STR2 : : "i"(p0),"i"(p1)
|
||||||
|
#define _INL_3(p0,p1,p2) ".word " _STR3 : : "i"(p0),"i"(p1),"i"(p2)
|
||||||
|
#define _INL_4(p0,p1,p2,p3) ".word " _STR4 : : "i"(p0),"i"(p1),"i"(p2),"i"(p3)
|
||||||
|
#define _INL_5(p0,p1,p2,p3,p4) ".word " _STR5 : : "i"(p0),"i"(p1),"i"(p2),"i"(p3),"i"(p4)
|
||||||
|
#define _INL_6(p0,p1,p2,p3,p4,p5) ".word " _STR6 : : "i"(p0),"i"(p1),"i"(p2),"i"(p3),"i"(p4),"i"(p5)
|
||||||
|
#define _INL_7(p0,p1,p2,p3,p4,p5,p6) ".word " _STR7 : : "i"(p0),"i"(p1),"i"(p2),"i"(p3),"i"(p4),"i"(p5),"i"(p6)
|
||||||
|
#define _INL_8(p0,p1,p2,p3,p4,p5,p6,p7) ".word " _STR8 : : "i"(p0),"i"(p1),"i"(p2),"i"(p3),"i"(p4),"i"(p5),"i"(p6),"i"(p7)
|
||||||
|
#define _INL_9(p0,p1,p2,p3,p4,p5,p6,p7,p8) ".word " _STR9 : : "i"(p0),"i"(p1),"i"(p2),"i"(p3),"i"(p4),"i"(p5),"i"(p6),"i"(p7),"i"(p8)
|
||||||
|
#define _INL_10(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9) ".word " _STR10 : : _OP10
|
||||||
|
|
||||||
|
#define _INL_11(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10) ".word " _STR11 : : _OP10,"i"(p10)
|
||||||
|
#define _INL_12(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11) ".word " _STR12 : : _OP10,"i"(p10),"i"(p11)
|
||||||
|
#define _INL_13(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12) ".word " _STR13 : : _OP10,"i"(p10),"i"(p11),"i"(p12)
|
||||||
|
#define _INL_14(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13) ".word " _STR14 : : _OP10,"i"(p10),"i"(p11),"i"(p12),"i"(p13)
|
||||||
|
#define _INL_15(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14) ".word " _STR15 : : _OP10,"i"(p10),"i"(p11),"i"(p12),"i"(p13),"i"(p14)
|
||||||
|
#define _INL_16(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15) ".word " _STR16 : : _OP10,"i"(p10),"i"(p11),"i"(p12),"i"(p13),"i"(p14),"i"(p15)
|
||||||
|
#define _INL_17(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16) ".word " _STR17 : : _OP10,"i"(p10),"i"(p11),"i"(p12),"i"(p13),"i"(p14),"i"(p15),"i"(p16)
|
||||||
|
#define _INL_18(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17) ".word " _STR18 : : _OP10,"i"(p10),"i"(p11),"i"(p12),"i"(p13),"i"(p14),"i"(p15),"i"(p16),"i"(p17)
|
||||||
|
#define _INL_19(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18) ".word " _STR19 : : _OP10,"i"(p10),"i"(p11),"i"(p12),"i"(p13),"i"(p14),"i"(p15),"i"(p16),"i"(p17),"i"(p18)
|
||||||
|
#define _INL_20(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19) ".word " _STR20 : : _OP20
|
||||||
|
|
||||||
|
#define _INL_21(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20) ".word " _STR21 : : _OP20,"i"(p20)
|
||||||
|
#define _INL_22(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21) ".word " _STR22 : : _OP20,"i"(p20),"i"(p21)
|
||||||
|
#define _INL_23(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22) ".word " _STR23 : : _OP20,"i"(p20),"i"(p21),"i"(p22)
|
||||||
|
#define _INL_24(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23) ".word " _STR24 : : _OP20,"i"(p20),"i"(p21),"i"(p22),"i"(p23)
|
||||||
|
#define _INL_25(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24) ".word " _STR25 : : _OP20,"i"(p20),"i"(p21),"i"(p22),"i"(p23),"i"(p24)
|
||||||
|
#define _INL_26(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25) ".word " _STR26 : : _OP20,"i"(p20),"i"(p21),"i"(p22),"i"(p23),"i"(p24),"i"(p25)
|
||||||
|
#define _INL_27(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26) ".word " _STR27 : : _OP20,"i"(p20),"i"(p21),"i"(p22),"i"(p23),"i"(p24),"i"(p25),"i"(p26)
|
||||||
|
#define _INL_28(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27) ".word " _STR28 : : _OP20,"i"(p20),"i"(p21),"i"(p22),"i"(p23),"i"(p24),"i"(p25),"i"(p26),"i"(p27)
|
||||||
|
#define _INL_29(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28) ".word " _STR29 : : _OP20,"i"(p20),"i"(p21),"i"(p22),"i"(p23),"i"(p24),"i"(p25),"i"(p26),"i"(p27),"i"(p28)
|
||||||
|
#define _INL_30(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29) ".word " _STR30 : : _OP30
|
||||||
|
|
||||||
|
#define _INL_31(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30) ".word " _STR31 : : _OP30,"i"(p30)
|
||||||
|
#define _INL_32(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31) ".word " _STR32 : : _OP30,"i"(p30),"i"(p31)
|
||||||
|
#define _INL_33(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32) ".word " _STR33 : : _OP30,"i"(p30),"i"(p31),"i"(p32)
|
||||||
|
#define _INL_34(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33) ".word " _STR34 : : _OP30,"i"(p30),"i"(p31),"i"(p32),"i"(p33)
|
||||||
|
#define _INL_35(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34) ".word " _STR35 : : _OP30,"i"(p30),"i"(p31),"i"(p32),"i"(p33),"i"(p34)
|
||||||
|
#define _INL_36(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35) ".word " _STR36 : : _OP30,"i"(p30),"i"(p31),"i"(p32),"i"(p33),"i"(p34),"i"(p35)
|
||||||
|
#define _INL_37(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36) ".word " _STR37 : : _OP30,"i"(p30),"i"(p31),"i"(p32),"i"(p33),"i"(p34),"i"(p35),"i"(p36)
|
||||||
|
#define _INL_38(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37) ".word " _STR38 : : _OP30,"i"(p30),"i"(p31),"i"(p32),"i"(p33),"i"(p34),"i"(p35),"i"(p36),"i"(p37)
|
||||||
|
#define _INL_39(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38) ".word " _STR39 : : _OP30,"i"(p30),"i"(p31),"i"(p32),"i"(p33),"i"(p34),"i"(p35),"i"(p36),"i"(p37),"i"(p38)
|
||||||
|
#define _INL_40(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39) ".word " _STR40 : : _OP40
|
||||||
|
|
||||||
|
#define _INL_41(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40) ".word " _STR41 : : _OP40,"i"(p40)
|
||||||
|
#define _INL_42(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41) ".word " _STR42 : : _OP40,"i"(p40),"i"(p41)
|
||||||
|
#define _INL_43(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42) ".word " _STR43 : : _OP40,"i"(p40),"i"(p41),"i"(p42)
|
||||||
|
#define _INL_44(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43) ".word " _STR44 : : _OP40,"i"(p40),"i"(p41),"i"(p42),"i"(p43)
|
||||||
|
#define _INL_45(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44) ".word " _STR45 : : _OP40,"i"(p40),"i"(p41),"i"(p42),"i"(p43),"i"(p44)
|
||||||
|
#define _INL_46(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45) ".word " _STR46 : : _OP40,"i"(p40),"i"(p41),"i"(p42),"i"(p43),"i"(p44),"i"(p45)
|
||||||
|
#define _INL_47(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46) ".word " _STR47 : : _OP40,"i"(p40),"i"(p41),"i"(p42),"i"(p43),"i"(p44),"i"(p45),"i"(p46)
|
||||||
|
#define _INL_48(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47) ".word " _STR48 : : _OP40,"i"(p40),"i"(p41),"i"(p42),"i"(p43),"i"(p44),"i"(p45),"i"(p46),"i"(p47)
|
||||||
|
#define _INL_49(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48) ".word " _STR49 : : _OP40,"i"(p40),"i"(p41),"i"(p42),"i"(p43),"i"(p44),"i"(p45),"i"(p46),"i"(p47),"i"(p48)
|
||||||
|
#define _INL_50(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49) ".word " _STR50 : : _OP50
|
||||||
|
|
||||||
|
#define _INL_51(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50) ".word " _STR51 : : _OP50,"i"(p50)
|
||||||
|
#define _INL_52(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51) ".word " _STR52 : : _OP50,"i"(p50),"i"(p51)
|
||||||
|
#define _INL_53(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52) ".word " _STR53 : : _OP50,"i"(p50),"i"(p51),"i"(p52)
|
||||||
|
#define _INL_54(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53) ".word " _STR54 : : _OP50,"i"(p50),"i"(p51),"i"(p52),"i"(p53)
|
||||||
|
#define _INL_55(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54) ".word " _STR55 : : _OP50,"i"(p50),"i"(p51),"i"(p52),"i"(p53),"i"(p54)
|
||||||
|
#define _INL_56(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55) ".word " _STR56 : : _OP50,"i"(p50),"i"(p51),"i"(p52),"i"(p53),"i"(p54),"i"(p55)
|
||||||
|
#define _INL_57(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56) ".word " _STR57 : : _OP50,"i"(p50),"i"(p51),"i"(p52),"i"(p53),"i"(p54),"i"(p55),"i"(p56)
|
||||||
|
#define _INL_58(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57) ".word " _STR58 : : _OP50,"i"(p50),"i"(p51),"i"(p52),"i"(p53),"i"(p54),"i"(p55),"i"(p56),"i"(p57)
|
||||||
|
#define _INL_59(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58) ".word " _STR59 : : _OP50,"i"(p50),"i"(p51),"i"(p52),"i"(p53),"i"(p54),"i"(p55),"i"(p56),"i"(p57),"i"(p58)
|
||||||
|
#define _INL_60(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59) ".word " _STR60 : : _OP60
|
||||||
|
|
||||||
|
#define _INL_61(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60) ".word " _STR61 : : _OP60,"i"(p60)
|
||||||
|
#define _INL_62(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61) ".word " _STR62 : : _OP60,"i"(p60),"i"(p61)
|
||||||
|
#define _INL_63(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62) ".word " _STR63 : : _OP60,"i"(p60),"i"(p61),"i"(p62)
|
||||||
|
#define _INL_64(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63) ".word " _STR64 : : _OP60,"i"(p60),"i"(p61),"i"(p62),"i"(p63)
|
||||||
|
#define _INL_65(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64) ".word " _STR65 : : _OP60,"i"(p60),"i"(p61),"i"(p62),"i"(p63),"i"(p64)
|
||||||
|
#define _INL_66(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65) ".word " _STR66 : : _OP60,"i"(p60),"i"(p61),"i"(p62),"i"(p63),"i"(p64),"i"(p65)
|
||||||
|
#define _INL_67(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66) ".word " _STR67 : : _OP60,"i"(p60),"i"(p61),"i"(p62),"i"(p63),"i"(p64),"i"(p65),"i"(p66)
|
||||||
|
#define _INL_68(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67) ".word " _STR68 : : _OP60,"i"(p60),"i"(p61),"i"(p62),"i"(p63),"i"(p64),"i"(p65),"i"(p66),"i"(p67)
|
||||||
|
#define _INL_69(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68) ".word " _STR69 : : _OP60,"i"(p60),"i"(p61),"i"(p62),"i"(p63),"i"(p64),"i"(p65),"i"(p66),"i"(p67),"i"(p68)
|
||||||
|
#define _INL_70(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69) ".word " _STR70 : : _OP70
|
||||||
|
|
||||||
|
#define _INL_71(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70) ".word " _STR71 : : _OP70,"i"(p70)
|
||||||
|
#define _INL_72(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71) ".word " _STR72 : : _OP70,"i"(p70),"i"(p71)
|
||||||
|
#define _INL_73(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72) ".word " _STR73 : : _OP70,"i"(p70),"i"(p71),"i"(p72)
|
||||||
|
#define _INL_74(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73) ".word " _STR74 : : _OP70,"i"(p70),"i"(p71),"i"(p72),"i"(p73)
|
||||||
|
#define _INL_75(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74) ".word " _STR75 : : _OP70,"i"(p70),"i"(p71),"i"(p72),"i"(p73),"i"(p74)
|
||||||
|
#define _INL_76(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75) ".word " _STR76 : : _OP70,"i"(p70),"i"(p71),"i"(p72),"i"(p73),"i"(p74),"i"(p75)
|
||||||
|
#define _INL_77(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76) ".word " _STR77 : : _OP70,"i"(p70),"i"(p71),"i"(p72),"i"(p73),"i"(p74),"i"(p75),"i"(p76)
|
||||||
|
#define _INL_78(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77) ".word " _STR78 : : _OP70,"i"(p70),"i"(p71),"i"(p72),"i"(p73),"i"(p74),"i"(p75),"i"(p76),"i"(p77)
|
||||||
|
#define _INL_79(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78) ".word " _STR79 : : _OP70,"i"(p70),"i"(p71),"i"(p72),"i"(p73),"i"(p74),"i"(p75),"i"(p76),"i"(p77),"i"(p78)
|
||||||
|
#define _INL_80(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79) ".word " _STR80 : : _OP80
|
||||||
|
|
||||||
|
#define _INL_81(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80) ".word " _STR81 : : _OP80,"i"(p80)
|
||||||
|
#define _INL_82(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81) ".word " _STR82 : : _OP80,"i"(p80),"i"(p81)
|
||||||
|
#define _INL_83(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82) ".word " _STR83 : : _OP80,"i"(p80),"i"(p81),"i"(p82)
|
||||||
|
#define _INL_84(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82,p83) ".word " _STR84 : : _OP80,"i"(p80),"i"(p81),"i"(p82),"i"(p83)
|
||||||
|
#define _INL_85(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82,p83,p84) ".word " _STR85 : : _OP80,"i"(p80),"i"(p81),"i"(p82),"i"(p83),"i"(p84)
|
||||||
|
#define _INL_86(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82,p83,p84,p85) ".word " _STR86 : : _OP80,"i"(p80),"i"(p81),"i"(p82),"i"(p83),"i"(p84),"i"(p85)
|
||||||
|
#define _INL_87(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82,p83,p84,p85,p86) ".word " _STR87 : : _OP80,"i"(p80),"i"(p81),"i"(p82),"i"(p83),"i"(p84),"i"(p85),"i"(p86)
|
||||||
|
#define _INL_88(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82,p83,p84,p85,p86,p87) ".word " _STR88 : : _OP80,"i"(p80),"i"(p81),"i"(p82),"i"(p83),"i"(p84),"i"(p85),"i"(p86),"i"(p87)
|
||||||
|
#define _INL_89(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82,p83,p84,p85,p86,p87,p88) ".word " _STR89 : : _OP80,"i"(p80),"i"(p81),"i"(p82),"i"(p83),"i"(p84),"i"(p85),"i"(p86),"i"(p87),"i"(p88)
|
||||||
|
#define _INL_90(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82,p83,p84,p85,p86,p87,p88,p89) ".word " _STR90 : : _OP90
|
||||||
|
|
||||||
|
#define _INL_91(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82,p83,p84,p85,p86,p87,p88,p89,p90) ".word " _STR91 : : _OP90,"i"(p90)
|
||||||
|
#define _INL_92(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82,p83,p84,p85,p86,p87,p88,p89,p90,p91) ".word " _STR92 : : _OP90,"i"(p90),"i"(p91)
|
||||||
|
#define _INL_93(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82,p83,p84,p85,p86,p87,p88,p89,p90,p91,p92) ".word " _STR93 : : _OP90,"i"(p90),"i"(p91),"i"(p92)
|
||||||
|
#define _INL_94(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82,p83,p84,p85,p86,p87,p88,p89,p90,p91,p92,p93) ".word " _STR94 : : _OP90,"i"(p90),"i"(p91),"i"(p92),"i"(p93)
|
||||||
|
#define _INL_95(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82,p83,p84,p85,p86,p87,p88,p89,p90,p91,p92,p93,p94) ".word " _STR95 : : _OP90,"i"(p90),"i"(p91),"i"(p92),"i"(p93),"i"(p94)
|
||||||
|
#define _INL_96(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82,p83,p84,p85,p86,p87,p88,p89,p90,p91,p92,p93,p94,p95) ".word " _STR96 : : _OP90,"i"(p90),"i"(p91),"i"(p92),"i"(p93),"i"(p94),"i"(p95)
|
||||||
|
#define _INL_97(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82,p83,p84,p85,p86,p87,p88,p89,p90,p91,p92,p93,p94,p95,p96) ".word " _STR97 : : _OP90,"i"(p90),"i"(p91),"i"(p92),"i"(p93),"i"(p94),"i"(p95),"i"(p96)
|
||||||
|
#define _INL_98(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82,p83,p84,p85,p86,p87,p88,p89,p90,p91,p92,p93,p94,p95,p96,p97) ".word " _STR98 : : _OP90,"i"(p90),"i"(p91),"i"(p92),"i"(p93),"i"(p94),"i"(p95),"i"(p96),"i"(p97)
|
||||||
|
#define _INL_99(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82,p83,p84,p85,p86,p87,p88,p89,p90,p91,p92,p93,p94,p95,p96,p97,p98) ".word " _STR99 : : _OP90,"i"(p90),"i"(p91),"i"(p92),"i"(p93),"i"(p94),"i"(p95),"i"(p96),"i"(p97),"i"(p98)
|
||||||
|
|
||||||
|
/* The AST Builders */
|
||||||
|
#define asm_clobber(...) : __VA_ARGS__
|
||||||
|
#define asm_inline(...) m_expand(glue(_INL_, _ASM_COUNT_ARGS(__VA_ARGS__))(__VA_ARGS__))
|
||||||
|
|
||||||
|
/* The Shell */
|
||||||
|
#define asm_blob(inlines, clobbers) asm volatile ( inlines clobbers )
|
||||||
+171
-60
@@ -8,86 +8,197 @@
|
|||||||
/* C2 data registers */
|
/* C2 data registers */
|
||||||
|
|
||||||
/* --- GTE Data Registers (Coprocessor 2) --- */
|
/* --- GTE Data Registers (Coprocessor 2) --- */
|
||||||
typedef enum {
|
enum {
|
||||||
C2_VXY0 = 0, C2_VZ0 = 1, C2_VXY1 = 2, C2_VZ1 = 3,
|
C2_VXY0 = 0, C2_VZ0 = 1, C2_VXY1 = 2, C2_VZ1 = 3,
|
||||||
C2_VXY2 = 4, C2_VZ2 = 5, C2_RGB = 6, C2_OTZ = 7,
|
C2_VXY2 = 4, C2_VZ2 = 5, C2_RGB = 6, C2_OTZ = 7,
|
||||||
C2_IR0 = 8, C2_IR1 = 9, C2_IR2 = 10, C2_IR3 = 11,
|
C2_IR0 = 8, C2_IR1 = 9, C2_IR2 = 10, C2_IR3 = 11,
|
||||||
C2_SXY0 = 12, C2_SXY1 = 13, C2_SXY2 = 14, C2_SXYP = 15,
|
C2_SXY0 = 12, C2_SXY1 = 13, C2_SXY2 = 14, C2_SXYP = 15,
|
||||||
C2_SZ0 = 16, C2_SZ1 = 17, C2_SZ2 = 18, C2_SZ3 = 19,
|
C2_SZ0 = 16, C2_SZ1 = 17, C2_SZ2 = 18, C2_SZ3 = 19,
|
||||||
C2_RGB0 = 20, C2_RGB1 = 21, C2_RGB2 = 22, C2_RES1 = 23,
|
C2_RGB0 = 20, C2_RGB1 = 21, C2_RGB2 = 22, C2_RES1 = 23,
|
||||||
C2_MAC0 = 24, C2_MAC1 = 25, C2_MAC2 = 26, C2_MAC3 = 27,
|
C2_MAC0 = 24, C2_MAC1 = 25, C2_MAC2 = 26, C2_MAC3 = 27,
|
||||||
C2_IRGB = 28, C2_ORGB = 29, C2_LZCS = 30, C2_LZCR = 31
|
C2_IRGB = 28, C2_ORGB = 29, C2_LZCS = 30, C2_LZCR = 31
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Semantic Aliases for GTE Data Registers */
|
/* Semantic Aliases for GTE Data Registers */
|
||||||
|
enum {
|
||||||
#define GTE_IN_VEC0_XY C2_VXY0 /* Input Vector 0 (X, Y) */
|
gte_in_v0_xy = C2_VXY0, /* Input Vector 0 (X, Y) */
|
||||||
#define GTE_IN_VEC0_Z C2_VZ0 /* Input Vector 0 (Z) */
|
gte_in_v0_z = C2_VZ0, /* Input Vector 0 (Z) */
|
||||||
#define GTE_IN_VEC1_XY C2_VXY1 /* Input Vector 1 (X, Y) */
|
gte_in_v1_xy = C2_VXY1, /* Input Vector 1 (X, Y) */
|
||||||
#define GTE_IN_VEC1_Z C2_VZ1 /* Input Vector 1 (Z) */
|
gte_in_v1_z = C2_VZ1, /* Input Vector 1 (Z) */
|
||||||
#define GTE_IN_VEC2_XY C2_VXY2 /* Input Vector 2 (X, Y) */
|
gte_in_v2_xy = C2_VXY2, /* Input Vector 2 (X, Y) */
|
||||||
#define GTE_IN_VEC2_Z C2_VZ2 /* Input Vector 2 (Z) */
|
gte_in_v2_z = C2_VZ2, /* Input Vector 2 (Z) */
|
||||||
#define GTE_IN_COLOR C2_RGB /* Input Color (R, G, B, Code) */
|
gte_in_rgb = C2_RGB, /* Input Color (R, G, B, Code) */
|
||||||
#define GTE_OUT_SCR_XY0 C2_SXY0 /* Output Screen Coord 0 (X, Y) */
|
gte_out_scr_xy0 = C2_SXY0, /* Output Screen Coord 0 (X, Y) */
|
||||||
#define GTE_OUT_SCR_XY1 C2_SXY1 /* Output Screen Coord 1 (X, Y) */
|
gte_out_scr_xy1 = C2_SXY1, /* Output Screen Coord 1 (X, Y) */
|
||||||
#define GTE_OUT_SCR_XY2 C2_SXY2 /* Output Screen Coord 2 (X, Y) */
|
gte_out_scr_xy2 = C2_SXY2, /* Output Screen Coord 2 (X, Y) */
|
||||||
#define GTE_OUT_DEPTH C2_OTZ /* Output Ordering Table Z (Depth) */
|
gte_out_depth = C2_OTZ, /* Output Ordering Table Z (Depth) */
|
||||||
#define GTE_MATH_ACCUM0 C2_MAC0 /* Math Accumulator 0 */
|
gte_math_accum0 = C2_MAC0, /* Math Accumulator 0 */
|
||||||
#define GTE_MATH_ACCUM1 C2_MAC1 /* Math Accumulator 1 */
|
gte_math_accum1 = C2_MAC1, /* Math Accumulator 1 */
|
||||||
#define GTE_MATH_ACCUM2 C2_MAC2 /* Math Accumulator 2 */
|
gte_math_accum2 = C2_MAC2, /* Math Accumulator 2 */
|
||||||
|
};
|
||||||
|
|
||||||
/* --- GTE Command Semantics (The Bitfield Meanings) ---
|
/* --- GTE Command Semantics (The Bitfield Meanings) ---
|
||||||
* A GTE command is a single 32-bit word sent to COP2.
|
* A GTE command is a single 32-bit word sent to COP2.
|
||||||
* It is highly configurable via bitfields.
|
* It is highly configurable via bitfields.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
enum {
|
||||||
/* Shift Fraction (Bit 19) - Determines fixed-point division */
|
/* Shift Fraction (Bit 19) - Determines fixed-point division */
|
||||||
#define GTE_SF_FRACTIONAL 0 /* Divide result by 4096 (Standard 4.12 fixed point) */
|
|
||||||
#define GTE_SF_INTEGER 1 /* No division (Raw integer math) */
|
gte_sf_fractional = 0, /* Divide result by 4096 (Standard 4.12 fixed point) */
|
||||||
|
gte_sf_integer = 1, /* No division (Raw integer math) */
|
||||||
|
|
||||||
/* Matrix Select (Bits 18-17) - Which 3x3 matrix to multiply by */
|
/* Matrix Select (Bits 18-17) - Which 3x3 matrix to multiply by */
|
||||||
#define GTE_MX_ROTATION 0 /* Rotation Matrix (RT) */
|
|
||||||
#define GTE_MX_LIGHT 1 /* Light Matrix (LL) */
|
|
||||||
#define GTE_MX_COLOR 2 /* Color Matrix (LC) */
|
|
||||||
#define GTE_MX_NONE 3 /* Reserved / Do not multiply */
|
|
||||||
|
|
||||||
/* Vector Select (Bits 16-15) - Which input vector to use */
|
gte_mx_rotation = 0, /* Rotation Matrix (RT) */
|
||||||
#define GTE_V_VEC0 0 /* Use Vector 0 (VXY0, VZ0) */
|
gte_mx_light = 1, /* Light Matrix (LL) */
|
||||||
#define GTE_V_VEC1 1 /* Use Vector 1 (VXY1, VZ1) */
|
gte_mx_color = 2, /* Color Matrix (LC) */
|
||||||
#define GTE_V_VEC2 2 /* Use Vector 2 (VXY2, VZ2) */
|
gte_mx_none = 3, /* Reserved / Do not multiply */
|
||||||
#define GTE_V_IR_REGS 3 /* Use Intermediate Registers (IR1, IR2, IR3) */
|
|
||||||
|
/* Vector select (Bits 16-15) - Which input vector to use */
|
||||||
|
|
||||||
|
gte_v_v0 = 0, /* Use Vector 0 (VXY0, VZ0) */
|
||||||
|
gte_v_v1 = 1, /* Use Vector 1 (VXY1, VZ1) */
|
||||||
|
gte_v_v2 = 2, /* Use Vector 2 (VXY2, VZ2) */
|
||||||
|
gte_v_ir_regs = 3, /* Use Intermediate Registers (IR1, IR2, IR3) */
|
||||||
|
|
||||||
/* Control Vector Select (Bits 14-13) - Which vector to ADD after multiplication */
|
/* Control Vector Select (Bits 14-13) - Which vector to ADD after multiplication */
|
||||||
#define GTE_CV_TRANSLATE 0 /* Add Translation Vector (TRX, TRY, TRZ) */
|
|
||||||
#define GTE_CV_BG_COLOR 1 /* Add Background Color (RBK, GBK, BBK) */
|
gte_cv_translate = 0, /* Add Translation Vector (TRX, TRY, TRZ) */
|
||||||
#define GTE_CV_FAR_COLOR 2 /* Add Far Color (RFC, GFC, BFC) */
|
gte_cv_bg_color = 1, /* Add Background Color (RBK, GBK, BBK) */
|
||||||
#define GTE_CV_NONE 3 /* Add Zero (No addition) */
|
gte_cv_far_color = 2, /* Add Far Color (RFC, GFC, BFC) */
|
||||||
|
gte_cv_none = 3, /* Add Zero (No addition) */
|
||||||
|
|
||||||
/* Limit/Clamp (Bit 10) - Prevents overflow artifacts */
|
/* Limit/Clamp (Bit 10) - Prevents overflow artifacts */
|
||||||
#define GTE_LM_NORMAL 0 /* Normal math (can overflow) */
|
|
||||||
#define GTE_LM_CLAMP 1 /* Clamp results to valid hardware ranges (e.g., RGB 0-255) */
|
gte_lm_normal = 0, /* Normal math (can overflow) */
|
||||||
|
gte_lm_clamp = 1, /* Clamp results to valid hardware ranges (e.g., RGB 0-255) */
|
||||||
|
|
||||||
/* Core Command IDs (Bits 5-0) */
|
/* Core Command IDs (Bits 5-0) */
|
||||||
#define GTE_CMD_RTPS 0x01 /* Rot/Trans Perspective Single (1 vertex) */
|
|
||||||
#define GTE_CMD_RTPT 0x02 /* Rot/Trans Perspective Triple (3 vertices) */
|
|
||||||
#define GTE_CMD_NCLIP 0x06 /* Normal Clipping (Backface culling) */
|
|
||||||
#define GTE_CMD_OP 0x0C /* Outer Product */
|
|
||||||
#define GTE_CMD_MVMVA 0x12 /* Matrix Vector Multiply & Add (Custom math) */
|
|
||||||
|
|
||||||
|
gte_cmd_rtps = 0x01, /* Rot/Trans Perspective Single (1 vertex) */
|
||||||
|
gte_cmd_rtpt = 0x02, /* Rot/Trans Perspective Triple (3 vertices) */
|
||||||
|
gte_cmd_nclip = 0x06, /* Normal Clipping (Backface culling) */
|
||||||
|
gte_cmd_op = 0x0C, /* Outer Product */
|
||||||
|
gte_cmd_mvmva = 0x12, /* Matrix Vector Multiply & Add (Custom math) */
|
||||||
|
|
||||||
/* COP2 (GTE) Transfer Format
|
/* --- GTE Command Bit-Field Layout ---
|
||||||
* Opcode is always MIPS_OP_COP2. The 'sub' field determines direction (MT/MF). */
|
* A GTE command word (sent to COP2 with RS=1) is laid out as:
|
||||||
#define ENC_COP2_TX(sub, rt, rd) \
|
*
|
||||||
((MIPS_OP_COP2 << MIPS_OPCODE_SHIFT) | \
|
* 31........25 24 23..19 18..17 16..15 14..13 12..11 10 9.......6 5.......0
|
||||||
(((sub) & MIPS_REG_MASK) << MIPS_RS_SHIFT) | \
|
* +------------+--+-----+------+------+------+------+---+--------+----------+
|
||||||
(((rt) & MIPS_REG_MASK) << MIPS_RT_SHIFT) | \
|
* | 0x3E (COP2)| 1| -- | sf | mx | v | cv | --| lm | -- | cmd |
|
||||||
(((rd) & MIPS_REG_MASK) << MIPS_RD_SHIFT))
|
* +------------+--+-----+------+------+------+------+---+--------+----------+
|
||||||
|
* \_____ GTE_PAYLOAD _____/ \__ GTE_CMD __/
|
||||||
|
*
|
||||||
|
* Shifts/masks below are the *bit positions* and *bit widths* of each
|
||||||
|
* configurable field, used by the ENC_GTE_CMD encoder. Mirrors the
|
||||||
|
* OPCODE_SHIFT / RS_SHIFT convention used in mips.h.
|
||||||
|
*/
|
||||||
|
|
||||||
/* GTE Command Format (The math engine trigger)
|
gte_shift_sf = 19, gte_width_sf = 1, gte_mask_sf = 0x1,
|
||||||
|
gte_shift_mx = 17, gte_width_mx = 2, gte_mask_mx = 0x3,
|
||||||
|
gte_shift_v = 15, gte_width_v = 2, gte_mask_v = 0x3,
|
||||||
|
gte_shift_cv = 13, gte_width_cv = 2, gte_mask_cv = 0x3,
|
||||||
|
gte_shift_lm = 10, gte_width_lm = 1, gte_mask_lm = 0x1,
|
||||||
|
gte_shift_cmd = 0, gte_width_cmd = 6, gte_mask_cmd = 0x3F,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* --- GTE Control Register Indices (for ctc2/cfc2) --- */
|
||||||
|
|
||||||
|
enum {
|
||||||
|
gte_cr_RT11 = 0, gte_cr_RT12 = 1, gte_cr_RT13 = 2,
|
||||||
|
gte_cr_RT21 = 3, gte_cr_RT22 = 4, gte_cr_RT23 = 5,
|
||||||
|
gte_cr_RT31 = 6, gte_cr_RT32 = 7, gte_cr_RT33 = 8,
|
||||||
|
gte_cr_TRX = 9, gte_cr_TRY = 10, gte_cr_TRZ = 11,
|
||||||
|
gte_cr_L11 = 12, gte_cr_L12 = 13, gte_cr_L13 = 14,
|
||||||
|
gte_cr_L21 = 15, gte_cr_L22 = 16, gte_cr_L23 = 17,
|
||||||
|
gte_cr_LR1 = 18, gte_cr_LR2 = 19, gte_cr_LR3 = 20,
|
||||||
|
gte_cr_RBK = 24, gte_cr_GBK = 25, gte_cr_BBK = 26,
|
||||||
|
gte_cr_RFC = 27, gte_cr_GFC = 28, gte_cr_BFC = 29,
|
||||||
|
gte_cr_OFX = 30, gte_cr_OFY = 31,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* COP2 (GTE) Transfer Format
|
||||||
|
* Opcode is always op_cop2. The 'sub' field determines direction (MT/MF). */
|
||||||
|
#define enc_cop2_tx(sub, rt, rd) enc_op(op_cop2) | enc_rs(sub) | enc_rt(rt) | enc_rd(rd)
|
||||||
|
|
||||||
|
/* GTE Command Format (The math engine trigger)
|
||||||
* Opcode is always MIPS_OP_COP2, RS is always 1 (CO).
|
* Opcode is always MIPS_OP_COP2, RS is always 1 (CO).
|
||||||
* The lower 25 bits are the GTE-specific command payload. */
|
* The lower 25 bits are the GTE-specific command payload.
|
||||||
#define GTE_CMD_BASE ((MIPS_OP_COP2 << MIPS_OPCODE_SHIFT) | (1 << 25))
|
*
|
||||||
#define ENC_GTE_CMD(sf, mx, v, cv, lm, cmd) \
|
* The granular `enc_gte_<field>(x)` macros below mirror the `enc_op`/`enc_rs`
|
||||||
(GTE_CMD_BASE | \
|
* pattern in mips.h: each one self-masks and shifts its own field, so a
|
||||||
(((sf) & 1) << 19) | (((mx) & 3) << 17) | (((v) & 3) << 15) | \
|
* caller can build up a GTE command piece by piece (handy for state-driven
|
||||||
(((cv) & 3) << 13) | (((lm) & 1) << 10) | ((cmd) & 0x3F))
|
* MVMVA emitters that vary one field at a time).
|
||||||
|
*
|
||||||
|
* `ENC_GTE_CMD` is the all-in-one convenience for emitting a full command
|
||||||
|
* word in one go. It just ORs the per-field encoders together. */
|
||||||
|
#define gte_cmd_base (enc_op(op_cop2) | (1 << 25))
|
||||||
|
|
||||||
|
/* Per-field encoders. Each one does (value & mask) << shift on its own. */
|
||||||
|
#define enc_gte_sf(sf) (((sf) & gte_mask_sf ) << gte_shift_sf )
|
||||||
|
#define enc_gte_mx(mx) (((mx) & gte_mask_mx ) << gte_shift_mx )
|
||||||
|
#define enc_gte_v(v) (((v) & gte_mask_v ) << gte_shift_v )
|
||||||
|
#define enc_gte_cv(cv) (((cv) & gte_mask_cv ) << gte_shift_cv )
|
||||||
|
#define enc_gte_lm(lm) (((lm) & gte_mask_lm ) << gte_shift_lm )
|
||||||
|
#define enc_gte_cmd(cmd) (((cmd) & gte_mask_cmd) << gte_shift_cmd)
|
||||||
|
|
||||||
|
/* Composite: all six GTE fields + the COP2/CO base. */
|
||||||
|
#define enc_gte_cmd(sf, mx, v, cv, lm, cmd) ( \
|
||||||
|
gte_cmd_base \
|
||||||
|
| enc_gte_sf(sf) \
|
||||||
|
| enc_gte_mx(mx) \
|
||||||
|
| enc_gte_v(v) \
|
||||||
|
| enc_gte_cv(cv) \
|
||||||
|
| enc_gte_lm(lm) \
|
||||||
|
| enc_gte_cmd(cmd) \
|
||||||
|
)
|
||||||
|
|
||||||
|
/* asm_gte_matrix_set_rotation(r0)
|
||||||
|
*
|
||||||
|
* Loads the 3x3 rotation matrix at `r0` into the GTE's rotation-matrix
|
||||||
|
* control registers (RT11..RT22, indices 0..4) via ctc2.
|
||||||
|
*
|
||||||
|
* Memory layout at r0: five contiguous 32-bit words (offsets 0..16),
|
||||||
|
* each holding two packed 16-bit matrix elements. The first 1.5 rows
|
||||||
|
* of a standard PSX SDK MATRIX struct (where each row is laid out as
|
||||||
|
* [RT_xx, RT_xy] | [RT_xz, pad] | ...).
|
||||||
|
*
|
||||||
|
* Generated MIPS (mirrors the source macro):
|
||||||
|
*
|
||||||
|
* lw $12, 0( %0 ) ; word 0
|
||||||
|
* lw $13, 4( %0 ) ; word 1
|
||||||
|
* ctc2 $12, $0 ; → C2_RT11
|
||||||
|
* ctc2 $13, $1 ; → C2_RT12
|
||||||
|
* lw $12, 8( %0 ) ; word 2
|
||||||
|
* lw $13, 12( %0 ) ; word 3
|
||||||
|
* lw $14, 16( %0 ) ; word 4
|
||||||
|
* ctc2 $12, $2 ; → C2_RT13
|
||||||
|
* ctc2 $13, $3 ; → C2_RT21
|
||||||
|
* ctc2 $14, $4 ; → C2_RT22
|
||||||
|
*
|
||||||
|
* WARNING: Incomplete by design. The source macro only writes RT11..RT22
|
||||||
|
* (5 of 9 rotation elements); RT23 and the entire RT3x row are left
|
||||||
|
* untouched. Real libpsn00b SetRotMatrix writes all 9. Use only when the
|
||||||
|
* GTE's remaining rotation entries are already correct, or you will
|
||||||
|
* get stale-RT2x/RT3x artifacts in RTPS/RTPT/MVMVA output.
|
||||||
|
*/
|
||||||
|
#define asm_gte_matrix_set_rotation(r0) \
|
||||||
|
asm volatile( \
|
||||||
|
asm_inline( \
|
||||||
|
load_imm(R_T4, r0, 0), \
|
||||||
|
load_imm(R_T5, r0, 4), \
|
||||||
|
enc_cop2_tx(cop_mt, R_T4, 0), \
|
||||||
|
enc_cop2_tx(cop_mt, R_T5, 1), \
|
||||||
|
load_imm(R_T4, r0, 8), \
|
||||||
|
load_imm(R_T5, r0, 12), \
|
||||||
|
load_imm(R_T6, r0, 16), \
|
||||||
|
enc_cop2_tx(cop_mt, R_T4, 2), \
|
||||||
|
enc_cop2_tx(cop_mt, R_T5, 3), \
|
||||||
|
enc_cop2_tx(cop_mt, R_T6, 4) \
|
||||||
|
) \
|
||||||
|
asm_clobber( clb_system, "$12", "$13", "$14") \
|
||||||
|
: \
|
||||||
|
: "r"(r0) \
|
||||||
|
)
|
||||||
|
|||||||
@@ -91,6 +91,7 @@ FI_ void slice_copy_(Slice dest, Slice src) {
|
|||||||
#pragma endregion Slice
|
#pragma endregion Slice
|
||||||
|
|
||||||
#pragma region FArena
|
#pragma region FArena
|
||||||
|
|
||||||
typedef Opt_(farena) { U4 alignment, type_width; };
|
typedef Opt_(farena) { U4 alignment, type_width; };
|
||||||
typedef Struct_(FArena) { U4 start, capacity, used; };
|
typedef Struct_(FArena) { U4 start, capacity, used; };
|
||||||
FI_ void farena_init(FArena_R arena, Slice mem) { assert(arena != nullptr);
|
FI_ void farena_init(FArena_R arena, Slice mem) { assert(arena != nullptr);
|
||||||
@@ -115,4 +116,5 @@ FI_ U4 farena_save(FArena arena) { return arena.used; }
|
|||||||
#define farena_push_(arena, amount, ...) farena_push((arena), (amount), opt_(farena, __VA_ARGS__))
|
#define farena_push_(arena, amount, ...) farena_push((arena), (amount), opt_(farena, __VA_ARGS__))
|
||||||
#define farena_push_type(arena, type, ...) C_(type*, farena_push((arena), 1, opt_(farena, .type_width=S_(type), __VA_ARGS__)).ptr)
|
#define farena_push_type(arena, type, ...) C_(type*, farena_push((arena), 1, opt_(farena, .type_width=S_(type), __VA_ARGS__)).ptr)
|
||||||
#define farena_push_array(arena, type, amount, ...) (tmpl(Slice,type)){ C_(type*, farena_push((arena), (amount), opt_(farena, .type_width=S_(type), __VA_ARGS__)).ptr), (amount) }
|
#define farena_push_array(arena, type, amount, ...) (tmpl(Slice,type)){ C_(type*, farena_push((arena), (amount), opt_(farena, .type_width=S_(type), __VA_ARGS__)).ptr), (amount) }
|
||||||
|
|
||||||
#pragma endregion FArena
|
#pragma endregion FArena
|
||||||
|
|||||||
+156
-148
@@ -1,154 +1,169 @@
|
|||||||
#ifdef INTELLISENSE_DIRECTIVES
|
#ifdef INTELLISENSE_DIRECTIVES
|
||||||
# pragma once
|
# pragma once
|
||||||
# include "dsl.h"
|
# include "dsl.h"
|
||||||
|
# include "gcc_asm.h"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
enum {
|
||||||
/* --- MIPS CPU Registers --- */
|
/* --- MIPS CPU Registers --- */
|
||||||
typedef enum {
|
|
||||||
R_ZERO = 0, R_AT = 1, R_V0 = 2, R_V1 = 3,
|
R_0 = 0, R_AT = 1, R_V0 = 2, R_V1 = 3,
|
||||||
R_A0 = 4, R_A1 = 5, R_A2 = 6, R_A3 = 7,
|
R_A0 = 4, R_A1 = 5, R_A2 = 6, R_A3 = 7,
|
||||||
R_T0 = 8, R_T1 = 9, R_T2 = 10, R_T3 = 11,
|
R_T0 = 8, R_T1 = 9, R_T2 = 10, R_T3 = 11,
|
||||||
R_T4 = 12, R_T5 = 13, R_T6 = 14, R_T7 = 15,
|
R_T4 = 12, R_T5 = 13, R_T6 = 14, R_T7 = 15,
|
||||||
R_S0 = 16, R_S1 = 17, R_S2 = 18, R_S3 = 19,
|
R_S0 = 16, R_S1 = 17, R_S2 = 18, R_S3 = 19,
|
||||||
R_S4 = 20, R_S5 = 21, R_S6 = 22, R_S7 = 23,
|
R_S4 = 20, R_S5 = 21, R_S6 = 22, R_S7 = 23,
|
||||||
R_T8 = 24, R_T9 = 25, R_K0 = 26, R_K1 = 27,
|
R_T8 = 24, R_T9 = 25, R_K0 = 26, R_K1 = 27,
|
||||||
R_GP = 28, R_SP = 29, R_FP = 30, R_RA = 31
|
R_GP = 28, R_SP = 29, R_FP = 30, R_RA = 31
|
||||||
};
|
|
||||||
|
|
||||||
/* Semantic Aliases for MIPS Registers (O32 ABI) */
|
/* Semantic Aliases for MIPS Registers (O32 ABI) */
|
||||||
|
|
||||||
#define REG_DISCARD R_ZERO /* Hardwired to 0 */
|
, rdiscard = R_0 /* Hardwired to 0 */
|
||||||
#define REG_RETURN_VAL R_V0 /* Function return value */
|
, rret_0 = R_V0 /* Function return value */
|
||||||
#define REG_RETURN_VAL2 R_V1 /* Second return value (e.g., 64-bit) */
|
, rret_1 = R_V1 /* Second return value (e.g., 64-bit) */
|
||||||
#define REG_ARG_0 R_A0 /* First function argument */
|
, rarg_0 = R_A0 /* First function argument */
|
||||||
#define REG_ARG_1 R_A1 /* Second function argument */
|
, rarg_1 = R_A1 /* Second function argument */
|
||||||
#define REG_ARG_2 R_A2 /* Third function argument */
|
, rarg_2 = R_A2 /* Third function argument */
|
||||||
#define REG_ARG_3 R_A3 /* Fourth function argument */
|
, rarg_3 = R_A3 /* Fourth function argument */
|
||||||
#define REG_TEMP_0 R_T0 /* Temporary (Caller saved) */
|
, rtmp_0 = R_T0 /* Temporary (Caller saved) */
|
||||||
#define REG_TEMP_1 R_T1 /* Temporary (Caller saved) */
|
, rtmp_1 = R_T1 /* Temporary (Caller saved) */
|
||||||
#define REG_TEMP_2 R_T2 /* Temporary (Caller saved) */
|
, rtmp_2 = R_T2 /* Temporary (Caller saved) */
|
||||||
#define REG_SAVED_0 R_S0 /* Saved register (Callee saved) */
|
, rsaved_0 = R_S0 /* Saved register (Callee saved) */
|
||||||
#define REG_STACK_PTR R_SP /* Stack Pointer */
|
, rstack_ptr = R_SP /* Stack Pointer */
|
||||||
#define REG_RETURN_ADDR R_RA /* Return Address (populated by JAL) */
|
, rret_addr = R_RA /* Return Address (populated by JAL) */
|
||||||
|
|
||||||
/* --- MIPS CPU Opcodes (Bits 31-26) --- */
|
/* --- MIPS CPU Opcodes (Bits 31-26) --- */
|
||||||
|
|
||||||
#define MIPS_OP_SPECIAL 0x00 /* R-Type instructions (uses FUNCT field) */
|
, op_special = 0x00 /* R-Type instructions (uses FUNCT field) */
|
||||||
#define MIPS_OP_BCOND 0x01 /* Branch on condition */
|
, op_bcond = 0x01 /* Branch on condition */
|
||||||
#define MIPS_OP_J 0x02 /* Jump */
|
, op_j = 0x02 /* Jump */
|
||||||
#define MIPS_OP_JAL 0x03 /* Jump and Link */
|
, op_jal = 0x03 /* Jump and Link */
|
||||||
#define MIPS_OP_BEQ 0x04 /* Branch on Equal */
|
, op_beq = 0x04 /* Branch on Equal */
|
||||||
#define MIPS_OP_BNE 0x05 /* Branch on Not Equal */
|
, op_bne = 0x05 /* Branch on Not Equal */
|
||||||
#define MIPS_OP_BLEZ 0x06 /* Branch on Less Than or Equal to Zero */
|
, op_blez = 0x06 /* Branch on Less Than or Equal to Zero */
|
||||||
#define MIPS_OP_BGTZ 0x07 /* Branch on Greater Than Zero */
|
, op_bgtz = 0x07 /* Branch on Greater Than Zero */
|
||||||
#define MIPS_OP_ADDI 0x08 /* Add Immediate */
|
, op_addi = 0x08 /* Add Immediate */
|
||||||
#define MIPS_OP_ADDIU 0x09 /* Add Immediate Unsigned */
|
, op_addiu = 0x09 /* Add Immediate Unsigned */
|
||||||
#define MIPS_OP_SLTI 0x0A /* Set on Less Than Immediate */
|
, op_slti = 0x0A /* Set on Less Than Immediate */
|
||||||
#define MIPS_OP_SLTIU 0x0B /* Set on Less Than Immediate Unsigned */
|
, op_sltiu = 0x0B /* Set on Less Than Immediate Unsigned */
|
||||||
#define MIPS_OP_ANDI 0x0C /* AND Immediate */
|
, op_andi = 0x0C /* AND Immediate */
|
||||||
#define MIPS_OP_ORI 0x0D /* OR Immediate */
|
, op_ori = 0x0D /* OR Immediate */
|
||||||
#define MIPS_OP_XORI 0x0E /* XOR Immediate */
|
, op_xori = 0x0E /* XOR Immediate */
|
||||||
#define MIPS_OP_LUI 0x0F /* Load Upper Immediate */
|
, op_lui = 0x0F /* Load Upper Immediate */
|
||||||
#define MIPS_OP_COP0 0x10 /* Coprocessor 0 (System) */
|
, op_cop0 = 0x10 /* Coprocessor 0 (System) */
|
||||||
#define MIPS_OP_COP2 0x12 /* Coprocessor 2 (GTE) */
|
, op_cop2 = 0x12 /* Coprocessor 2 (GTE) */
|
||||||
#define MIPS_OP_LB 0x20 /* Load Byte */
|
, op_la = 0
|
||||||
#define MIPS_OP_LH 0x21 /* Load Halfword */
|
, op_li = 0
|
||||||
#define MIPS_OP_LW 0x23 /* Load Word */
|
, op_lb = 0x20 /* Load Byte */
|
||||||
#define MIPS_OP_LBU 0x24 /* Load Byte Unsigned */
|
, op_lh = 0x21 /* Load Halfword */
|
||||||
#define MIPS_OP_LHU 0x25 /* Load Halfword Unsigned */
|
, op_lw = 0x23 /* Load Word */
|
||||||
#define MIPS_OP_SB 0x28 /* Store Byte */
|
, op_lbu = 0x24 /* Load Byte Unsigned */
|
||||||
#define MIPS_OP_SH 0x29 /* Store Halfword */
|
, op_lhu = 0x25 /* Load Halfword Unsigned */
|
||||||
#define MIPS_OP_SW 0x2B /* Store Word */
|
, op_sb = 0x28 /* Store Byte */
|
||||||
|
, op_sh = 0x29 /* Store Halfword */
|
||||||
|
, op_sw = 0x2B /* Store Word */
|
||||||
|
|
||||||
|
, op_load_addr = op_la
|
||||||
|
, op_load_imm = op_li
|
||||||
|
, op_jump = op_j
|
||||||
|
, op_jump_nlink = op_jal
|
||||||
|
|
||||||
/* --- MIPS CPU Function Codes (Bits 5-0, used when OP == MIPS_OP_SPECIAL) --- */
|
/* --- MIPS CPU Function Codes (Bits 5-0, used when OP == MIPS_OP_SPECIAL) --- */
|
||||||
|
|
||||||
#define MIPS_FC_SLL 0x00 /* Shift Word Left Logical */
|
, fc_sll = 0x00 /* Shift Word Left Logical */
|
||||||
#define MIPS_FC_SRL 0x02 /* Shift Word Right Logical */
|
, fc_srl = 0x02 /* Shift Word Right Logical */
|
||||||
#define MIPS_FC_SRA 0x03 /* Shift Word Right Arithmetic */
|
, fc_sra = 0x03 /* Shift Word Right Arithmetic */
|
||||||
#define MIPS_FC_SLLV 0x04 /* Shift Word Left Logical Variable */
|
, fc_sllv = 0x04 /* Shift Word Left Logical Variable */
|
||||||
#define MIPS_FC_SRLV 0x06 /* Shift Word Right Logical Variable */
|
, fc_srlv = 0x06 /* Shift Word Right Logical Variable */
|
||||||
#define MIPS_FC_SRAV 0x07 /* Shift Word Right Arithmetic Variable */
|
, fc_srav = 0x07 /* Shift Word Right Arithmetic Variable */
|
||||||
#define MIPS_FC_JR 0x08 /* Jump Register */
|
, fc_jr = 0x08 /* Jump Register */
|
||||||
#define MIPS_FC_JALR 0x09 /* Jump and Link Register */
|
, fc_jalr = 0x09 /* Jump and Link Register */
|
||||||
#define MIPS_FC_SYSCALL 0x0C /* System Call */
|
, fc_syscall = 0x0C /* System Call */
|
||||||
#define MIPS_FC_BREAK 0x0D /* Breakpoint */
|
, fc_break = 0x0D /* Breakpoint */
|
||||||
#define MIPS_FC_MFHI 0x10 /* Move From HI */
|
, fc_mfhi = 0x10 /* Move From HI */
|
||||||
#define MIPS_FC_MTHI 0x11 /* Move To HI */
|
, fc_mthi = 0x11 /* Move To HI */
|
||||||
#define MIPS_FC_MFLO 0x12 /* Move From LO */
|
, fc_mflo = 0x12 /* Move From LO */
|
||||||
#define MIPS_FC_MTLO 0x13 /* Move To LO */
|
, fc_mtlo = 0x13 /* Move To LO */
|
||||||
#define MIPS_FC_MULT 0x18 /* Multiply Word */
|
, fc_mult = 0x18 /* Multiply Word */
|
||||||
#define MIPS_FC_MULTU 0x19 /* Multiply Unsigned Word */
|
, fc_multu = 0x19 /* Multiply Unsigned Word */
|
||||||
#define MIPS_FC_DIV 0x1A /* Divide Word */
|
, fc_div = 0x1A /* Divide Word */
|
||||||
#define MIPS_FC_DIVU 0x1B /* Divide Unsigned Word */
|
, fc_divu = 0x1B /* Divide Unsigned Word */
|
||||||
#define MIPS_FC_ADD 0x20 /* Add Word */
|
, fc_add = 0x20 /* Add Word */
|
||||||
#define MIPS_FC_ADDU 0x21 /* Add Unsigned Word */
|
, fc_addu = 0x21 /* Add Unsigned Word */
|
||||||
#define MIPS_FC_SUB 0x22 /* Subtract Word */
|
, fc_sub = 0x22 /* Subtract Word */
|
||||||
#define MIPS_FC_SUBU 0x23 /* Subtract Unsigned Word */
|
, fc_subu = 0x23 /* Subtract Unsigned Word */
|
||||||
#define MIPS_FC_AND 0x24 /* AND */
|
, fc_and = 0x24 /* AND */
|
||||||
#define MIPS_FC_OR 0x25 /* OR */
|
, fc_or = 0x25 /* OR */
|
||||||
#define MIPS_FC_XOR 0x26 /* XOR */
|
, fc_xor = 0x26 /* XOR */
|
||||||
#define MIPS_FC_NOR 0x27 /* NOR */
|
, fc_nor = 0x27 /* NOR */
|
||||||
#define MIPS_FC_SLT 0x2A /* Set on Less Than */
|
, fc_slt = 0x2A /* Set on Less Than */
|
||||||
#define MIPS_FC_SLTU 0x2B /* Set on Less Than Unsigned */
|
, fc_sltu = 0x2B /* Set on Less Than Unsigned */
|
||||||
|
|
||||||
|
, fc_jump_reg = fc_jr
|
||||||
|
|
||||||
/* --- Coprocessor 0 (System Control & Exceptions) --- */
|
/* --- Coprocessor 0 (System Control & Exceptions) --- */
|
||||||
|
|
||||||
#define MIPS_COP_MF 0x00 /* Move From Coprocessor */
|
, cop_mf = 0x00 /* Move From Coprocessor */
|
||||||
#define MIPS_COP_MT 0x04 /* Move To Coprocessor */
|
, cop_mt = 0x04 /* Move To Coprocessor */
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
// Bitfield Packets (Encoders)
|
// Bitfield Packets (Encoders)
|
||||||
|
|
||||||
|
enum { _BitOffsets = 0
|
||||||
/* Bit Offsets for MIPS Instruction Fields */
|
/* Bit Offsets for MIPS Instruction Fields */
|
||||||
|
|
||||||
#define MIPS_OPCODE_SHIFT 26
|
, OPCODE_SHIFT = 26
|
||||||
#define MIPS_RS_SHIFT 21
|
, RS_SHIFT = 21
|
||||||
#define MIPS_RT_SHIFT 16
|
, RT_SHIFT = 16
|
||||||
#define MIPS_RD_SHIFT 11
|
, RD_SHIFT = 11
|
||||||
#define MIPS_SHAMT_SHIFT 6
|
, SHAMT_SHIFT = 6 /* Shift Amount */
|
||||||
#define MIPS_FC_SHIFT 0
|
, FC_SHIFT = 0
|
||||||
|
|
||||||
/* Bit Masks to prevent overflow into adjacent fields */
|
/* Bit Masks to prevent overflow into adjacent fields */
|
||||||
|
|
||||||
#define MIPS_OPCODE_MASK 0x3F
|
, OPCODE_MASK = 0x3F
|
||||||
#define MIPS_REG_MASK 0x1F
|
, REG_MASK = 0x1F
|
||||||
#define MIPS_SHAMT_MASK 0x1F
|
, SHAMT_MASK = 0x1F /* Shift Amount */
|
||||||
#define MIPS_FC_MASK 0x3F
|
, FC_MASK = 0x3F
|
||||||
#define MIPS_IMM_MASK 0xFFFF
|
, IMM_MASK = 0xFFFF
|
||||||
|
};
|
||||||
|
|
||||||
|
#define enc_op(op) (((op) & OPCODE_MASK) << OPCODE_SHIFT)
|
||||||
|
#define enc_rs(rs) (((rs) & REG_MASK) << RS_SHIFT)
|
||||||
|
#define enc_rt(rt) (((rt) & REG_MASK) << RT_SHIFT)
|
||||||
|
#define enc_rd(rd) (((rd) & REG_MASK) << RD_SHIFT)
|
||||||
|
#define enc_shamt(shamt) (((shamt) & SHAMT_MASK) << SHAMT_SHIFT)
|
||||||
|
#define enc_fc(fc) (((fc) & FC_MASK) << FC_SHIFT)
|
||||||
|
#define enc_imm(imm) (((imm) & IMM_MASK))
|
||||||
|
|
||||||
/* MIPS R-Type Instruction Format (Register-to-Register) */
|
/* MIPS R-Type Instruction Format (Register-to-Register) */
|
||||||
#define ENC_R(op, rs, rt, rd, shamt, funct) \
|
#define enc_r(op, rs, rt, rd, shamt, fc) (enc_op(op) | enc_rs(rs) | enc_rt(rt) | enc_rd(rd) | enc_shamt(shamt) | enc_fc(fc))
|
||||||
((((op) & MIPS_OPCODE_MASK) << MIPS_OPCODE_SHIFT) | \
|
|
||||||
(((rs) & MIPS_REG_MASK) << MIPS_RS_SHIFT) | \
|
|
||||||
(((rt) & MIPS_REG_MASK) << MIPS_RT_SHIFT) | \
|
|
||||||
(((rd) & MIPS_REG_MASK) << MIPS_RD_SHIFT) | \
|
|
||||||
(((shamt) & MIPS_SHAMT_MASK) << MIPS_SHAMT_SHIFT) | \
|
|
||||||
(((funct) & MIPS_FC_MASK) << MIPS_FC_SHIFT))
|
|
||||||
|
|
||||||
/* MIPS I-Type Instruction Format (Immediate/Constant) */
|
/* MIPS I-Type Instruction Format (Immediate/Constant) */
|
||||||
#define ENC_I(op, rs, rt, imm) \
|
#define enc_i(op, rs, rt, imm) (enc_op(op) | enc_rs(rs) | enc_rt(rt) | enc_imm(imm))
|
||||||
((((op) & MIPS_OPCODE_MASK) << MIPS_OPCODE_SHIFT) | \
|
|
||||||
(((rs) & MIPS_REG_MASK) << MIPS_RS_SHIFT) | \
|
|
||||||
(((rt) & MIPS_REG_MASK) << MIPS_RT_SHIFT) | \
|
|
||||||
(((imm) & MIPS_IMM_MASK)))
|
|
||||||
|
|
||||||
/* COP0 (System) Transfer Format */
|
/* COP0 (System) Transfer Format */
|
||||||
#define ENC_COP0_TX(sub, rt, rd) \
|
#define enc_cop0_tx(sub, rt, rd) enc_op(op_cop0) | enc_rs(sub) | enc_rt(rt) | enc_rd(rd)
|
||||||
((MIPS_OP_COP0 << MIPS_OPCODE_SHIFT) | \
|
|
||||||
(((sub) & MIPS_REG_MASK) << MIPS_RS_SHIFT) | \
|
|
||||||
(((rt) & MIPS_REG_MASK) << MIPS_RT_SHIFT) | \
|
|
||||||
(((rd) & MIPS_REG_MASK) << MIPS_RD_SHIFT))
|
|
||||||
|
|
||||||
/* COP0 Return From Exception (rfe) */
|
/* COP0 Return From Exception (rfe) */
|
||||||
#define ENC_RFE() 0x42000010
|
#define enc_rfe() 0x42000010
|
||||||
|
|
||||||
|
#define load_imm(rs,rt,imm) enc_i(op_lw, rs, rt, imm)
|
||||||
|
#define store_word(rs,rt,imm) enc_i(op_sw, rs, rt, imm)
|
||||||
|
#define add_ui(rs,rt,imm) enc_i(op_addiu, rs, rt, imm)
|
||||||
|
#define shift_ll(rs,rt,rd) enc_r(op_special, rs, rt, rd, 0, fc_sll)
|
||||||
|
|
||||||
|
#define jump_reg(rs) enc_r(op_special, rs, R_0, R_0, 0, fc_jr)
|
||||||
|
#define jump_nreg(rs,rt,rd) enc_r(op_special, rs, rt, rd, 0, fc_jalr)
|
||||||
|
|
||||||
|
#define nop() shift_ll(rdiscard, rdiscard, rdiscard)
|
||||||
|
|
||||||
|
// FI_ void emit_load_imm(U4 rs, U4 rt, U4 imm) { emit(load_imm()); }
|
||||||
|
|
||||||
// Binary Metaprogramming
|
// Binary Metaprogramming
|
||||||
|
|
||||||
typedef U4 const Code;
|
typedef U4 const Code;
|
||||||
#define def_code_blob(sym) sym ## _ ## blob [] align_(4) =
|
#define CodeBlob_(sym) tmpl(codeblob,sym) [] align_(4) =
|
||||||
|
|
||||||
// #define def_code_blob(func_name, func_signature, ...) \
|
// #define def_code_blob(func_name, func_signature, ...) \
|
||||||
// internal U4 const \
|
// internal U4 const \
|
||||||
@@ -158,46 +173,39 @@ typedef U4 const Code;
|
|||||||
// }; \
|
// }; \
|
||||||
// internal func_signature func_name = (func_signature)func_name##_blob;
|
// internal func_signature func_name = (func_signature)func_name##_blob;
|
||||||
|
|
||||||
internal
|
enum {
|
||||||
Code def_code_blob(mips_flush_icache) {
|
bios_flushcache = 0x44,
|
||||||
/* addiu , , -8 */
|
bios_table_addr = 0xA0,
|
||||||
ENC_I(MIPS_OP_ADDIU, REG_STACK_PTR, REG_STACK_PTR, -8),
|
|
||||||
/* sw , 4() */
|
|
||||||
ENC_I(MIPS_OP_SW, REG_STACK_PTR, REG_RETURN_ADDR, 4),
|
|
||||||
/* addiu , , 0x44 (BIOS Call 0x44: FlushCache) */
|
|
||||||
ENC_I(MIPS_OP_ADDIU, REG_DISCARD, REG_RETURN_VAL, 0x44),
|
|
||||||
/* addiu , , 0xA0 (BIOS A0 Table Address) */
|
|
||||||
ENC_I(MIPS_OP_ADDIU, REG_DISCARD, REG_TEMP_1, 0xA0),
|
|
||||||
/* jalr , (Jump to BIOS) */
|
|
||||||
ENC_R(MIPS_OP_SPECIAL, REG_TEMP_1, R_ZERO, REG_RETURN_ADDR, 0, MIPS_FC_JALR),
|
|
||||||
/* nop (Branch delay slot) */
|
|
||||||
ENC_R(MIPS_OP_SPECIAL, R_ZERO, R_ZERO, R_ZERO, 0, MIPS_FC_SLL),
|
|
||||||
/* lw , 4() */
|
|
||||||
ENC_I(MIPS_OP_LW, REG_STACK_PTR, REG_RETURN_ADDR, 4),
|
|
||||||
/* jr (Return to C code) */
|
|
||||||
ENC_R(MIPS_OP_SPECIAL, REG_RETURN_ADDR, R_ZERO, R_ZERO, 0, MIPS_FC_JR),
|
|
||||||
/* addiu , , 8 (Branch delay slot: restore stack pointer) */
|
|
||||||
ENC_I(MIPS_OP_ADDIU, REG_STACK_PTR, REG_STACK_PTR, 8)
|
|
||||||
};
|
};
|
||||||
FI_ void mips_flush_icache(void) { C_(VoidFn*, mips_flush_icache_blob)(); }
|
|
||||||
|
|
||||||
/* Flushes the Instruction Cache so the CPU sees our newly written tape */
|
|
||||||
// FI_ void mips_flush_icache(void) {
|
|
||||||
// /* Uses standard PS1 BIOS A0 table call 0x44 */
|
|
||||||
// __asm__ volatile (
|
|
||||||
// "li $v0, 0x44\n\t"
|
|
||||||
// "li $t1, 0xA0\n\t"
|
|
||||||
// "jalr $t1\n\t"
|
|
||||||
// "nop"
|
|
||||||
// : : : "v0", "t1", "ra", "memory"
|
|
||||||
// );
|
|
||||||
// }
|
|
||||||
|
|
||||||
|
/* Flushes the Instruction Cache */
|
||||||
|
I_
|
||||||
|
Code CodeBlob_(mips_flush_icache) {
|
||||||
|
add_ui(rstack_ptr, rstack_ptr, -8),
|
||||||
|
store_word(rstack_ptr, rret_addr, 4),
|
||||||
|
add_ui(rdiscard, rret_0, bios_flushcache), add_ui(rdiscard, rtmp_0, bios_table_addr),
|
||||||
|
jump_nreg(rtmp_0, rdiscard, rret_addr),
|
||||||
|
nop(), load_imm(rstack_ptr, rret_addr, 4), jump_reg(rret_addr),
|
||||||
|
add_ui(rstack_ptr, rstack_ptr, 8)
|
||||||
|
};
|
||||||
|
FI_ void mips_flush_icache(void) { C_(VoidFn*, codeblob_mips_flush_icache)(); }
|
||||||
|
|
||||||
|
#define clb_system "$2", "$8", "$9", "$31", "memory"
|
||||||
|
|
||||||
|
#define asm_mips_flush_icache() asm volatile( \
|
||||||
|
asm_inline( \
|
||||||
|
add_ui(rstack_ptr, rstack_ptr, -8) \
|
||||||
|
, store_word(rstack_ptr, rret_addr, 4) \
|
||||||
|
, add_ui(rdiscard, rret_0, bios_flushcache), add_ui(rdiscard, rtmp_0, bios_table_addr) \
|
||||||
|
, jump_nreg(rtmp_0, rdiscard, rret_addr) \
|
||||||
|
, nop(), load_imm(rstack_ptr, rret_addr, 4), jump_reg(rret_addr) \
|
||||||
|
, add_ui(rstack_ptr, rstack_ptr, 8) \
|
||||||
|
) \
|
||||||
|
asm_clobber( clb_system ) \
|
||||||
|
)
|
||||||
|
|
||||||
|
void test_mips_asm() {
|
||||||
|
asm_mips_flush_icache();
|
||||||
|
}
|
||||||
|
|
||||||
// TAPE & EMITTERS
|
// TAPE & EMITTERS
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
Reference in New Issue
Block a user