intiial review on: resolve_look_at__input_and_sub_proc

code/duffle/bios.h

@@ -0,0 +1,14 @@
+#ifdef INTELLISENSE_DIRECTIVES
+#	pragma once
+#endif
+enum {
+	bios_init_pad_2  = 0x12,
+	bios_start_pad_2 = 0x13,
+	bios_flushcache  = 0x44,
+	bios_table_addr  = 0xA0,
+	bios_btable_addr = 0xB0,
+};
+
+enum {
+	bios_pad_buffer_size = 0x22,
+};

code/duffle/dsl.atom.h

@@ -75,6 +75,26 @@
  * ----------------------------------------------------------------------------*/
 #define atom_reg /* atom_reg: opt the preceding enum entry into the DWARF registry */
 
+// ----------------------------------------------------------------------------
+// atom_auto_reg(atom, sym) — per-atom auto-allocated GPR binding.
+//   enum {
+//       atom_auto_reg(cube_g4_face, R_Fwdx),                // expands to: R_Fwdx = R_Fwdx_Code /* atom_auto_reg: cube_g4_face */,
+//       atom_auto_reg(cube_g4_face, R_Eye_z) atom_type(S4), // atom_type chains after
+//   };
+// (The macro IS the entire enum entry — no separate LHS=RHS. The `atom` scope is
+//  preserved in a trailing C-comment on the RHS so the Lua scanner can recover
+//  it after preprocessing strips the macro form. R_<Sym>_Code is resolved from gen/auto_reg.h which the .c file #include's before the enum declaration.)
+#define atom_auto_reg(atom, sym) sym = sym ## _Code /* atom_auto_reg: atom */
+
+// ----------------------------------------------------------------------------
+// phase_auto_reg(phase, sym) — per-phase auto-allocated GPR binding.
+//   enum {
+//       phase_auto_reg(cube_g4, R_Temp0),     // expands to: R_Temp0 = R_Temp0_Code /* phase_auto_reg: cube_g4 */,
+//       phase_auto_reg(cube_g4, R_Temp1),
+//   };
+// (Same macro-as-enum-entry form as atom_auto_reg above; the `phase` scope is preserved in a trailing C-comment on the RHS for the Lua scanner to recover.)
+#define phase_auto_reg(phase, sym) sym = sym ## _Code /* phase_auto_reg: phase */
+
 /* ============================================================================
  *   atom_info :
  *      MipsAtom_(cube_tri) atom_info(

code/duffle/dsl.h

@@ -28,8 +28,9 @@
 #define internal static // internal
 
 #define asm           __asm__
-#define align_(value) __attribute__((aligned (value)))             // for easy alignment
 
+#define A_(data)      (& data)
+#define align_(value) __attribute__((aligned (value)))             // for easy alignment
 #define align_(value) __attribute__((aligned (value)))             // for easy alignment
 #define C_(type,data) ((type)(data))                               // for enforced precedence
 #define expect_(x, y) __builtin_expect(x, y)                       // so compiler knows the common path
@@ -90,8 +91,8 @@
 #define PtrSet_(type)  TypeR_(type); typedef TypeV_(type)
 #define TSet_(type)    type; typedef PtrSet_(type)
 
-#define array_len(a)                   (U4)(sizeof(a) / sizeof(typeof((a)[0])))
-#define array_decl(type, ...)          (type[]){__VA_ARGS__}
+#define Array_len(a)                   (U4)(sizeof(a) / sizeof(typeof((a)[0])))
+#define Array_decl(type, ...)          (type[]){__VA_ARGS__}
 #define Array_sym(type,len)            A ## len ## _ ## type
 #define Array_expand(type,len)         type Array_sym(type, len)[len]; typedef PtrSet_(Array_sym(type, len))
 #define Array_(type,len)               Array_expand(type,len)
@@ -133,8 +134,8 @@ typedef __UINT32_TYPE__ TSet_(B4);
 #define u4_v(value) C_(U4 V_*, value)
 enum { false = 0, true  = 1, true_overflow, };
 
-#define u4_lo(value) ((value) & 0xFFFFU)
-#define u4_hi(value) ((value) >> 12)
+#define u4_lo(value) (u4_(value) & 0xFFFFU)
+#define u4_hi(value) (u4_(value) >> (S_(U2) * 8))
 
 typedef void Proc_(VoidFn) (void);
 
@@ -168,6 +169,8 @@ def_signed_ops(le, <=)
 #undef def_signed_ops
 #undef def_signed_op
 
+// Unused, we arent' doing any C-like asm since we have the asm dsl. We'll keep the non-generics if we somehow do.
+#if 0
 #define def_generic_sop(op, a, ...) _Generic((a), U1:  op ## _s1, U2: op ## _s2, U4: op ## _s4) (a, __VA_ARGS__)
 #define add_s(a,b) def_generic_sop(add,a,b)
 #define sub_s(a,b) def_generic_sop(sub,a,b)
@@ -177,6 +180,7 @@ def_signed_ops(le, <=)
 #define ge_s(a,b)  def_generic_sop(ge, a,b)
 #define le_s(a,b)  def_generic_sop(le, a,b)
 #undef def_generic_sop
+#endif
 
 #define alignas                             _Alignas
 #define alignof                             _Alignof

code/duffle/gen/macs.h

@@ -14,7 +14,9 @@
 //   source: C:\projects\Pikuma\ps1\code\duffle\pad.h
 //   source: C:\projects\Pikuma\ps1\code\duffle\dsl.atom.h
 //   source: C:\projects\Pikuma\ps1\code\duffle\lottes_tape.h
+//   source: C:\projects\Pikuma\ps1\code\duffle\bios.h
 //   source: C:\projects\Pikuma\ps1\code\duffle\psyq.h
+//   source: C:\projects\Pikuma\ps1\code\duffle\pad.c
 //   source: C:\projects\Pikuma\ps1\code\duffle\math.atom.c
 //   source: C:\projects\Pikuma\ps1\code\duffle\mips.atom.c
 //   source: C:\projects\Pikuma\ps1\code\duffle\gte.atom.c
@@ -58,8 +60,8 @@ WORD_COUNT(mac_yield_tail, 3)
 
 /* atom_dbg_skip */
 #define mac_load_v2s2(rs_x, rs_y, r_base, offset) \
-	load_half( rs_x, r_base, O_(V3_S2,x)) \
-,	load_half( rs_y, r_base, O_(V3_S2,y))
+	load_half( rs_x, r_base, offset + O_(V3_S2,x)) \
+,	load_half( rs_y, r_base, offset + O_(V3_S2,y))
 WORD_COUNT(mac_load_v2s2, 2)
 
 /* atom_dbg_skip */
@@ -68,6 +70,27 @@ WORD_COUNT(mac_load_v2s2, 2)
 ,	store_half(rt_y, base, offset + O_(V2_S2,y))
 WORD_COUNT(mac_store_v2s2, 2)
 
+/* atom_dbg_skip */
+#define mac_load_v3s4(rs_x, rs_y, rs_z, r_base, offset) \
+	load_word( rs_x, r_base, offset + O_(V3_S4,x)) \
+,	load_word( rs_y, r_base, offset + O_(V3_S4,y)) \
+,	load_word( rs_z, r_base, offset + O_(V3_S4,z))
+WORD_COUNT(mac_load_v3s4, 3)
+
+/* atom_dbg_skip */
+#define mac_store_v3s4(rt_x, rt_y, rt_z, base, offset) \
+	store_word(rt_x, base, offset + O_(V3_S4,x)) \
+,	store_word(rt_y, base, offset + O_(V3_S4,y)) \
+,	store_word(rt_z, base, offset + O_(V3_S4,z))
+WORD_COUNT(mac_store_v3s4, 3)
+
+/* atom_dbg_skip */
+#define mac_sub_v3s4(rds_x, rds_y, rds_z, rt_x, rt_y, rt_z) \
+	sub_s(rds_x, rds_x, rt_x) \
+,	sub_s(rds_y, rds_y, rt_y) \
+,	sub_s(rds_z, rds_z, rt_z)
+WORD_COUNT(mac_sub_v3s4, 3)
+
 /* atom_dbg_skip */
 #define mac_store_rects2(rt_x, rt_y, rt_width, rt_height, base, offset) \
 	store_half(rt_x,      base, offset + O_(Rect_S2,x)) \
@@ -124,9 +147,86 @@ WORD_COUNT(mac_gte_store_g4_p012, 3)
 	gte_sw(C2_SXY2, r_primitive_cursor, O_(Poly_G4,p3))
 WORD_COUNT(mac_gte_store_g4_p3, 1)
 
+/* atom_dbg_skip */
+#define mac_gte_sqr_v3(r_sx, r_sy, r_sz, r_sq_x, r_sq_y, r_sq_z) \
+	gte_mv_to_data_r(r_sx, C2_IR1) \
+,	gte_mv_to_data_r(r_sy, C2_IR2) \
+,	gte_mv_to_data_r(r_sz, C2_IR3) \
+,	nop \
+,	gte_cmdw_sqr \
+,	gte_mv_from_data_r(r_sq_x, C2_MAC1) \
+,	gte_mv_from_data_r(r_sq_y, C2_MAC2) \
+,	gte_mv_from_data_r(r_sq_z, C2_MAC3)
+WORD_COUNT(mac_gte_sqr_v3, 8)
+
+/* atom_dbg_skip */
+#define mac_gte_gpf_scale(r_sx, r_sy, r_sz, r_recip_est, r_shift, r_dx, r_dy, r_dz) \
+	gte_mv_to_data_r(r_recip_est, C2_IR0) \
+,	gte_mv_to_data_r(r_sx,        C2_IR1) \
+,	gte_mv_to_data_r(r_sy,        C2_IR2) \
+,	gte_mv_to_data_r(r_sz,        C2_IR3) \
+,	nop2 /* retire IR0..IR3 → GPF input pre-fill (matches libgte 0x80016134..0x80016138) */ \
+,	gte_cmdw_gpf \
+,	gte_mv_from_data_r(r_dx, C2_MAC1) \
+,	gte_mv_from_data_r(r_dy, C2_MAC2) \
+,	gte_mv_from_data_r(r_dz, C2_MAC3) \
+,	shift_aright_var(r_dx, r_dx, r_shift) \
+,	shift_aright_var(r_dy, r_dy, r_shift) \
+,	shift_aright_var(r_dz, r_dz, r_shift)
+WORD_COUNT(mac_gte_gpf_scale, 13)
+
+#define mac_apply_matrix_lv(r_mtx, r_vec, r_out, r_t0, r_t1, r_t2) \
+	load_word(r_t0, r_mtx,  0) \
+,	nop \
+,	gte_mv_to_ctrl_r(r_t0, gte_cr_RT11_Code) \
+,	load_word(r_t0, r_mtx,  4) \
+,	nop \
+,	gte_mv_to_ctrl_r(r_t0, gte_cr_RT12_Code) \
+,	load_word(r_t0, r_mtx,  8) \
+,	nop \
+,	gte_mv_to_ctrl_r(r_t0, gte_cr_RT13_Code) \
+,	load_word(r_t0, r_mtx, 12) \
+,	nop \
+,	gte_mv_to_ctrl_r(r_t0, gte_cr_RT21_Code) \
+,	load_half_u(r_t0, r_mtx, 16) \
+,	nop \
+,	gte_mv_to_ctrl_r(r_t0, gte_cr_RT22_Code) \
+,	nop2	/* Load PACKED pos into V0 (libgte SVECTOR layout).
+	 * r_vec points to atom-0-staged packed data ((pos.y << 16) | pos.x at +0, pos.z at +4).
+	 * LWC2 base register MUST be the pointer r_vec, NOT the loaded value r_t0. */ \
+,	load_word(r_t0, r_vec, 0) \
+,	nop \
+,	gte_lw(C2_VXY0, r_vec, 0) \
+,	load_word(r_t0, r_vec, 4) \
+,	nop \
+,	gte_lw(C2_VZ0, r_vec, 4)	/* RTPS: cv=3 (no translation), sf=1 (no shift, integer), v=0 (V0 input),
+	 * mx=0 (rotation matrix). MAC = RT row · V0 + 0. RTPS also writes
+	 * SXY0/1/2 + SZ0..SZ3 (perspective division); ignored. */ \
+,	gte_cmdw_rtps_sf1	/* Read MAC1/2/3 → out. */ \
+,	gte_mv_from_data_r(r_t0, C2_MAC1) \
+,	gte_mv_from_data_r(r_t1, C2_MAC2) \
+,	gte_mv_from_data_r(r_t2, C2_MAC3) \
+,	nop \
+,	store_word(r_t0, r_out, 0) \
+,	store_word(r_t1, r_out, 4) \
+,	store_word(r_t2, r_out, 8)
+WORD_COUNT(mac_apply_matrix_lv, 31)
+
+#define mac_trans_matrix(r_mtx, r_off, r_t1) \
+	load_word(r_t1, r_off, O_(V3_S4,x)) \
+,	nop \
+,	store_word(r_t1, r_mtx, O_(MT3_S2S4,t[0])) \
+,	load_word(r_t1, r_off, O_(V3_S4,y)) \
+,	nop \
+,	store_word(r_t1, r_mtx, O_(MT3_S2S4,t[1])) \
+,	load_word(r_t1, r_off, O_(V3_S4,z)) \
+,	nop \
+,	store_word(r_t1, r_mtx, O_(MT3_S2S4,t[2]))
+WORD_COUNT(mac_trans_matrix, 9)
+
 #define mac_gcmd_push(cmd, reg_transfer, reg_base, port) \
-	load_upper_i(reg_transfer, cmd >> 16) \
-,	or_i_self(   reg_transfer, cmd & 0xFFFF) \
+	load_upper_i(reg_transfer, u4_hi(cmd)) \
+,	or_i_self(   reg_transfer, u4_lo(cmd))	/* load_upper_i(reg_transfer, cmd >> 16),	// or_i_self(   reg_transfer, cmd & 0xFFFF), */ \
 ,	store_word(  reg_transfer, reg_base, port)
 WORD_COUNT(mac_gcmd_push, 3)
 

code/duffle/gen/offsets.h

@@ -11,7 +11,9 @@
 //   source: C:\projects\Pikuma\ps1\code\duffle\pad.h
 //   source: C:\projects\Pikuma\ps1\code\duffle\dsl.atom.h
 //   source: C:\projects\Pikuma\ps1\code\duffle\lottes_tape.h
+//   source: C:\projects\Pikuma\ps1\code\duffle\bios.h
 //   source: C:\projects\Pikuma\ps1\code\duffle\psyq.h
+//   source: C:\projects\Pikuma\ps1\code\duffle\pad.c
 //   source: C:\projects\Pikuma\ps1\code\duffle\math.atom.c
 //   source: C:\projects\Pikuma\ps1\code\duffle\mips.atom.c
 //   source: C:\projects\Pikuma\ps1\code\duffle\gte.atom.c
@@ -23,6 +25,16 @@
 #pragma region duffle
 
 
+// --- atom: normalize_v3s4 (66 words) ---
+
+#define _atom_offset_aligned_done_srav_path           3
+#define _atom_offset_srav_path_aligned_done           4
+
+enum {
+    atom_offset_aligned_done_srav_path = _atom_offset_aligned_done_srav_path,
+    atom_offset_srav_path_aligned_done = _atom_offset_srav_path_aligned_done,
+};
+
 // --- atom: pad_bios_snapshot (84 words) ---
 
 #define _atom_offset_snap_root_skip_disconnected      10

code/duffle/gp.atom.c

@@ -8,41 +8,37 @@ ATOM_FILE_DEBUGGER_LINE_MARKER(gp_atom_c);
 
 #pragma region MACs (Mips Atom Components)
 
-FI_ Slice_MipsCode ac_gcmd_push(U4 cmd, U4 reg_transfer, U4 reg_base, U2 port)
-MipsAtomComp_Proc_(ac_gcmd_push, {
-	load_upper_i(reg_transfer, cmd >> 16),
-	or_i_self(   reg_transfer, cmd & 0xFFFF),
+FI_ Slice_MipsCode ac_gcmd_push(AtomBuilder_R ab, U4 cmd, U4 reg_transfer, U4 reg_base, U2 port)
+MipsAtomComp_Proc_(ac_gcmd_push, ab, {
+	load_upper_i(reg_transfer, u4_hi(cmd)),
+	or_i_self(   reg_transfer, u4_lo(cmd)),
+	// load_upper_i(reg_transfer, cmd >> 16),
+	// or_i_self(   reg_transfer, cmd & 0xFFFF),
 	store_word(  reg_transfer, reg_base, port),
 })
 
-FI_ Slice_MipsCode ac_store_rgb8(U1 rr, U1 rg, U1 rb, U4 base, U4 offset) atom_dbg_skip MipsAtomComp_Proc_(ac_store_rgb8, {
+FI_ Slice_MipsCode ac_store_rgb8(AtomBuilder_R ab, U1 rr, U1 rg, U1 rb, U4 base, U4 offset) atom_dbg_skip MipsAtomComp_Proc_(ac_store_rgb8, ab, {
 	store_byte(rr, base, offset + O_(RGB8,r)),
 	store_byte(rg, base, offset + O_(RGB8,g)),
 	store_byte(rb, base, offset + O_(RGB8,b)),
 })
 
-/* Words: 3; Emits one (cmd|color) word to R_PrimCursor at the given
- * byte offset. Internal helper used by the *_format_*_color macros. */
-FI_ Slice_MipsCode ac_pack_color_word(U4 r_base, U4 off, U4 cmd, U1 r, U1 g, U1 b)
-atom_dbg_skip MipsAtomComp_Proc_(ac_pack_color_word, {
+FI_ Slice_MipsCode ac_pack_color_word(AtomBuilder_R ab, U4 r_base, U4 off, U4 cmd, U1 r, U1 g, U1 b)
+atom_dbg_skip MipsAtomComp_Proc_(ac_pack_color_word, ab, {
 	load_upper_i(R_AT, (cmd) << 8  | (b)),
 	or_i_self(   R_AT, ((g)  << 8) | (r)),
 	store_word(  R_AT, r_base, (off)),
 })
 
-/* Words: 3; Emits the F3 command+color word (cmd byte | BLUE | GREEN | RED)
- * Args: _r, _g, _b are 8-bit RGB byte values (not raw 16-bit fields). */
-FI_ Slice_MipsCode ac_format_f3_color(U4 r_base, U1 r, U1 g, U1 b)
-atom_dbg_skip MipsAtomComp_Proc_(ac_format_f3_color, { mac_pack_color_word(r_base, O_(Poly_F3,color), gp0_cmd_poly_f3, r, g, b) })
+FI_ Slice_MipsCode ac_format_f3_color(AtomBuilder_R ab, U4 r_base, U1 r, U1 g, U1 b)
+atom_dbg_skip MipsAtomComp_Proc_(ac_format_f3_color, ab, { mac_pack_color_word(r_base, O_(Poly_F3,color), gp0_cmd_poly_f3, r, g, b) })
 
-/* Words: 12; Emits the four (code|color) words of a Poly_G4.
- * Args: rN,gN,bN are 8-bit RGB byte values for each of the 4 vertices. */
-FI_ Slice_MipsCode ac_format_g4_color(U4 r_prim_cursor,
+FI_ Slice_MipsCode ac_format_g4_color(AtomBuilder_R ab, U4 r_prim_cursor,
 	U1 r0, U1 g0, U1 b0,
   U1 r1, U1 g1, U1 b1,
   U1 r2, U1 g2, U1 b2,
   U1 r3, U1 g3, U1 b3)
-MipsAtomComp_Proc_(ac_format_g4_color, {
+MipsAtomComp_Proc_(ac_format_g4_color, ab, {
 	mac_pack_color_word(r_prim_cursor, O_(Poly_G4,c0), gp0_cmd_poly_g4, r0,g0,b0),
 	mac_pack_color_word(r_prim_cursor, O_(Poly_G4,c1), 0,               r1,g1,b1),
 	mac_pack_color_word(r_prim_cursor, O_(Poly_G4,c2), 0,               r2,g2,b2),
@@ -50,7 +46,7 @@ MipsAtomComp_Proc_(ac_format_g4_color, {
 })
 
 /* Words: 11; Correctly inserts a primitive into the Ordering Table linked list. */
-I_ Slice_MipsCode ac_insert_ot_tag(U4 r_ot_base, U4 r_prim_cursor, U4 poly_size) MipsAtomComp_Proc_(ac_insert_ot_tag, {
+I_ Slice_MipsCode ac_insert_ot_tag(AtomBuilder_R ab, U4 r_ot_base, U4 r_prim_cursor, U4 poly_size) MipsAtomComp_Proc_(ac_insert_ot_tag, ab, {
 	shift_lleft( R_T1, R_T1, S_(U4)/2),                        // T1 = otz * S_(U4) (otz arg is implicit R_T1)
 	add_u_self(  R_T1, r_ot_base),                             // T1 = & OrderingTable[OTZ]
 	load_word(   R_AT, R_T1,          O_(PolyTag,code)),       // AT = old_ot_head

code/duffle/gte.atom.c

@@ -11,7 +11,7 @@ ATOM_FILE_DEBUGGER_LINE_MARKER(gte_atom_c);
 #pragma region MACs (Mips Atom Components)
 
 /* Words: 3; Loads 3 S2 indices from the face array */
-FI_ Slice_MipsCode ac_load_tri_indices(U4 r_face_cusor, U4 r_i0, U4 r_i1, U4 r_i2) atom_dbg_skip MipsAtomComp_Proc_(ac_load_tri_indices, {
+FI_ Slice_MipsCode ac_load_tri_indices(AtomBuilder_R ab, U4 r_face_cusor, U4 r_i0, U4 r_i1, U4 r_i2) atom_dbg_skip MipsAtomComp_Proc_(ac_load_tri_indices, ab, {
 	load_half_u(r_i0, r_face_cusor, 0 * S_(S2)),
 	load_half_u(r_i1, r_face_cusor, 1 * S_(S2)),
 	load_half_u(r_i2, r_face_cusor, 2 * S_(S2)),
@@ -19,14 +19,14 @@ FI_ Slice_MipsCode ac_load_tri_indices(U4 r_face_cusor, U4 r_i0, U4 r_i1, U4 r_i
 
 /* Words: 3; Stores the 3 transformed (V2_S2 screen) vertices to the F3.
  * PIPELINE: post-RTPT (SXY0=v0.screen, SXY1=v1.screen, SXY2=v2.screen). */
-FI_ Slice_MipsCode ac_gte_store_f3(U4 r_primitive_cursor) atom_dbg_skip MipsAtomComp_Proc_(ac_gte_store_f3, {
+FI_ Slice_MipsCode ac_gte_store_f3(AtomBuilder_R ab, U4 r_primitive_cursor) atom_dbg_skip MipsAtomComp_Proc_(ac_gte_store_f3, ab, {
 	gte_sw(C2_SXY0, r_primitive_cursor, O_(Poly_F3,p0)),
 	gte_sw(C2_SXY1, r_primitive_cursor, O_(Poly_F3,p1)),
 	gte_sw(C2_SXY2, r_primitive_cursor, O_(Poly_F3,p2)),
 })
 
 /* Words: 18; Translates indices to vertex addresses and pushes them to GTE  */
-I_ Slice_MipsCode ac_gte_load_tri_verts(U4 r_vert_base, U4 r_v0, U4 r_v1, U4 r_v2) atom_dbg_skip MipsAtomComp_Proc_(ac_gte_load_tri_verts, {
+I_ Slice_MipsCode ac_gte_load_tri_verts(AtomBuilder_R ab, U4 r_vert_base, U4 r_v0, U4 r_v1, U4 r_v2) atom_dbg_skip MipsAtomComp_Proc_(ac_gte_load_tri_verts, ab, {
 	shift_lleft(R_AT, r_v0, v3s2_byteoff), add_u_self(R_AT, r_vert_base), load_word(R_V0, R_AT, O_(V3_S2,x)), load_word(R_V1, R_AT, O_(V3_S2,z)), gte_mv_to_data_r(R_V0, C2_VXY0), gte_mv_to_data_r(R_V1, C2_VZ0),
 	shift_lleft(R_AT, r_v1, v3s2_byteoff), add_u_self(R_AT, r_vert_base), load_word(R_V0, R_AT, O_(V3_S2,x)), load_word(R_V1, R_AT, O_(V3_S2,z)), gte_mv_to_data_r(R_V0, C2_VXY1), gte_mv_to_data_r(R_V1, C2_VZ1),
 	shift_lleft(R_AT, r_v2, v3s2_byteoff), add_u_self(R_AT, r_vert_base), load_word(R_V0, R_AT, O_(V3_S2,x)), load_word(R_V1, R_AT, O_(V3_S2,z)), gte_mv_to_data_r(R_V0, C2_VXY2), gte_mv_to_data_r(R_V1, C2_VZ2),
@@ -37,7 +37,7 @@ I_ Slice_MipsCode ac_gte_load_tri_verts(U4 r_vert_base, U4 r_v0, U4 r_v1, U4 r_v
  * PIPELINE: post-RTPT, pre-RTPS (SXY0=v0.screen, SXY1=v1.screen, SXY2=v2.screen).
  * MUST be called BEFORE V3-RTPS, otherwise SXY0/1/2 get overwritten with v3
  * (RTPS writes only to SXY2, but to keep the three registers aligned with v0/v1/v2 you must store before RTPS). */
-FI_ Slice_MipsCode ac_gte_store_g4_p012(U4 r_primitive_cursor) atom_dbg_skip MipsAtomComp_Proc_(ac_gte_store_g4_p012, {
+FI_ Slice_MipsCode ac_gte_store_g4_p012(AtomBuilder_R ab, U4 r_primitive_cursor) atom_dbg_skip MipsAtomComp_Proc_(ac_gte_store_g4_p012, ab, {
 	gte_sw(C2_SXY0, r_primitive_cursor, O_(Poly_G4,p0)),
 	gte_sw(C2_SXY1, r_primitive_cursor, O_(Poly_G4,p1)),
 	gte_sw(C2_SXY2, r_primitive_cursor, O_(Poly_G4,p2)),
@@ -47,22 +47,330 @@ FI_ Slice_MipsCode ac_gte_store_g4_p012(U4 r_primitive_cursor) atom_dbg_skip Mip
  * PIPELINE: post-RTPS (SXY2 holds v3.screen because RTPS writes its single-vertex result to SXY2;
  * SXY0 still holds v0.screen from the earlier RTPT.
  */
-FI_ Slice_MipsCode ac_gte_store_g4_p3(U4 r_primitive_cursor) atom_dbg_skip MipsAtomComp_Proc_(ac_gte_store_g4_p3, { gte_sw(C2_SXY2, r_primitive_cursor, O_(Poly_G4,p3)) })
+FI_ Slice_MipsCode ac_gte_store_g4_p3(AtomBuilder_R ab, U4 r_primitive_cursor) atom_dbg_skip MipsAtomComp_Proc_(ac_gte_store_g4_p3, ab, { gte_sw(C2_SXY2, r_primitive_cursor, O_(Poly_G4,p3)) })
+
+/* ─── STAGE 1 of normalize: SQR + mfc2 MAC1/2/3 ───
+ * Emits squared magnitude per component (in MAC1/2/3) into caller-provided scratch regs.
+ * Stage 2 of normalize consumes these directly.
+ * Words: 8.  Clobbers: IR1/2/3, MAC1/2/3.  Uses gte_cmdw_sqr (sf=0, lm=1). */
+FI_ Slice_MipsCode ac_gte_sqr_v3(AtomBuilder_R ab, U4 r_sx, U4 r_sy, U4 r_sz, U4 r_sq_x, U4 r_sq_y, U4 r_sq_z) atom_dbg_skip MipsAtomComp_Proc_(ac_gte_sqr_v3, ab, {
+	gte_mv_to_data_r(r_sx, C2_IR1),
+	gte_mv_to_data_r(r_sy, C2_IR2),
+	gte_mv_to_data_r(r_sz, C2_IR3),
+	nop, gte_cmdw_sqr,
+	gte_mv_from_data_r(r_sq_x, C2_MAC1),
+	gte_mv_from_data_r(r_sq_y, C2_MAC2),
+	gte_mv_from_data_r(r_sq_z, C2_MAC3),
+})
+
+/* ─── STAGE 4 of normalize: mtc2 IR0..3 + GPF + mfc2 MAC + srav finalize ───
+ * Reusable standalone — given an IR0 = 1/|v| estimate (typically from a sqrtbl lookup) and a shift count 
+ * (typically (31 - LZCR)/2), multiplies IR0*IR[i] via GPF and shifts right to produce the normalized output.
+ * Used standalone for "scale vector by scalar".
+ * Words: 11.  Clobbers: IR0..3, MAC1..3.  Uses gte_cmdw_gpf (sf=0, lm=0). */
+FI_ Slice_MipsCode ac_gte_gpf_scale(AtomBuilder_R ab, U4 r_sx, U4 r_sy, U4 r_sz, U4 r_recip_est, U4 r_shift, U4 r_dx, U4 r_dy, U4 r_dz) atom_dbg_skip MipsAtomComp_Proc_(ac_gte_gpf_scale, ab, {
+	gte_mv_to_data_r(r_recip_est, C2_IR0),
+	gte_mv_to_data_r(r_sx,        C2_IR1),
+	gte_mv_to_data_r(r_sy,        C2_IR2),
+	gte_mv_to_data_r(r_sz,        C2_IR3),
+	nop2, /* retire IR0..IR3 → GPF input pre-fill (matches libgte 0x80016134..0x80016138) */
+	gte_cmdw_gpf,
+	gte_mv_from_data_r(r_dx, C2_MAC1),
+	gte_mv_from_data_r(r_dy, C2_MAC2),
+	gte_mv_from_data_r(r_dz, C2_MAC3),
+	shift_aright_var(r_dx, r_dx, r_shift),
+	shift_aright_var(r_dy, r_dy, r_shift),
+	shift_aright_var(r_dz, r_dz, r_shift),
+})
+
+/* ─── APPLY MATRIX LV (libgte ApplyMatrixLV port) ───
+ * Atom component — auto-generates mac_apply_matrix_lv Mac composer macro.
+ * Uses GTE RTPS (cv=1, sf=1, v=0) with lwc2-loaded V0/VZ0 inputs.
+ * Per PSX-SPX `geometrytransformationenginegte.md` lines 416-418:
+ *   IR1 = MAC1 = (TRX*1000h + RT11*VX0 + RT12*VY0 + RT13*VZ0) SAR (sf*12)
+ *   IR2 = MAC2 = (TRY*1000h + RT21*VX0 + RT22*VY0 + RT23*VZ0) SAR (sf*12)
+ *   IR3 = MAC3 = (TRZ*1000h + RT31*VX0 + RT32*VY0 + RT33*VZ0) SAR (sf*12)
+ * RTPS uses the FULL row of the rotation matrix (not just diagonal like MVMVA with mx=0).
+ * libgte's `gte_ApplyMatrix` calls `gte_rtv0()` = RTPS cv=1 v=0 mx=0.
+ * Per `gte.h` line 405 the body sets cv=3 (BK, zero-initialized) so no TR contribution.
+ *
+ * Operands:
+ *   r_mtx  : MT3_S2S4* (matrix pointer)
+ *   r_vec  : U4 (pointer to PACKED V0 data — (pos.y << 16) | pos.x at +0, pos.z at +4)
+ *   r_out  : V3_S4* (output pointer; MAC1/2/3 stored here)
+ *   r_t0/1/2 : 3 GPR codes for matrix load + intermediate state
+ * Words: ~26.  Clobbers: r_t0, r_t1, r_t2 (C2 $0..$4, VXY0/VZ0, MAC1/2/3, SXY0/1/2). */
+FI_ Slice_MipsCode ac_apply_matrix_lv(AtomBuilder_R ab
+	,	U4 r_mtx, U4 r_vec, U4 r_out
+	,	U4 r_t0,  U4 r_t1,  U4 r_t2
+) MipsAtomComp_Proc_(ac_apply_matrix_lv, ab, {
+	/* Load MATRIX rows into GTE RT11..RT33 (libgte convention: ctc2 to C2 $0..$4 in order).
+	 * load_half_u zero-extends the last word so RT33 = m[2][2] and TRX = 0. */
+	load_word(r_t0, r_mtx,  0), nop,
+	gte_mv_to_ctrl_r(r_t0, gte_cr_RT11_Code),
+	load_word(r_t0, r_mtx,  4), nop,
+	gte_mv_to_ctrl_r(r_t0, gte_cr_RT12_Code),
+	load_word(r_t0, r_mtx,  8), nop,
+	gte_mv_to_ctrl_r(r_t0, gte_cr_RT13_Code),
+	load_word(r_t0, r_mtx, 12), nop,
+	gte_mv_to_ctrl_r(r_t0, gte_cr_RT21_Code),
+	load_half_u(r_t0, r_mtx, 16), nop,
+	gte_mv_to_ctrl_r(r_t0, gte_cr_RT22_Code),
+	nop2,
+
+	/* Load PACKED pos into V0 (libgte SVECTOR layout).
+	 * r_vec points to atom-0-staged packed data ((pos.y << 16) | pos.x at +0, pos.z at +4).
+	 * LWC2 base register MUST be the pointer r_vec, NOT the loaded value r_t0. */
+	load_word(r_t0, r_vec, 0), nop,
+	gte_lw(C2_VXY0, r_vec, 0),
+	load_word(r_t0, r_vec, 4), nop,
+	gte_lw(C2_VZ0, r_vec, 4),
+
+	/* RTPS: cv=3 (no translation), sf=1 (no shift, integer), v=0 (V0 input),
+	 * mx=0 (rotation matrix). MAC = RT row · V0 + 0. RTPS also writes
+	 * SXY0/1/2 + SZ0..SZ3 (perspective division); ignored. */
+	gte_cmdw_rtps_sf1,
+
+	/* Read MAC1/2/3 → out. */
+	gte_mv_from_data_r(r_t0, C2_MAC1),
+	gte_mv_from_data_r(r_t1, C2_MAC2),
+	gte_mv_from_data_r(r_t2, C2_MAC3),
+	nop,
+	store_word(r_t0, r_out, 0),
+	store_word(r_t1, r_out, 4),
+	store_word(r_t2, r_out, 8),
+})
+
+/* ─── TRANS MATRIX (libgte TransMatrix port) ───
+ * Atom component — auto-generates mac_trans_matrix Mac composer macro.
+ * m->t = v (struct copy; libgte's TransMatrix at 0x8001a540 is just 3 store_words, no GTE, no add).
+ * Uses 1 GPR (r_t1 = off value) per axis; per-axis load-delay-slot pattern.
+ * Words: 9.  Clobbers: r_t1. */
+FI_ Slice_MipsCode ac_trans_matrix(AtomBuilder_R ab
+	,	U4 r_mtx, U4 r_off
+	,	U4 r_t1
+) MipsAtomComp_Proc_(ac_trans_matrix, ab, {
+	load_word(r_t1, r_off, O_(V3_S4,x)),
+	nop,
+	store_word(r_t1, r_mtx, O_(MT3_S2S4,t[0])),
+
+	load_word(r_t1, r_off, O_(V3_S4,y)),
+	nop,
+	store_word(r_t1, r_mtx, O_(MT3_S2S4,t[1])),
+
+	load_word(r_t1, r_off, O_(V3_S4,z)),
+	nop,
+	store_word(r_t1, r_mtx, O_(MT3_S2S4,t[2])),
+})
 
 #pragma endregion MACs (Mips Atom Components)
 
-#pragma region Bsked Atoms
+#pragma region Atom Procs
 
-typedef Struct_(Binds_SetGteWorld) {
-	M3_S2* transform;
+/* ─── Local copy of PSYQ's sqrtbl (1/sqrt lookup table for VectorNormal). ───
+ * Source: PSYQ 4.7 libgte sqrtbl at 0x800185B4 in hello_camera.elf.
+ *   objdump -s --start-address=0x800185B4 --stop-address=0x800185F4 hello_camera.elf
+ *   → 192 entries × 16-bit signed, in 1.12 fixed-point (max value 0x1000 = 1.0).
+ *
+ * Data is identical to the libgte original (byte-for-byte verified).
+ * 
+ * ─── Per-entry semantics (decoded from libgte msc02 VectorNormal) ───
+ * Each entry is `1/sqrt(x)` in 1.12 fixed point (value / 4096).
+ * The 192 entries span 4 octaves of the input magnitude, with 48 entries per octave:
+ *   Octave 0 (entries  0- 47): mantissa in [0x8000,  0x10000)  output ~[1.000, 0.707]
+ *   Octave 1 (entries 48- 95): mantissa in [0x10000, 0x20000)  output ~[0.707, 0.500]
+ *   Octave 2 (entries 96-143): mantissa in [0x20000, 0x40000)  output ~[0.500, 0.354]
+ *   Octave 3 (entries144-191): mantissa in [0x40000, 0x80000)  output ~[0.354, 0.251]
+ * Within each octave, 8 sub-entries interpolate over the 8 fractional bits of the mantissa
+ * (the byte `(0x80 | (i mod 8))` for the lower-byte of the aligned value).
+ * Sampling the first value of each octave:
+ *   [0]   0x1000 = 1.0000                 ; 1 / sqrt(1.0000)
+ *   [48]  0x0e4f = 0.8940                 ; 1 / sqrt(1.2500)
+ *   [96]  0x0d10 = 0.8164                 ; 1 / sqrt(1.5000)
+ *   [144] 0x0c0a = 0.7520                 ; 1 / sqrt(1.7500)
+ * And representative sub-entries within octave 0 (mantissa in [0x8000, 0x8100)):
+ *   [0]   0x1000 = 1.0000                 ; 1 / sqrt(0x8000)
+ *   [1]   0x0fe0 = 0.9922                 ; 1 / sqrt(0x8100)
+ *   [2]   0x0fc1 = 0.9846                 ; 1 / sqrt(0x8200)
+ *   [3]   0x0fa3 = 0.9773                 ; 1 / sqrt(0x8300)
+ *   [4]   0x0f85 = 0.9700                 ; 1 / sqrt(0x8400)
+ *   [5]   0x0f68 = 0.9629                 ; 1 / sqrt(0x8500)
+ *   [6]   0x0f4c = 0.9561                 ; 1 / sqrt(0x8600)
+ *   [7]   0x0f30 = 0.9492                 ; 1 / sqrt(0x8700)
+ *
+ * The algorithm's `addi -64 / sll 1 / lh` selects the entry at `(aligned - 64) * 2` for the case where `aligned` has its top bit at bit 24.
+ * After the sllv/srav pair, `aligned` always lands in `[0x80, 0x100)` 
+ * (with top bit at bit 24 → after `sub $aligned - 64`, the index sits in `[0x40, 0x80) * 2 = [0x80, 0x100)` bytes = entries [64, 128) within the sqrtbl).
+ * The earlier 64 entries (octave 0) are reached when the magnitude after shifting puts the top bit below bit 24 (the `sllv` branch),
+ * and the load upper_halves of the table bracket the input range.
+ * The later 64 entries (octaves 2-3) are the `srav` branch when the magnitude's top bit is well above bit 24.
+ *
+ * 192-entry table is reproduced verbatim from libgte (verified against libpsn00b/psxgte/vector.s:100-123 — 24 rows × 8 halfwords, last entry 0x0804). */
+internal RO_ S2  gte_normalize_sqr_tbl[192] align_(2) = {
+	0x1000, 0x0fe0, 0x0fc1, 0x0fa3, 0x0f85, 0x0f68, 0x0f4c, 0x0f30,
+	0x0f15, 0x0efb, 0x0ee1, 0x0ec7, 0x0eae, 0x0e96, 0x0e7e, 0x0e66,
+	0x0e4f, 0x0e38, 0x0e22, 0x0e0c, 0x0df7, 0x0de2, 0x0dcd, 0x0db9,
+	0x0da5, 0x0d91, 0x0d7e, 0x0d6b, 0x0d58, 0x0d45, 0x0d33, 0x0d21,
+	0x0d10, 0x0cff, 0x0cee, 0x0cdd, 0x0ccc, 0x0cbc, 0x0cac, 0x0c9c,
+	0x0c8d, 0x0c7d, 0x0c6e, 0x0c5f, 0x0c51, 0x0c42, 0x0c34, 0x0c26,
+	0x0c18, 0x0c0a, 0x0bfd, 0x0bef, 0x0be2, 0x0bd5, 0x0bc8, 0x0bbb,
+	0x0baf, 0x0ba2, 0x0b96, 0x0b8a, 0x0b7e, 0x0b72, 0x0b67, 0x0b5b,
+	0x0b50, 0x0b45, 0x0b39, 0x0b2e, 0x0b24, 0x0b19, 0x0b0e, 0x0b04,
+	0x0af9, 0x0aef, 0x0ae5, 0x0adb, 0x0ad1, 0x0ac7, 0x0abd, 0x0ab4,
+	0x0aaa, 0x0aa1, 0x0a97, 0x0a8e, 0x0a85, 0x0a7c, 0x0a73, 0x0a6a,
+	0x0a61, 0x0a59, 0x0a50, 0x0a47, 0x0a3f, 0x0a37, 0x0a2e, 0x0a26,
+	0x0a1e, 0x0a16, 0x0a0e, 0x0a06, 0x09fe, 0x09f6, 0x09ef, 0x09e7,
+	0x09e0, 0x09d8, 0x09d1, 0x09c9, 0x09c2, 0x09bb, 0x09b4, 0x09ad,
+	0x09a5, 0x099e, 0x0998, 0x0991, 0x098a, 0x0983, 0x097c, 0x0976,
+	0x096f, 0x0969, 0x0962, 0x095c, 0x0955, 0x094f, 0x0949, 0x0943,
+	0x093c, 0x0936, 0x0930, 0x092a, 0x0924, 0x091e, 0x0918, 0x0912,
+	0x090d, 0x0907, 0x0901, 0x08fb, 0x08f6, 0x08f0, 0x08eb, 0x08e5,
+	0x08e0, 0x08da, 0x08d5, 0x08cf, 0x08ca, 0x08c5, 0x08bf, 0x08ba,
+	0x08b5, 0x08b0, 0x08ab, 0x08a6, 0x08a1, 0x089c, 0x0897, 0x0892,
+	0x088d, 0x0888, 0x0883, 0x087e, 0x087a, 0x0875, 0x0870, 0x086b,
+	0x0867, 0x0862, 0x085e, 0x0859, 0x0855, 0x0850, 0x084c, 0x0847,
+	0x0843, 0x083e, 0x083a, 0x0836, 0x0831, 0x082d, 0x0829, 0x0824,
+	0x0820, 0x081c, 0x0818, 0x0814, 0x0810, 0x080c, 0x0808, 0x0804,
 };
-internal MipsAtom_(set_gte_world) atom_info(
-		atom_bind(Binds_SetGteWorld)
+
+/* ─── Full normalize (all 4 stages inline) ───
+ * Generic 4-stage GTE normalize (SQR → sum+LZCR → align+sqrtbl → GPF+srav).
+ *
+ * Parameterized by caller-provided scratch base + src/dst offsets.
+ * The caller passes r_src_offset and r_dst_offset as compile-time constants
+ * (typically derived from O_ macros in the caller's struct schema, e.g., `O_(CallerBundleScratch, fwd)`).
+ *
+ * This design lets any caller (with a scratch base + struct schema) use `normalize_v3s4_proc` 
+ * without putting magic offsets in the C-side bundle helper — the offsets come from O_ macros at the call site.
+ *
+ * Body uses 9 GPRs (r_src_ptr..r_branch_tmp):
+ *   r_src_ptr, r_dst_ptr : src/dst pointers (computed from r_scratch + caller offsets)
+ *   r_tmp                : src.x PRESERVED across stages 1-2 (NOT clobbered by mfc2 MAC2) → fed to IR1 in stage 4
+ *   r_mac1_scratch       : MAC1 result scratch (also holds aligned |v|² in stage 3)
+ *   r_mac2_scratch       : MAC2 result scratch → result.x after stage 4 sra
+ *   r_recip_est          : src.y PRESERVED across stages 1-2 → fed to IR2 in stage 4 → result.y
+ *   r_lzcr               : |v|² sum (stage 2) → shift count (stage 3) → 1/|v| (stage 4 IR0)
+ *   r_shift              : shift count SAVED in stage 3 → consumed by stage 4 srav
+ *   r_branch_tmp         : src.z PRESERVED across stages 1-2 → fed to IR3 in stage 4 → result.z (also sqrtbl base addr)
+ *
+ * Atom_labels are srav_path / aligned_done 
+ * (NOT namespaced — they're internal to this proc; 
+ * the metaprogram's per-atom-name enum emission handles any collision across different atoms/files that share the same labels).
+ *
+ * Pool cost: 11 GPRs (well within the 9-10 caller-trash GPR budget when r_scratch is a wave-context carrier).
+ *
+ * Direct port of PSYQ libgte msc02.rel.text VectorNormal disassembly (0x800160a0..0x8001615c).
+ * Words: ~59 (matches libgte 0x800160a0..0x8001615c at +/- 0-2 words for BD-slot reshuffling).
+ * Sqrtbl: hardcoded to 0x800185B4 (libgte msc02.rel.data). Note: swapped to local.
+ * Pipeline: clobbers IR0..3, MAC1..3, LZCS, LZCR.
+ */
+/* MipsAtom_Proc_ wrapper: declares the static MipsCode[] body, then calls atombuilder_unroll(ab, ...) to copy the encoded instructions into the caller's MipsAtomBuilder arena.  */
+internal MipsAtom* normalize_v3s4_proc(AtomArena_R aa,	U4 r_scratch /* GPR code: scratch base carrier (e.g., R_T4 = R_ResolveScratch) */
+	,	U4 r_src_offset, U4 r_dst_offset     /* GPR codes: PARAMETERIZED offsets (caller passes O_ macros) */
+	,	U4 r_src_ptr, U4 r_dst_ptr, U4 r_tmp /* GPR codes: 3 scratch regs (src/dst computed + tmp) */
+	,	U4 r_mac1_scratch, U4 r_mac2_scratch /* GPR codes: 2 more: MAC1/MAC2 scratch */
+	,	U4 r_recip_est                       /* GPR code: |v|² sum + shift-input + sqrtbl[index] */
+	,	U4 r_lzcr, U4 r_shift                /* GPR codes: lzcr + final srav amount */
+	,	U4 r_branch_tmp                      /* GPR code: scratch (shift count, branch target, lookup addr) */
+)
+MipsAtom_Proc_(normalize_v3s4, aa, {
+	add_si(r_src_ptr, r_scratch, r_src_offset),     /* r_src_ptr = &src */
+	add_si(r_dst_ptr, r_scratch, r_dst_offset),     /* r_dst_ptr = &dst */
+	nop,
+
+	/* Load src.x/y/z from r_src_ptr (caller-determined address) into r_tmp/r_recip_est/r_branch_tmp.
+	 * r_tmp holds src.x throughout stages 1-2 — r_mac2_scratch is clobbered to MAC2 in stage 1.5 (line below). */
+	load_word(r_tmp,          r_src_ptr, O_(V3_S4,x)),
+	load_word(r_recip_est,    r_src_ptr, O_(V3_S4,y)),
+	load_word(r_branch_tmp,   r_src_ptr, O_(V3_S4,z)),
+	nop, /* load-delay */
+
+	/* Stage 1: mtc2 src → IR1/2/3, SQR fires. */
+	gte_mv_to_data_r(r_tmp,        C2_IR1),
+	gte_mv_to_data_r(r_recip_est,  C2_IR2),
+	gte_mv_to_data_r(r_branch_tmp, C2_IR3),
+	nop, gte_cmdw_sqr,
+
+	/* Stage 2: mfc2 MAC1/2/3, sum, mtc2 LZCS. */
+	gte_mv_from_data_r(r_mac1_scratch, C2_MAC1),
+	gte_mv_from_data_r(r_mac2_scratch, C2_MAC2),
+	gte_mv_from_data_r(r_lzcr,         C2_MAC3),
+	nop,
+	add_u(r_lzcr, r_lzcr, r_mac2_scratch),
+	add_u(r_lzcr, r_lzcr, r_mac1_scratch),
+	gte_mv_to_data_r(r_lzcr, C2_LZCS),
+	nop2,
+	gte_mv_from_data_r(r_shift, C2_LZCR),
+	nop,
+
+	/* Stage 3: compute srav amount (r_lzcr) + align |v|² to bit 24.
+	 * IMPORTANT: the sllv/srav below writes the aligned |v|² to r_mac1_scratch (NOT r_lzcr),
+	 * so r_lzcr retains the shift count all the way to the start of stage 4.
+	 */
+	and_i(   r_shift, r_shift, -2),
+	or_u(r_mac1_scratch, r_lzcr, 0),                            /* FIX B: save sum before clobbering r_lzcr with shift count */
+	li_s(    r_lzcr,           31),
+	sub_s(   r_lzcr, r_lzcr, r_shift),
+	shift_aright(r_lzcr, r_lzcr, 1),
+	/* r_branch_tmp = LZCR - 24 (overwrites r_branch_tmp; src.z no longer needed after SQR) */
+	add_si(  r_branch_tmp, r_shift, -24),
+	branch_lt_zero(r_branch_tmp, atom_offset(aligned_done, srav_path)), nop,    /* FIX A: bltz → srav_path (LZCR<24 path) */
+	jump_rel(atom_offset(srav_path, aligned_done)),                              /* FIX A: b → aligned_done (LZCR>=24 path) */
+	shift_lleft_var(r_mac1_scratch, r_mac1_scratch, r_branch_tmp),              /* FIX B: src=sum (r_mac1_scratch), dst=same */
+	atom_label(srav_path)
+	li_s(    r_branch_tmp, 24),
+	sub_s(   r_branch_tmp, r_branch_tmp, r_shift),
+	shift_aright_var(r_mac1_scratch, r_mac1_scratch, r_branch_tmp),             /* FIX B: src=sum (r_mac1_scratch), dst=same */
+	atom_label(aligned_done)
+	/* Save the shift count to r_shift before the next 5 instructions overwrite r_lzcr
+	 * (the sqrtbl lookup loads 1/|v| into r_lzcr, which becomes IR0 in stage 4). */
+	or_u(r_shift, r_lzcr, 0),                                    /* r_shift ← shift count (preserved through stage 4) */
+	/* r_mac1_scratch holds |v|² aligned (top bit at bit 7). */
+	add_si(     r_mac1_scratch, r_mac1_scratch, -64),
+	shift_lleft(r_mac1_scratch, r_mac1_scratch, 1),
+	load_upper_i(r_branch_tmp, u4_hi(& gte_normalize_sqr_tbl)),
+	or_i_self(   r_branch_tmp, u4_lo(& gte_normalize_sqr_tbl)),
+	add_u(r_branch_tmp, r_branch_tmp, r_mac1_scratch),
+	load_half(r_lzcr,   r_branch_tmp, 0), nop,                  /* r_lzcr = sqrtbl[aligned-64] = 1/|v| (IR0 in stage 4) */
+
+	/* FIX bug C: r_branch_tmp held the sqrtbl base+index, NOT src.z. Reload src.z from scratch now that r_branch_tmp is free. */
+	load_word(r_branch_tmp, r_src_ptr, O_(V3_S4,z)), nop,        /* r_branch_tmp = src.z (for IR3 in stage 4) */
+
+	/* Stage 4: GPF + srav finalize (r_shift = shift count, r_lzcr = 1/|v|). */
+	gte_mv_to_data_r(r_lzcr,         C2_IR0),
+	gte_mv_to_data_r(r_tmp,          C2_IR1),                    /* IR1 = src.x (preserved in r_tmp — r_mac2_scratch was clobbered to MAC2 in stage 1.5) */
+	gte_mv_to_data_r(r_recip_est,    C2_IR2),
+	gte_mv_to_data_r(r_branch_tmp,   C2_IR3),                    /* IR3 = src.z (reloaded) */
+	nop2, gte_cmdw_gpf,
+	gte_mv_from_data_r(r_mac2_scratch, C2_MAC1),
+	gte_mv_from_data_r(r_recip_est,    C2_MAC2),
+	gte_mv_from_data_r(r_branch_tmp,   C2_MAC3),
+	shift_aright_var(r_mac2_scratch, r_mac2_scratch, r_shift),   /* sra by r_shift = (31-LZCR)/2 (saved before sqrtbl lookup) */
+	shift_aright_var(r_recip_est,    r_recip_est,    r_shift),
+	shift_aright_var(r_branch_tmp,   r_branch_tmp,   r_shift),
+
+	/* Store result.x/y/z to r_dst_ptr (caller-determined dst address). */
+	store_word(r_mac2_scratch, r_dst_ptr, O_(V3_S4,x)),
+	store_word(r_recip_est,    r_dst_ptr, O_(V3_S4,y)),
+	store_word(r_branch_tmp,   r_dst_ptr, O_(V3_S4,z)),
+
+	mac_yield()
+})
+
+#pragma endregion Atom Procs
+
+#pragma region Baked Atoms
+
+typedef Struct_(Binds_SetGteMT3S2S4) {
+	MT3_S2S4* transform;
+};
+internal MipsAtom_(set_gte_mt3s2s4) atom_info(
+		atom_bind(Binds_SetGteMT3S2S4)
 	,	atom_reads(R_TapePtr)
 ){
 	/* Pop matrix address from tape into R_T3 ($11) */
-	load_word(R_T3, R_TapePtr, O_(Binds_SetGteWorld,transform)),
-	add_ui_self(    R_TapePtr, S_(Binds_SetGteWorld)),
+	load_word(R_T3, R_TapePtr, O_(Binds_SetGteMT3S2S4,transform)),
+	add_ui_self(    R_TapePtr, S_(Binds_SetGteMT3S2S4)),
 	/* Load 3x3 Rotation + 3x1 Translation from R_T3 into GTE CONTROL Regs (ctc2) */
 	load_word(R_T0, R_T3, 0),  load_word(R_T1, R_T3,  4),
 	gte_mv_to_ctrl_r(R_T0, gte_cr_RT11), gte_mv_to_ctrl_r(R_T1, gte_cr_RT12),

code/duffle/gte.h

@@ -161,6 +161,8 @@ enum {
 	gte_cmd_nclip     = 0x06, /* Normal Clipping (Backface culling) */
 	gte_cmd_op        = 0x0C, /* Outer Product */
 	gte_cmd_mvmva     = 0x12, /* Matrix Vector Multiply & Add (Custom math) */
+	gte_cmd_sqr       = 0x28, /* Square vector — MAC[i] = IR[i]²; IR[i] ← MAC[i] saturated */
+	gte_cmd_gpf       = 0x3D, /* General-purpose Interpolation — MAC[i] = IR0 * IR[i]  */
 
 /* --- GTE Command Bit-Field Layout ---
  * A GTE command word (sent to COP2 with RS=1) is laid out as:
@@ -171,19 +173,48 @@ enum {
  *   +------------+--+-----+------+------+------+------+---+--------+----------+
  *                                    \_____ GTE_PAYLOAD _____/       \__ GTE_CMD __/
  *
- * Shifts/masks below are the *bit positions* and *bit widths* of each
- * configurable field, used by the ENC_GTE_CMD encoder. 
+ * Shifts/masks below are the *bit positions* and *bit widths* of each configurable field, used by the ENC_GTE_CMD encoder. 
  * Mirrors the OPCODE_SHIFT / RS_SHIFT convention used in mips.h.
  */
 
 	gte_shift_sf  = 19,  gte_width_sf  = 1,  gte_mask_sf  = 0x1,
 	gte_shift_mx  = 17,  gte_width_mx  = 2,  gte_mask_mx  = 0x3,
 	gte_shift_v   = 15,  gte_width_v   = 2,  gte_mask_v   = 0x3,
-	gte_shift_cv  = 13,  gte_width_cv  = 2,  gte_mask_cv  = 0x3,
+	gte_shift_cv  = 13,  gte_width_cv  = 2,  gte_mask_cv = 0x3,
 	gte_shift_lm  = 10,  gte_width_lm  = 1,  gte_mask_lm  = 0x1,
 	gte_shift_cmd =  0,  gte_width_cmd = 6,  gte_mask_cmd = 0x3F,
+
+	/* Fake command number (bits 24-20) — IGNORED by the GTE hardware per PSX-SPX `geometrytransformationenginegte.md` line 48.
+	 * libgte's compiler emits non-zero values in this field as a disassembly signature. */
+	gte_shift_fake_cmd = 20,
+	gte_width_fake_cmd = 5,
+	gte_mask_fake_cmd  = 0x1F,
 };
 
+/* --- GTE Control Register Aliases (Pitfall 1) ---
+ * Three pairs of aliases map to the SAME C2 control-register slot on real silicon:
+ *   C2[24] = gte_cr_RBK (background R)         | gte_cr_OFX (screen offset X)
+ *   C2[25] = gte_cr_GBK (background G)         | gte_cr_OFY (screen offset Y)
+ *   C2[26] = gte_cr_BBK (background B)         | gte_cr_H   (projection plane distance H)
+ * Cross-alias writes inside one atom body, or across the wave-context boundary,
+ * silently clobber each other. The metaprogram's check_gte_cr_alias_writes
+ * (CHECK_RULES row) warns about each pair per source. See
+ * docs/gte_reference.md §"Control-register alias table" for the silicon
+ * rationale and the libgte outer-product convention.
+ */
+
+/* --- RT-matrix packed-slot convention (Pitfall 4) ---
+ * The silicon packs two 16-bit RT elements per 32-bit C2 slot:
+ *   C2[2] = (RT22 << 16) | RT13       (gte_cr_RT13 writes the low  half, gte_cr_RT22 writes the high half)
+ *   C2[4] = (RT33 << 16) | RT22       (gte_cr_RT22 writes the low  half — clobbers prior RT22 value if RT13 was also written)
+ * OP and MVMVA read D1/D2/D3 from these packed slots. The libgte outer-product
+ * convention (see ac_apply_matrix_lv at gte.atom.c:108-122) writes C2[2] then
+ * C2[4] in sequence; the SECOND write's low half is RT22, not RT13. An agent
+ * who writes gte_cr_RT13 then gte_cr_RT22 to the SAME source GPR clobbers the
+ * RT13 value. See docs/gte_reference.md §"RT-matrix packed-slot convention"
+ * for the canonical write pattern.
+ */
+
 /* --- GTE Control Register Indices (for ctc2/cfc2) ---
  * Preprocessor-visible integer ids for the COP2 control register file.
  * Each enum value is bound to a parallel `_Code` `#define` so the preprocessor can stringify the integer (for `reg_str`/`rgcc` paths).
@@ -243,10 +274,10 @@ enum { _C2_OPS_ = 0
  *   bit 1 (0x02): register class — 0 = data,  1 = control
  *   bit 2 (0x04): direction      — 0 = read,  1 = write
  *
- * The values 0x00 (sub_mfc2) and 0x04 (sub_mtc2) are the same 5-bit numbers as the general MIPS `cop_mf` / `cop_mt` defined in mips.h
+ * The values 0x00 (sub_mfc2) and 0x04 (sub_mtc2) are the same 5-bit numbers as general MIPS `cop_mf` / `cop_mt` defined in mips.h
  * (which target the data register file on any coprocessor).
  * They are re-aliased here so the four-way table reads like the spec mnemonics (MFC2 / CFC2 / MTC2 / CTC2)
- * and so the encoding lives next to its only consumer (this header).
+ * and so the encoding is next to its only consumer (this header).
  *
  * Vendor mnemonic aliases (gte_mfc2 / gte_mtc2 / gte_cfc2 / gte_ctc2) live in gte_vendor_sym.h. */
 enum { _C2_TX_SUBS_ = 0
@@ -309,23 +340,24 @@ enum { _C2_TX_SUBS_ = 0
 
 /* GTE Command Format
  * Opcode is always MIPS_OP_COP2, RS is always 1 (CO).
- * The lower 25 bits are the GTE-specific command payload.
+ * Lower 25 bits are GTE-specific command payload.
  *
- * The granular `enc_gte_<field>(x)` macros below mirror the `enc_op`/`enc_rs` pattern in mips.h:
+ * The `enc_gte_<field>(x)` macros below mirror the `enc_op`/`enc_rs` pattern in mips.h:
  * Each one self-masks and shifts its own field, so a caller can build up a GTE command piece by piece
  * (handy for state-driven MVMVA emitters that vary one field at a time).
  *
- * `ENC_GTE_CMD` is the all-in-one convenience for emitting a full command word in one go.
+ * `ENC_GTE_CMD` is an all-in-one convenience for emitting a full command word.
  * It just ORs the per-field encoders together. */
 #define gte_cmd_base (enc_op(op_cop2) | (1 << 25))
 
 /* Per-field encoders. Each one does (value & mask) << shift on its own. */
-#define enc_gte_sf(sf)   (((sf)  & gte_mask_sf ) << gte_shift_sf )
-#define enc_gte_mx(mx)   (((mx)  & gte_mask_mx ) << gte_shift_mx )
-#define enc_gte_v(v)     (((v)   & gte_mask_v  ) << gte_shift_v  )
-#define enc_gte_cv(cv)   (((cv)  & gte_mask_cv ) << gte_shift_cv )
-#define enc_gte_lm(lm)   (((lm)  & gte_mask_lm ) << gte_shift_lm )
-#define enc_gte_cmd(cmd) (((cmd) & gte_mask_cmd) << gte_shift_cmd)
+#define enc_gte_sf(sf)          (((sf)  & gte_mask_sf      ) << gte_shift_sf )
+#define enc_gte_mx(mx)          (((mx)  & gte_mask_mx      ) << gte_shift_mx )
+#define enc_gte_v(v)            (((v)   & gte_mask_v       ) << gte_shift_v  )
+#define enc_gte_cv(cv)          (((cv)  & gte_mask_cv      ) << gte_shift_cv )
+#define enc_gte_lm(lm)          (((lm)  & gte_mask_lm      ) << gte_shift_lm )
+#define enc_gte_cmd(cmd)        (((cmd) & gte_mask_cmd     ) << gte_shift_cmd )
+#define enc_gte_fake_cmd(x)     (((x)   & gte_mask_fake_cmd) << gte_shift_fake_cmd)
 
 /* Composite: all six GTE fields + the COP2/CO base. */
 #define enc_gte_cmdw(sf, mx, v, cv, lm, cmd) ( \
@@ -363,11 +395,11 @@ enum { _C2_TX_SUBS_ = 0
  *  (the perspective divide happens regardless of `sf`).
  *
  *  If we emit a strictly-spec-compliant word (`sf=0`, reserved bits clear),
- *  PCSX-Redux's GTE checks those bits more strictly than the silicon does and RTPT silently no-ops — 
- *  the floor's screen coordinates come out as raw projection-of-rotation (Z never divided),
+ *  PCSX-Redux's GTE checks those bits more strictly than the silicon does and RTPT silently no-ops.
+ *  The floor's screen coordinates come out as raw projection-of-rotation (Z never divided), 
  *  `nclip` ends up wrong, and the triangle is culled.
  *
- *  So for RTPS and RTPT we OR-in the `0x28` "PsyQ compat" pattern to match the working bit pattern everyone has shipped for 25 years.
+ *  So for RTPS and RTPT we OR-in the `0x28` "PsyQ compat" pattern to match the working bit pattern.
  *  NCLIP / OP / MVMVA stay spec-clean — their reserved bits really are zero in the original PsyQ source.
  * --------------------------------------------------------------------------
  */
@@ -378,11 +410,95 @@ enum { _C2_TX_SUBS_ = 0
 #define gte_cmdw_nclip  (gte_cmd_base | enc_gte_cmd(gte_cmd_nclip))
 #define gte_cmdw_op     (gte_cmd_base | enc_gte_cmd(gte_cmd_op   ))
 #define gte_cmdw_outer_product gte_cmdw_op      /* "outer product" -- NOCASH/Sdk terminology */
-#define gte_cmdw_wedge        gte_cmdw_op      /* "wedge product"  -- geometric-algebra terminology */
+#define gte_cmdw_wedge         gte_cmdw_op      /* "wedge product"  -- geometric-algebra terminology.
+	* RGA(Lengyel): the GTE OP is a 3D signed-16-bit D x IR cross, not a generic RGA exterior product.
+	* The wedge alias is the 3D complement interpretation of the same 3 scalars (MAC1..MAC3). */
 #define gte_cmdw_mvmva  (gte_cmd_base | enc_gte_cmd(gte_cmd_mvmva))
 
+/* MVMVA with sf=0 (no shift, full-integer), cv=3 (no translation), v=3 (IR vector input).
+ * Reads input from IR1/2/3 (loaded via mtc2 rt, C2_IRx). MAC1/2/3 = RT row · IR (full product, no >>12).
+ * Per PSX-SPX: SAR (sf*12) with sf=0 = SAR 0 = no shift. */
+#define gte_cmdw_mvmva_sf0_ir  (gte_cmd_base | enc_gte_cv(3) | enc_gte_v(3) | enc_gte_cmd(gte_cmd_mvmva))
+
+/* MVMVA with sf=1 (>>12 shift, 4.12 fixed-point), cv=3 (no translation), v=3 (IR): for ApplyMatrixLV.
+ * Reads input from IR1/2/3 (loaded via mtc2 rt, C2_IRx). MAC1/2/3 = (RT row · IR) >> 12.
+ * Per PSX-SPX: SAR (sf*12) with sf=1 = SAR 12 = arithmetic right-shift by 12.
+ * This matches the libgte C-side ApplyMatrixLV output (R*pos >> 12). */
+#define gte_cmdw_mvmva_ir    (gte_cmd_base | enc_gte_sf(1) | enc_gte_cv(3) | enc_gte_v(3) | enc_gte_cmd(gte_cmd_mvmva))
+
+/* MVMVA: sf=0, mx=3 (Light matrix), v=3 (IR), cv=3 (no TR).
+ * For pass1 of the C11 two-pass decomposition. Reads L matrix.
+ * Since L matrix is typically zero, pass1 contributes 0 to the combine. */
+#define gte_cmdw_mvmva_sf0_mx3_v3_cv3  (gte_cmd_base | enc_gte_sf(0) | enc_gte_cv(3) | enc_gte_v(3) | enc_gte_mx(3) | enc_gte_cmd(gte_cmd_mvmva))
+
+/* MVMVA: sf=1 (>>12), mx=3 (Light matrix), v=2 (V0), cv=0 (with TR).
+ * Matches the C11 ApplyMatrixLV pass 2 command word (0x49E012) exactly.
+ * The combine is (pass1 << 3) + pass2. */
+#define gte_cmdw_mvmva_pass2_c11  (gte_cmd_base | enc_gte_sf(1) | enc_gte_v(2) | enc_gte_mx(3) | enc_gte_cmd(gte_cmd_mvmva))
+
+/* MVMVA: sf=0, mx=3, v=2, cv=0. Matches the C11 pass 1 command. */
+#define gte_cmdw_mvmva_pass1_c11  (gte_cmd_base | enc_gte_v(2) | enc_gte_mx(3) | enc_gte_cmd(gte_cmd_mvmva))
+#define gte_cmdw_mvmva_no_tr gte_cmdw_mvmva_ir
+
+/* MVMVA pass 2 — EXACT C11 ApplyMatrixLV command.
+ * Command word: 0x4A49E012.
+ * bits 31-26: 010010 = COP2
+ * bit 25: 1 (CO set)
+ * bits 24-20: 01001 = 9 (fake_cmd)
+ * bit 19: 1 (sf=1)
+ * bits 18-17: 00 (mx=0, RT matrix)
+ * bits 16-15: 11 (v=3, IR)
+ * bits 14-13: 11 (cv=3, no translation)
+ * bits 5-0: 010010 = MVMVA
+ * sf=1, mx=0, v=3, cv=3. Pass 2 reads RT matrix, IR input, >>12. */
+#define gte_cmdw_mvmva_c11_pass2_exact  0x4A49E012
+
+/* MVMVA pass 1 — C11's exact command: 0x4A41E012.
+ * bit 25: 1, sf=0, mx=0, v=3, cv=3. Pass 1 reads RT matrix, IR input, no shift. */
+#define gte_cmdw_mvmva_c11_pass1_exact  0x4A41E012
+
+/* MVMVA: sf=1 (>>12), mx=0 (RT matrix), v=0 (V0), cv=3 (no TR). */
+#define gte_cmdw_mvmva_sf1_mx0_v0_cv3  (gte_cmd_base | enc_gte_sf(1) | enc_gte_cv(3) | enc_gte_v(0) | enc_gte_mx(0) | enc_gte_cmd(gte_cmd_mvmva))
+
+/* RTPS with sf=1 (12-bit shift, no translation): matches the output of libgte's
+ * ApplyMatrixLV when the GTE pipeline expects R*pos >> 12. The shift produces
+ * values like (-270, 710, 1713) which match the C11 reference path. */
+#define gte_cmdw_rtps_sf1   (gte_cmd_base | enc_gte_sf(1) | enc_gte_cv(3) | enc_gte_cmd(gte_cmd_rtps))
+
+/* SQR / GPF cosmetic-bits compat helpers.
+ * Each command's `_compat` macro ORs in the `fake_cmd` field value libgte happens to emit.
+ * The hardware ignores these bits (per PSX-SPX line 48). */
+#define gte_cmdw_sqr_fake_sig  enc_gte_fake_cmd(0x0A)
+#define gte_cmdw_gpf_fake_sig  enc_gte_fake_cmd(0x19)
+
+/* SQR — Square Vector.
+ * PSX-SPX `geometrytransformationenginegte.md` §"SQR":
+ *   [MAC1,MAC2,MAC3] = [IR1*IR1, IR2*IR2, IR3*IR3] SHR (sf*12)
+ *   [IR1,IR2,IR3]    = [MAC1,MAC2,MAC3] (saturated to 0x7FFF when lm=1)
+ * Sourced verbatim from libgte msc02 VectorNormal disassembly at 0x800160b0:
+ *   0x4AA00428 = gte_cmd_base | gte_cmdw_sqr_compat | enc_gte_lm(1) | enc_gte_cmd(0x28)
+ *   bit 19     sf=0
+ *   bit 10     lm=1
+ *   bits 5-0   cmd=0x28=SQR
+ *   bits 24-20 = 0x0A (libgte "nonsense SDK command number" signature) */
+#define gte_cmdw_sqr   (gte_cmd_base | enc_gte_cmd(gte_cmd_sqr) | enc_gte_lm(1) | gte_cmdw_sqr_fake_sig)
+
+/* GPF — General-purpose Interpolation.
+ * PSX-SPX `geometrytransformationenginegte.md` §"GPF":
+ *   [MAC1,MAC2,MAC3] = (([IR1,IR2,IR3] * IR0) + [MAC1,MAC2,MAC3]) SAR (sf*12)
+ *   [IR1,IR2,IR3]    = [MAC1,MAC2,MAC3]
+ * Sourced verbatim from libgte msc02 VectorNormal disassembly at 0x8001613c:
+ *   0x4B90003D = gte_cmd_base | gte_cmdw_gpf_compat | enc_gte_cmd(0x3D)
+ *   bit 19     sf=0
+ *   bit 10     lm=0
+ *   bits 5-0   cmd=0x3D=GPF
+ *   bits 24-20 = 0x19 (libgte "nonsense SDK command number" signature) */
+#define gte_cmdw_gpf   (gte_cmd_base | enc_gte_cmd(gte_cmd_gpf) | gte_cmdw_gpf_fake_sig)
+
 #define gte_cmdw_rotate_translate_perspective_single gte_cmdw_rtps
 #define gte_cmdw_rotate_translate_perspective_triple gte_cmdw_rtpt
+/* RGA(Lengyel): RTPS/RTPT consume the matrix expansion of a rigid transformation (rotation matrix + translation vector) loaded into the RT/TR control registers.
+ * For unitized points the same result equals the motor antiproduct; the GTE executes the LA form, not a symbolic antiproduct. */
 
 /* PsyQ compatibility bits for AVSZ3 (Bits 20, 22, 24 must be set) */
 #define gte_cmdw_psyq_avsz3_compat (0x15 << 20)
@@ -433,7 +549,6 @@ enum {
 #define gte_lw_v2_z(base)   enc_gte_lw(gte_in_v2_z,  (base), GTE_Z_Offset)
 
 /* gte_load_vN(r_ptr, base) — placeholder-punned lwc2 loaders
- *
  * Emits `.word` constants encoding `lwc2 $N, off(<base>)` for the chosen GTE vector register, where `<base>` is the GPR number you pass in
  * (typically one of R_T4..R_T9 for the standard "3-pointer" pattern).
  *

code/duffle/lottes_tape.h

@@ -23,13 +23,13 @@
  * directly executed chain of assemby arrays (Atoms) that terminate with a yield sequence to the next atom.
  * These eventually lead to a terminal atom for the tape which is defined below as "tape_exit".
  * 
- * This behaves as one of the simplest runtime harnesses ontop of a host-enviornment's execution engine 
+ * It behaves as one of the simplest runtime harnesses ontop of a host-enviornment's execution engine 
  * to author and compose programs with. From here various conventions can be further applied. 
  * To make things easier  to understand it may be better to focus on what this ABI does not have. 
  * It does not have have any branching within the tape but relative branches within atoms or between atoms.
- * Branching nearly is always downstream. Stack usage is non-existent.
+ * Branching nearly is always downstream. Automatic stack usage is non-existent.
  * Push/Pop, FIFO, or Arena/Bump data structures are used by atoms explicitly.
- * In it's current form with the C11 macro dsl, the user also has fullfill manual register allocation per atom.
+ * In it's current form with the C11 macro DSL, the user also has fullfill manual register allocation per atom.
  * 
  * One of the remarkable things about utilizing this ABI is its essentially interopable with CPUs, GPUs, FPGA, 
  * or, basically anything from the 5th generation consoles and onward.
@@ -39,10 +39,10 @@
  * but, we can set the foundation for legoing whats required for eventually expanding this ABI's paradigm 
  * and core atoms to take those newer hardware features into account. For example, you can easily expand 
  * this to support wave-based execution model on a PS2 or PS3. Not having a stack or 
- * automatic register allocation means the user cannott ignore excessive argument shuffle across workload or
+ * automatic register allocation means the user cannot ignore excessive argument shuffle across workload or
  * waves and thier phases. Crossing ABI boundaries to other runtimes that do has obviouss penalties.
  * 
- * Learning data-oreinted code becomes a natural progression. Your not fighting a stack-based procedural 
+ * Learning data-oriented code becomes a natural progression. Your not fighting a stack-based procedural 
  * paradigm that wants to argument shuffle. There is no ambiguity due to the lack of constraints, for example,
  * on how the user may "call" a procedure in traditional random dispatch runtimes. The user does have to
  * hammer down "rules" or patterns for massaging the compiler to dissolve those call frames; just to get 
@@ -100,31 +100,48 @@ enum {
 	// S 0-7
 };
 
+typedef U2 Reg; // Register parameter used with atom or atom component procedures
+
 typedef U4 const MipsCode; // Underlying type to mips asm words.
 typedef Slice_(MipsCode);
 
-typedef U4 const MipsAtom; // Underlying type to an array of mips asm words that must terminate with an ac_yield.
+typedef U4 const MipsAtom; 
+typedef Slice_(MipsAtom); 
+// Sometimes a user will define a bundle of atoms that represent a procedure of work as:
+//   MipsAtom* <identifier>[...];
+// Unfortuantely if using slice_from_array it will make the slice's pointer: MipsAtom** so this enforce its defined as MipsAtom*
+// TODO(Ed): Alternatively we can make the MipsAtom an opaque pointer to the atom... so that the blow returns 'MipsAtom'.
+#define atombundle_from_array(array) (Slice_MipsAtom){.ptr=array[0],.len=Array_len(array)}
+
+// Underlying type to an ptr to an array of mips asm words that must terminate with an ac_yield.
 #define MipsAtom_(sym) MipsCode sym [] align_(4) =
 
+// Used for atoms with value-args
+//   FI_ void ac_X(args) MipsAtomComp_Proc_(ac_X, { body })
+// expands to:
+//   FI_ void ac_X(args) { MipsCode ac_X[] align_(4) = { body }; return ac_X; }
+#define MipsAtom_Proc_(sym, aa, ...) { MipsCode sym [] align_(4) = __VA_ARGS__; return atomarena_push(aa, slice_from_array(MipsCode, sym)); }
+
 // Used for components with no args (e.g., ac_load_tri_indices) or identifier-args (hardcoded register names).
 //   MipsAtomComp_(ac_X) { body }
 // expands to:
 //   MipsCode ac_X[] align_(4) = { body };
 #define MipsAtomComp_(sym) MipsCode sym [] align_(4) =
 
-// Used for components with value-args (e.g., ac_format_f3_color).
-//   FI_ Slice_MipsCode ac_X(args) MipsAtomComp_Proc_(ac_X, { body })
+// Used for components with value-args (mandatory `ab` (atom-builder) arg).
+//   FI_ void ac_X(MipsAtomBuilder_R ab, args) MipsAtomComp_Proc_(ac_X, ab, { body })
 // expands to:
-//   FI_ Slice_MipsCode ac_X(args) { MipsCode ac_X[] align_(4) = { body }; return slice_from_array(MipsCode, ac_X); }
-#define MipsAtomComp_Proc_(sym, ...) { MipsCode sym [] align_(4) = __VA_ARGS__; return slice_from_array(MipsCode, sym); }
-
-/* Line-table anchor: gcc only adds a file to the .debug_line file table when the
-   file contains line-numbered content. Files containing only:
-     - `MipsAtomComp_` static-array declarations, or
-     - `MipsAtomComp_Proc_` (force-inline) function bodies whose line info gets
-       attributed to the call site at the include point are otherwise omitted from the file table,
-			 which breaks the DWARF injection when it tries to resolve atom-component provenance paths.
+//   FI_ void ac_X(MipsAtomBuilder_R ab, args) {
+//       MipsCode ac_X[] align_(4) = { body };
+//       atombuilder_unroll(ab, slice_from_array(MipsCode, ac_X));
+//   }
+// The body must NOT include mac_yield() (the parent atom yields).
+// Inline-only callers (the generated `mac_<name>` aliases) skip this arg via metaprogram filtering;
+// escape callers (ac_<name> invoked as a function) pass a long-lived builder.
+#define MipsAtomComp_Proc_(sym, ab, ...) { MipsCode sym [] align_(4) = __VA_ARGS__; atombuilder_push(ab, slice_from_array(MipsCode, sym)); }
 
+/* Line-table anchor: gcc only adds a file to the .debug_line file table when the contains line-numbered content.
+	Files containing only atoms and atom components.
    Place `ATOM_FILE_LINE_MARKER();` once at file scope in any `.atom.c` that defines atoms.
 	 The macro expands to a file-scope `internal U4 const` declaration keeps the file in the line table.
 	 The constant is in `.rodata` and unreferenced; the linker may eliminate it.
@@ -132,10 +149,10 @@ typedef U4 const MipsAtom; // Underlying type to an array of mips asm words that
 	 (the identifier embeds the source line, so duplicates across `#include`d files don't collide). */
 #define ATOM_FILE_DEBUGGER_LINE_MARKER(file_name) internal U4 const tmpl(atom_file_debugger_line_marker,file_name) = 0
 
- typedef Slice_(MipsAtom); typedef Slice_MipsAtom Tape;
+typedef Slice_MipsAtom Tape;
 
 /* The 'Exit' Atom */
-atom_dbg_skip MipsAtom_(tape_exit) { jump_reg(rret_addr), nop };
+atom_dbg_skip MipsAtom_(tape_exit) { jump_reg(R_RA), nop };
 
 // TODO(Ed): When we have a substantial workload/throughput, profile each of these to see impact at ABI boundaries.
 
@@ -179,13 +196,15 @@ FI_ void tape_run_a02_s07(Tape tape) { register U4* tape_ptr rgcc(R_TapePtr) = u
 typedef Relative_(FArena) Struct_(TapeBuilder) { U4 ptr; U4 capacity; U4 used; };
 FI_ void        tb_init(TapeBuilder* tb, FArena* arena) { tb->ptr = arena->start; tb->used = 0; }
 FI_ TapeBuilder tb_make_old(             FArena* arena) { return (TapeBuilder){ arena->start, 0 }; }
-FI_ TapeBuilder tb_make(Slice mem) { return (TapeBuilder){ mem.ptr, mem.len, 0 }; }
+FI_ TapeBuilder tb_make(Slice mem) { return (TapeBuilder){ u4_(mem.ptr), mem.len, 0 }; }  /* capacity in elements (matches used units) */
 
-FI_ void tb_emit(TapeBuilder* tb, MipsCode* atom) { u4_r(tb->ptr)[tb->used] = u4_(atom); ++ tb->used; }
+FI_ void tb_emit(TapeBuilder* tb, MipsAtom* atom) { u4_r(tb->ptr)[tb->used] = u4_(atom); ++ tb->used; }
 FI_ void tb_data(TapeBuilder* tb, U4        data) { u4_r(tb->ptr)[tb->used] = u4_(data); ++ tb->used; }
 #define tb_emit_(atom)        tb_emit(& tb, atom)
 #define tb_data_(field, data) tb_data(& tb, u4_(data))
 
+FI_ void tb_emit_bundle(TapeBuilder_R tb, Slice_MipsAtom atoms) { mem_copy(u4_(tb->ptr), u4_(atoms.ptr), S_slice(atoms)); tb->used += atoms.len; }
+
 FI_ Tape tb_end  (TapeBuilder* tb) { tb_emit(tb,tape_exit); return (Tape){ C_(U4*,tb->ptr), tb->used }; }
 FI_ Tape tb_slice(TapeBuilder  tb) {                        return (Tape){ C_(U4*,tb.ptr),  tb.used }; }
 #define tb_scope(tb)     for(U4 tbs_once=0;tbs_once==0;++tbs_once,tb_emit(tb,tape_exit))
@@ -220,35 +239,85 @@ atom_dbg_skip MipsAtomComp_(ac_yield_tail) {
 	add_ui_self(R_TapePtr, S_(MipsCode)),
 	jump_reg(  R_AtomJmp), nop,
 };
-
 #pragma endregion Macro Atom Components
 
-#pragma region Mips Atom Builder
+#pragma region Atom Builder
 // This helps with runtime procedural authoring of mips atoms.
 
 typedef Struct_(FMipsAtom512) { U4 data[512]; U4 used; };
 
 // FArena Related
-typedef Relative_(FArena) Struct_(MipsAtomBuilder) { U4 start; U4 capacity; U4 used; };
-// Whatever the builder is writting to should most likely coresspond
-// to something that can fit within instruction cache?
+typedef Relative_(FArena) Struct_(AtomBuilder) { U4 start; U4 capacity; U4 used; };
 
-FI_ void atombuilder_unroll(MipsAtomBuilder_R ab, Slice_MipsCode_R code) {
-	assert(ab->capacity - ab->used - code->len);
-	mem_copy(ab->start, u4_(code->ptr), code->len);
-	mem_bump(ab->start, ab->capacity, & ab->used, code->len);
+// Usual way to resolve an atom after the bulder is done.
+#define atom_from_atombuilder(ab) C_(MipsAtom*, (ab).start)
+
+FI_ void atombuilder_push(AtomBuilder_R ab, Slice_MipsCode code) {
+	assert(ab->capacity - ab->used - code.len);
+	U4 dest = ab->start + ab->used * S_(MipsCode); U4 size = S_slice(code);
+	mem_copy(dest, u4_(code.ptr), size); ab->used += size;
 }
-#define atombuilder_unroll_mac(ab, mac) atombuilder_unroll(ab, slice_arg_from_array(Slice_MipsCode, mac))
+#define atombuilder_push_mac(ab, mac) atombuilder_push(ab, slice_arg_from_array(Slice_MipsCode, mac))
 
-// When done authoring, utilize this to cap-off the atom
-FI_ void atombuilder_end(MipsAtomBuilder_R ab) {
-	mem_copy(ab->start, u4_(ac_yield), S_(ac_yield));
-	mem_bump(ab->start, ab->capacity, & ab->used, S_(ac_yield));
-}
+// When done authoring, utilize this to cap-off the atom (if not utilizing a MipsAtom_Proc).
+FI_ void atombuilder_end(AtomBuilder_R ab) { atombuilder_push(ab, slice_from_array(MipsCode, ac_yield)); }
 
-#define mipsatom_from_builder(ab) (Slice_MipsCode){ab.start, ab.used}
+FI_ void tb_emit_atombuilder(TapeBuilder_R tb, AtomBuilder_R ab) { tb_emit(tb, atom_from_atombuilder(ab[0])); }
 #pragma endregion Mips Atom Builder
 
+#pragma region Atom Arena
+// Just a dedicated FArena that is meant to mem_copy and return atom definitions made with MipsAtom_Proc_
+
+typedef Relative_(FArena) Struct_(AtomArena) { U4 start; U4 capacity; U4 used; };
+
+#define atomarena_unused_start(ab) ((ab).start + (ab).used)
+FI_ void atomarena_init(AtomArena_R arena, Slice mem) {  assert(arena != nullptr);
+	arena->start    = u4_(mem.ptr);
+	arena->capacity = mem.len;
+	arena->used     = 0;
+}
+FI_ AtomArena atomarena_make(Slice mem) { AtomArena a; atomarena_init(& a, mem); return a; }
+FI_ MipsAtom* atomarena_push(AtomArena_R aa, Slice_MipsCode code) {
+	assert(aa->capacity - aa->used - code.len);
+	U4 dest = atomarena_unused_start(aa[0]); U4 size = S_slice(code);
+	mem_copy(dest, u4_(code.ptr), size); aa->used += size;
+	return C_(MipsAtom*, dest);
+}
+FI_ void atomarena_reset(AtomArena_R aa) { aa->used = 0; }
+#pragma region Atom Arena
+
+#pragma region RegFile (Register File Allocator)
+// A specialized allocator utilized to help the user track which registers are bound to values
+// that must be preserved for the arena's bounds.
+
+enum {
+	RegFileArena_Len,
+};
+typedef Enum_(U4, RegFileEntry) {
+	// TODO(Ed): Define RF_Field, each field is maped by index + bit pos.
+	// the index is the upper portion of a U4 and the bit pos in the lower pos.
+
+	regfileentry_todo_,
+	// TODO(Ed): Is there a trick we can do with the current register enums to 
+	// just resolve an entry automatically when doing a pin?
+};
+typedef Struct_(RegFile) {
+	U1 GPR[RegFileArena_Len];
+	U1 GTE[RegFileArena_Len];
+	U1 GP[RegFileArena_Len];
+};
+
+void regfile_pin(U4 register) {
+
+	assert(false);
+}
+
+#pragma endregion RegFileArena (Register File Allocator)
+
+#pragma region Mips Atom Procs
+
+#pragma endregion Mips Atom Procs
+
 #pragma region Baked Mips Atoms
 // These atoms are resolved at compile time and are (usually) statically linked readonly data.
 

code/duffle/math.atom.c

@@ -9,17 +9,41 @@ ATOM_FILE_DEBUGGER_LINE_MARKER(math_atom_c);
 
 #pragma region MACs (Mips Atom Component)
 
-FI_ Slice_MipsCode ac_load_v2s2(U4 rs_x, U4 rs_y, U4 r_base, U4 offset) atom_dbg_skip MipsAtomComp_Proc_(ac_load_v2s2, {
-	load_half( rs_x, r_base, O_(V3_S2,x)),
-	load_half( rs_y, r_base, O_(V3_S2,y)),
+FI_ Slice_MipsCode ac_load_v2s2(AtomBuilder_R ab, U4 rs_x, U4 rs_y, U4 r_base, U4 offset) atom_dbg_skip MipsAtomComp_Proc_(ac_load_v2s2, ab, {
+	load_half( rs_x, r_base, offset + O_(V3_S2,x)),
+	load_half( rs_y, r_base, offset + O_(V3_S2,y)),
 })
 
-FI_ Slice_MipsCode ac_store_v2s2(U4 rt_x, U4 rt_y, U4 base, U4 offset) atom_dbg_skip MipsAtomComp_Proc_(ac_store_v2s2, {
+FI_ Slice_MipsCode ac_store_v2s2(AtomBuilder_R ab, U4 rt_x, U4 rt_y, U4 base, U4 offset) atom_dbg_skip MipsAtomComp_Proc_(ac_store_v2s2, ab, {
 	store_half(rt_x, base, offset + O_(V2_S2,x)),
 	store_half(rt_y, base, offset + O_(V2_S2,y)),
 })
 
-FI_ Slice_MipsCode ac_store_rects2(U4 rt_x, U4 rt_y, U4 rt_width, U4 rt_height, U4 base, U4 offset) atom_dbg_skip MipsAtomComp_Proc_(ac_store_rects2, {
+FI_ Slice_MipsCode ac_load_v3s4(AtomBuilder_R ab, U4 rs_x, U4 rs_y, U4 rs_z, U4 r_base, U4 offset) atom_dbg_skip MipsAtomComp_Proc_(ac_load_v3s4, ab, {
+	load_word( rs_x, r_base, offset + O_(V3_S4,x)),
+	load_word( rs_y, r_base, offset + O_(V3_S4,y)),
+	load_word( rs_z, r_base, offset + O_(V3_S4,z)),
+})
+// TODO(Ed): we could generate these mappings properly..
+#define ac_load_p3s4 ac_load_v3s4
+#define mac_load_p3s4 mac_load_v3s4
+
+FI_ Slice_MipsCode ac_store_v3s4(AtomBuilder_R ab, U4 rt_x, U4 rt_y, U4 rt_z, U4 base, U4 offset) atom_dbg_skip MipsAtomComp_Proc_(ac_store_v3s4, ab, {
+	store_word(rt_x, base, offset + O_(V3_S4,x)),
+	store_word(rt_y, base, offset + O_(V3_S4,y)),
+	store_word(rt_z, base, offset + O_(V3_S4,z)),
+})
+// TODO(Ed): we could generate these mappings properly..
+#define ac_store_p3s4 ac_store_v3s4
+#define mac_store_p3s4 mac_store_v3s4
+
+FI_ Slice_MipsCode ac_sub_v3s4(AtomBuilder_R ab, U4 rds_x, U4 rds_y, U4 rds_z, U4 rt_x,  U4 rt_y,  U4 rt_z) atom_dbg_skip MipsAtomComp_Proc_(ac_sub_v3s4, ab, {
+	sub_s(rds_x, rds_x, rt_x),
+	sub_s(rds_y, rds_y, rt_y),
+	sub_s(rds_z, rds_z, rt_z),
+})
+
+FI_ Slice_MipsCode ac_store_rects2(AtomBuilder_R ab, U4 rt_x, U4 rt_y, U4 rt_width, U4 rt_height, U4 base, U4 offset) atom_dbg_skip MipsAtomComp_Proc_(ac_store_rects2, ab, {
 	store_half(rt_x,      base, offset + O_(Rect_S2,x)),
 	store_half(rt_y,      base, offset + O_(Rect_S2,y)),
 	store_half(rt_width,  base, offset + O_(Rect_S2,width)),

code/duffle/math.h

@@ -7,6 +7,18 @@
 #define max(A, B)       (((A) > (B)) ? (A) : (B))
 #define clamp_bot(X, B) max(X, B)
 
+/* Convention
+<Type> ## <Width> _ <Component Type> ## <Component Width>
+For types with compound data (Ex: Rotation Matrix & Translation):
+<TypeA> ## <TypeB> ## <Width> _ <ComponentTypeA> ## <ComponentWidthA> ## <ComponentTypeB> ## <ComponentWidthB>
+
+A: Array
+V: Vector
+R: Range
+M: Matrix
+T: Translation
+*/
+
 enum { 
 	v3s2_byteoff = 3, // log2(8), used with shift_left_logical op for index via byte offset.
 };
@@ -26,24 +38,38 @@ typedef Struct_(Extent2_S4) { S4 width; S4 height; };
 typedef Struct_(V2_U1)      { U1 x; U1 y; };
 typedef Struct_(V2_S2)      { S2 x; S2 y; };
 typedef Struct_(V2_S4)      { S4 x; S4 y; };
-typedef Struct_(V3_S2)      { S2 x; S2 y; S2 z; S2 pad; };
-typedef Struct_(V3_S4)      { S4 x; S4 y; S4 z; S4 pad; };
+typedef Struct_(V3_S2)      { S2 x; S2 y; S2 z; S2 pad; }; // PSY-Q: SVECTOR
+typedef Struct_(V3_S4)      { S4 x; S4 y; S4 z; S4 pad; }; // PSY-Q: VECTOR. RGA(Lengyel): Euclidean vector or direction. A zero-weight RGA point is stored as a V3_S4 with the implicit weight dropped.
 typedef Struct_(V4_S2)      { S2 x; S2 y; S2 z; S2 w; };
 typedef Struct_(V4_S4)      { S4 x; S4 y; S4 z; S4 w; };
 
-typedef Struct_(R2_S2)      { V2_S2 p0; V2_S2 p1; };
-typedef Struct_(R2_S4)      { V2_S4 p0; V2_S4 p1; };
+// typedef Struct_(P3_S4)      { S4 x; S4 y; S4 z; S4 w1; }; // RGA(Lengyel): Affine point with implicit weight one. Storage alias of V3_S4. Use P3_S4 when the value is a point.
+typedef V3_S4 P3_S4;
+
+typedef Struct_(R2_S2)      { V2_S2 p0; V2_S2 p1; }; // Range-2 Signed 2-Byte (16-bit)
+typedef Struct_(R2_S4)      { V2_S4 p0; V2_S4 p1; }; // Range-2 Signed 4-Byte (32-bit)
 
 typedef Struct_(Rect_S2)    { S2 x; S2 y; S2 width; S2 height; };
 typedef Struct_(Rect_S4)    { S4 x; S4 y; S4 width; S4 height; };
 
-typedef Struct_(M3_S2)      { A3x3_S2 m; A3_S4 t; };
+typedef Struct_(MT3_S2S4)   { A3x3_S2 m; A3_S4 t; }; // PSY-Q: MATRIX. RGA(Lengyel): Matrix expansion of a rigid transformation. GTE utilizes this representation; corresponding motor not constructed here.
+
+/* RGA(Lengyel) reserved names (deferred):
+ *   P4_S4  - future flat point with explicit weight (Lengyel/TML FlatPoint3D analog).
+ *   B3_S4  - future 3D bivector (callers store a Complement(Wedge(...)) as a V3_S4).
+ *   Mo8_S4 - future motor. Not introduced until a course operation actually needs composition, interpolation, or inversion. */
 
 typedef Array_(V2_U1, 2);
 typedef Array_(V2_S2, 2);
 typedef Array_(V2_S2, 3);
 typedef Array_(V2_S2, 4);
 
+enum {
+	fp_one = (1 << 12),
+};
+
+#define v3s4_fp_one() v3s4(fp_one, fp_one, fp_one)
+
 #define v2s2(x,y)     (V2_S2){x,y}
 #define v3s2(x,y,z)   (V3_S2){x,y,z,0}
 #define v3s4(x,y,z)   (V3_S4){x,y,z,0}
@@ -62,5 +88,28 @@ FI_ void add_a3s4_fp(A3_S4_R out_a, A3_S4 b) {
 	(out_a[0])[2] += b[2] >> 1;
 }
 
+FI_ void sub_a3s4(A3_S4_R out_a, A3_S4 b) {
+	(out_a[0])[0] -= b[0];
+	(out_a[0])[1] -= b[1];
+	(out_a[0])[2] -= b[2];
+}
+
+FI_ void sub_a3s4_fp(A3_S4_R out_a, A3_S4 b) {
+	(out_a[0])[0] -= b[0] >> 1;
+	(out_a[0])[1] -= b[1] >> 1;
+	(out_a[0])[2] -= b[2] >> 1;
+}
+
+FI_ void mul_a3s4(A3_S4_R out_a, A3_S4 b) {
+	(out_a[0])[0] *= b[0];
+	(out_a[0])[1] *= b[1];
+	(out_a[0])[2] *= b[2];
+}
+
 FI_ void add_v3s4   (V3_S4_R out_a, V3_S4 b) {  add_a3s4   (pcast(A3_S4_R, out_a), pcast(A3_S4, b));  }
 FI_ void add_v3s4_fp(V3_S4_R out_a, V3_S4 b) {  add_a3s4_fp(pcast(A3_S4_R, out_a), pcast(A3_S4, b));  }
+
+FI_ void sub_v3s4   (V3_S4_R out_a, V3_S4 b) {  sub_a3s4   (pcast(A3_S4_R, out_a), pcast(A3_S4, b));  }
+FI_ void sub_v3s4_fp(V3_S4_R out_a, V3_S4 b) {  sub_a3s4_fp(pcast(A3_S4_R, out_a), pcast(A3_S4, b));  }
+
+FI_ void mul_v3s4   (V3_S4_R out_a, V3_S4 b) {  mul_a3s4   (pcast(A3_S4_R, out_a), pcast(A3_S4, b));  }

code/duffle/memory.h

@@ -18,7 +18,7 @@ I_ U4 align_pow2(U4 x, U4 b) {
 
 #define align_struct(type_width) ((U4)(((type_width) + 3) & ~3))
 
-FI_ void mem_bump(U4 start, U4 cap, U4*R_ used, U4 amount) {
+FI_ void mem_bump(U4 cap, U4*R_ used, U4 amount) {
 	assert(amount <= (cap - used[0])); 
 	used[0] += amount; 
 }
@@ -58,13 +58,13 @@ typedef Struct_(Str8)        { UTF8* ptr; U4 len; };
 typedef Struct_(Slice_Str8)  { Str8* ptr; U4 len; };
 #define slit(string_literal) (Str8){ (UTF8*) string_literal, S_(string_literal) - 1 }
 
-typedef Struct_(Slice) { U4 ptr, len; }; // Untyped Slice
-FI_ Slice slice_ut_(U4 ptr, U4 len) { return (Slice){ptr, len}; }
+typedef Struct_(Slice) { B1* ptr; U4 len; }; // Untyped Slice (byte-addressable; .len in elements)
+FI_ Slice slice_ut_(U4 ptr, U4 len) { return (Slice){(B1*)ptr, len}; }
 
 #define Slice_(type)       Struct_(tmpl(Slice,type)) { type* ptr; U4 len; }
 typedef Slice_(B1);
 #define slice_assert(s)    do { assert((s).ptr != 0); assert((s).len > 0); } while(0)
-#define slice_end(slice)   ((slice).ptr + (slice).len)
+#define slice_end(slice)   ((slice).ptr + S_slice(slice) / S_(B1))  /* byte-ptr arithmetic; .len is in elements per slice convention */
 #define S_slice(s)         ((s).len * S_((s).ptr[0]))
 
 #define slice_ut(ptr,len)  slice_ut_(u4_(ptr),     u4_(len))
@@ -72,23 +72,30 @@ typedef Slice_(B1);
 #define slice_to_ut(s)     slice_ut_(u4_((s).ptr), S_slice(s))
 
 #define slice_iter(container, iter)     (T_((container).ptr) iter = (container).ptr; iter != slice_end(container); ++ iter)
-#define slice_arg_from_array(type, ...) & (tmpl(Slice,type)) { .ptr = array_decl(type,__VA_ARGS__), .len = array_len( array_decl(type,__VA_ARGS__)) }
-#define slice_from_array(type, array)     (tmpl(Slice,type)) { .ptr = array, .len = S_(array) }
+#define slice_arg_from_array(type, ...) & (tmpl(Slice,type)) { .ptr = Array_decl(type,__VA_ARGS__), .len = Array_len( Array_decl(type,__VA_ARGS__)) }
+#define slice_from_array(type, array)     (tmpl(Slice,type)) { .ptr = array, .len = S_(array) / S_(type) }
 
-FI_ void slice_zero_(Slice s) { slice_assert(s); mem_zero(s.ptr, s.len); }
+FI_ void slice_zero_(Slice s) { slice_assert(s); mem_zero(u4_(s.ptr), s.len); }
 #define  slice_zero(s)        slice_zero_(slice_to_ut(s))
 
 FI_ void slice_copy_(Slice dest, Slice src) {
-	assert(dest.len >= src.len);
+	assert(S_slice(dest) >= S_slice(src));
 	slice_assert(dest);
 	slice_assert(src);
-	mem_copy(dest.ptr, src.ptr, src.len);
+	mem_copy(u4_(dest.ptr), u4_(src.ptr), S_slice(src));
 }
 #define slice_copy(dest, src) do {  \
 	static_assert(T_same(dest, src)); \
 	slice_copy_(slice_to_ut(dest), slice_to_ut(src)); \
 } while(0)
 
+FI_ Slice slice_bump(U4_R used, U4 start, U4 len, U4 amount) {
+	assert(len - used[0] - amount);
+	U4 ptr = start + used[0]; used[0] += amount;
+	return slice_ut(ptr, amount);
+}
+
+typedef Slice_(U1);
 typedef Slice_(U4);
 
 #pragma endregion Slice
@@ -98,18 +105,19 @@ typedef Slice_(U4);
 typedef Opt_(farena)    { U4 alignment, type_width; };
 typedef Struct_(FArena) { U4 start, capacity, used; };
 FI_ void farena_init(FArena_R arena, Slice mem) {  assert(arena != nullptr);
-	arena->start    = mem.ptr;
+	arena->start    = u4_(mem.ptr);
 	arena->capacity = mem.len;
 	arena->used     = 0;
 }
 FI_ FArena farena_make(Slice mem) { FArena a; farena_init(& a, mem); return a; }
-I_  Slice  farena_push(FArena_R arena, U4 amount, Opt_farena o) {
+FI_ Slice farena_bump(FArena_R a, U4 amount) { return slice_bump(& a->used, a->start, a->capacity, amount); }
+I_  Slice farena_push(FArena_R arena, U4 amount, Opt_farena o) {
 	if (amount == 0) { return (Slice){}; }
 	U4 desired   = amount * (o.type_width == 0 ? 1 : o.type_width);
 	U4 to_commit = align_pow2(desired, o.alignment ?  o.alignment : MEM_ALIGNMENT_DEFAULT);
 	U4 ptr       = arena->start + arena->used;
-	mem_bump(arena->start, arena->capacity, & arena->used, to_commit);
-	return (Slice){ ptr, to_commit };
+	mem_bump(arena->capacity, & arena->used, to_commit);
+	return (Slice){ (B1*)ptr, to_commit };
 }
 FI_ void farena_reset (FArena_R arena) { arena->used = 0; }
 FI_ void farena_rewind(FArena_R arena, U4 save_point) {
@@ -117,6 +125,7 @@ FI_ void farena_rewind(FArena_R arena, U4 save_point) {
 	arena->used -= save_point - arena->start;
 }
 FI_ U4 farena_save(FArena arena) { return arena.used; }
+FI_ U4 farena_unused_start(FArena arena) { return arena.start + arena.used; }
 #define farena_push_(arena, amount, ...)                                          farena_push((arena), (amount), opt_(farena, __VA_ARGS__))
 #define farena_push_type(arena, type, ...)                              C_(type*, farena_push((arena), 1,        opt_(farena, .type_width=S_(type), __VA_ARGS__)).ptr)
 #define farena_push_array(arena, type, amount, ...) (tmpl(Slice,type)){ C_(type*, farena_push((arena), (amount), opt_(farena, .type_width=S_(type), __VA_ARGS__)).ptr), (amount) }

code/duffle/mips.atom.c

@@ -1,6 +1,7 @@
 #ifdef INTELLISENSE_DIRECTIVES
 #	include "gen/macs.h"
 #	include "gen/offsets.h"
+#	include "bios.h"
 #	include "lottes_tape.h"
 #endif
 
@@ -8,11 +9,6 @@ ATOM_FILE_DEBUGGER_LINE_MARKER(mips_atom_c);
 
 #pragma region Baked Atoms
 
-enum {
-	bios_flushcache = 0x44,
-	bios_table_addr = 0xA0,
-};
-
 /* Flushes the Instruction Cache (PSX A-function 0x44 via BIOS stub at 0xA0).
  * Sequence (per MIPS ABI; arguments in arg registers, RA pushed to stack):
  *   1. sp -= 8;  sw $ra, 4($sp)        ; save RA
@@ -24,14 +20,14 @@ enum {
  *   6. sp += 8
  */
 internal MipsAtom_(mips_flush_icache) {
-	add_ui(rstack_ptr, rstack_ptr, -MipsStackAlignment), // sp -= 8
-	store_word(rret_addr, rstack_ptr, S_(U4)),           // sw  $ra,   4($sp) 
-	add_ui(rret_0, rdiscard, bios_flushcache),           // addiu $a0, $0, 0x44 
-	add_ui(rtmp_0, rdiscard, bios_table_addr),           // addiu $t0, $0, 0xA0 
-	jump_link(rtmp_0, rret_addr), nop,                   // jalr  $t0, $ra, BD slot
-	load_word(rret_addr, rstack_ptr, S_(U4)),            // lw   $ra, 4($sp) 
-	jump_reg(rret_addr),                                 // jr   $ra 
-	add_ui(rstack_ptr, rstack_ptr, MipsStackAlignment),  // sp += 8 (BD) 
+	add_ui(R_SP, R_SP, -MipsStackAlignment), // sp -= 8
+	store_word(R_RA, R_SP, S_(U4)),           // sw  $ra,   4($sp) 
+	add_ui(R_V0, R_0, bios_flushcache),           // addiu $a0, $0, 0x44 
+	add_ui(R_T0, R_0, bios_table_addr),           // addiu $t0, $0, 0xA0 
+	jump_link(R_T0, R_RA), nop,                   // jalr  $t0, $ra, BD slot
+	load_word(R_RA, R_SP, S_(U4)),            // lw   $ra, 4($sp) 
+	jump_reg(R_RA),                                 // jr   $ra 
+	add_ui(R_SP, R_SP, MipsStackAlignment),  // sp += 8 (BD) 
 	mac_yield(),
 };
 

code/duffle/mips.h

@@ -136,31 +136,31 @@ enum {
 
 /* Semantic Aliases for MIPS Registers (O32 ABI) */
 
-	, rdiscard      = R_0  /* Hardwired to 0 */
-	, rasm_tmp      = R_AT /* Assembler temporary (destroyed by some assembler pseudoinstructions!) */
-	, rret_0        = R_V0 /* Function return value */
-	, rret_1        = R_V1 /* Second return value (e.g., 64-bit) */
-	, rarg_0        = R_A0 /* First function argument */
-	, rarg_1        = R_A1 /* Second function argument */
-	, rarg_2        = R_A2 /* Third function argument */
-	, rarg_3        = R_A3 /* Fourth function argument */
-	, rtmp_0        = R_T0 /* Temporary (Caller saved) */
-	, rtmp_1        = R_T1 /* Temporary (Caller saved) */
-	, rtmp_2        = R_T2 /* Temporary (Caller saved) */
-	, rtmp_3        = R_T3 /* Temporary (Caller saved) */
-	, rtmp_4        = R_T4 /* Temporary (Caller saved) — common GTE base pointer */
-	, rtmp_9        = R_T9 /* Temporary (Caller saved) — common GTE base pointer */
-	, rstatic_0     = R_S0 /* Static (Callee saved, preserved across calls) */
-	, rstatic_1     = R_S1
-	, rstatic_2     = R_S2
-	, rstatic_3     = R_S3
-	, rstatic_4     = R_S4
-	, rstatic_5     = R_S5
-	, rstatic_6     = R_S6
-	, rstatic_7     = R_S7
-	, rsaved_0      = R_S0 /* Alias for rstatic_0 (alternate vocabulary) */
-	, rstack_ptr    = R_SP /* Stack Pointer */
-	, rret_addr     = R_RA /* Return Address (populated by JAL) */
+	// , rdiscard      = R_0  /* Hardwired to 0 */
+	// , rasm_tmp      = R_AT /* Assembler temporary (destroyed by some assembler pseudoinstructions!) */
+	// , rret_0        = R_V0 /* Function return value */
+	// , rret_1        = R_V1 /* Second return value (e.g., 64-bit) */
+	// , rarg_0        = R_A0 /* First function argument */
+	// , rarg_1        = R_A1 /* Second function argument */
+	// , rarg_2        = R_A2 /* Third function argument */
+	// , rarg_3        = R_A3 /* Fourth function argument */
+	// , rtmp_0        = R_T0 /* Temporary (Caller saved) */
+	// , rtmp_1        = R_T1 /* Temporary (Caller saved) */
+	// , rtmp_2        = R_T2 /* Temporary (Caller saved) */
+	// , rtmp_3        = R_T3 /* Temporary (Caller saved) */
+	// , rtmp_4        = R_T4 /* Temporary (Caller saved) — common GTE base pointer */
+	// , rtmp_9        = R_T9 /* Temporary (Caller saved) — common GTE base pointer */
+	// , rstatic_0     = R_S0 /* Static (Callee saved, preserved across calls) */
+	// , rstatic_1     = R_S1
+	// , rstatic_2     = R_S2
+	// , rstatic_3     = R_S3
+	// , rstatic_4     = R_S4
+	// , rstatic_5     = R_S5
+	// , rstatic_6     = R_S6
+	// , rstatic_7     = R_S7
+	// , rsaved_0      = R_S0 /* Alias for rstatic_0 (alternate vocabulary) */
+	// , rstack_ptr    = R_SP /* Stack Pointer */
+	// , rret_addr     = R_RA /* Return Address (populated by JAL) */
 
 /* --- MIPS CPU Opcodes (Bits 31-26) --- */
 
@@ -348,6 +348,12 @@ enum { _BitOffsets = 0
 #define shift_lright(rd, rt, shamt) enc_r(op_special, R_0,  (rt), (rd), (shamt), fc_srl)
 #define shift_aright(rd, rt, shamt) enc_r(op_special, R_0,  (rt), (rd), (shamt), fc_sra)
 
+/* Shift Variable — register-shift forms.
+ * shift_lleft_var(rd, rt, rs)  → sllv rd, rt, rs   (shamt in low 5 bits of rs)
+ * shift_aright_var(rd, rt, rs) → srav rd, rt, rs */
+#define shift_lleft_var(rd, rt, rs)  enc_r(op_special, (rs), (rt), (rd), 0, fc_sllv)
+#define shift_aright_var(rd, rt, rs) enc_r(op_special, (rs), (rt), (rd), 0, fc_srav)
+
 #define shift_lleft_self(rd_rt, shamt) enc_r(op_special, R_0, (rd_rt), (rd_rt), (shamt), fc_sll)
 
 #define mask_upper(rd, rt, shamt) shift_lleft(rd, rt, shamt), shift_lright(rd, rt, shamt)
@@ -366,20 +372,18 @@ enum { _BitOffsets = 0
  * WARNING: `jump(off)` CANNOT BE USED for within-atom jumps in the current pipeline.
  * The MIPS j opcode encodes `(target_addr >> 2)` in its 26-bit immediate field; an  ABSOLUTE byte address, not a relative word offset.
  * The metaprogram computes `off` as a relative word offset (`target_word_idx - branch_word_idx - 1`), which the assembler/linker does NOT resolve.
- *
  * `jump(off)` is only safe when the BUILD PIPELINE owns the absolute position of the emitted code — i.e. when: s
  *   - the build emits a symbol-relative `.word` expression that the linker resolvess via `R_MIPS_26`, OR
  *   - the code is hand-assembled with explicit absolute targets, OR a custom post-build patcher resolves the 26-bit field.
+ * TODO(Ed): Review this.. technically we can resolve aboslute jumps on baked atoms? (Even proedurally generated ones...)
  */
 #define jump(off)                  enc_i(op_j,     R_0, R_0, (off))
 
 /* jump_rel off — unconditional relative jump (the within-atom-safe `jump`).
- * MIPS I R3000A has no "branch always" opcode. The idiom for an unconditional relative jump is `beq $0, $0, off`.
- */
+ * MIPS I R3000A has no "branch always" opcode. The idiom for an unconditional relative jump is `beq $0, $0, off`. */
 #define jump_rel(off)              branch_equal(R_0, R_0, (off))
 
 /* call_addr off — jump-and-link to immediate address.
- *
  * Same WARNING as `jump(off)` above: the jal opcode also encodes an absolute 26-bit target.
  * For within-atom calls, the current pipeline has no equivalent always-taken call-and-link idiom.
  * Workaround: `branch_link` (always-taken branch + explicit `la $ra, next_word_addr; jr $ra`), or just use `call_reg($tmp)` after loading the target into a register.
@@ -397,13 +401,7 @@ enum { _BitOffsets = 0
  * sub_s / sub_u  → sub / subu
  * mult_s / mult_u → mult / multu   (writes HI/LO; result in LO)
  * div_s / div_u   → div / divu     (LO = quot, HI = rem)
- *
- * NOTE: dsl.h defines `add_s`/`sub_s`/`mut_s`/`gt_s`/etc. as _Generic-based signed integer-arithmetic helpers for U1/U2/U4.
- * Those live in a different conceptual layer (generic arithmetic on DSL types) and would collide with the instruction encoders here.
- * The `#undef` below lets the gas-style names below win; if a file needs both, the dsl.h versions can be reached via their long forms
- * (e.g. `def_signed_op`-style or the underlying `add_s1/s2/s4`). */
-#undef add_s
-#undef sub_s
+ */
 #define add_s(rd, rs, rt)          enc_r(op_special, (rs), (rt), (rd), 0, fc_add)
 #define add_u(rd, rs, rt)          enc_r(op_special, (rs), (rt), (rd), 0, fc_addu)
 #define sub_s(rd, rs, rt)          enc_r(op_special, (rs), (rt), (rd), 0, fc_sub)
@@ -455,9 +453,12 @@ enum { _BitOffsets = 0
 #define shift_amount(rd, rt, n)     shift_lleft(rd, rt, n)
 
 /* nop — sll $0, $0, 0 */
-#define nop  shift_lleft(rdiscard, rdiscard, 0)
+#define nop  shift_lleft(R_0, R_0, 0)
 #define nop2 nop, nop
 
+// li_s — load signed 16-bit immediate into GPR (addiu rt, $0, imm — sign-extends).
+#define li_s(rt, imm)  add_ui((rt), R_0, (imm))
+
 #define load_imm_1w(rt, imm)    add_ui((rt),  R_0, (imm))
 #define load_imm_1w_s0(rt, imm) add_si((rt)), R_0, (imm))
 

code/duffle/pad.atom.c

@@ -11,18 +11,18 @@ ATOM_FILE_DEBUGGER_LINE_MARKER(pad_atom_c);
 
 #pragma region MACs (Mips Atom Components)
 
-FI_ Slice_MipsCode ac_pad_set_centered_axes(U4 r_state, U4 r_scratch) atom_dbg_skip MipsAtomComp_Proc_(ac_pad_set_centered_axes, {
+FI_ Slice_MipsCode ac_pad_set_centered_axes(AtomBuilder_R ab, U4 r_state, U4 r_scratch) atom_dbg_skip MipsAtomComp_Proc_(ac_pad_set_centered_axes, ab, {
     load_upper_i(r_scratch, (PadAxis_Centered_Word >> 16) & 0xFFFF),
     or_i_self(   r_scratch,  PadAxis_Centered_Word        & 0xFFFF),
     store_word(  r_scratch, r_state, O_(PadState,axes)),
 })
 
-FI_ Slice_MipsCode ac_pad_set_id_byte(U1 r_state, U1 r_id, U1 id_value) atom_dbg_skip MipsAtomComp_Proc_(ac_pad_set_id_byte, {
+FI_ Slice_MipsCode ac_pad_set_id_byte(AtomBuilder_R ab, U1 r_state, U1 r_id, U1 id_value) atom_dbg_skip MipsAtomComp_Proc_(ac_pad_set_id_byte, ab, {
     add_ui(    r_id, R_0, id_value),
     store_byte(r_id, r_state, O_(PadState,id)),
 })
 
-FI_ Slice_MipsCode ac_pad_set_status(U4 r_tmp, U1 r_state, U4 pad_status) atom_dbg_skip MipsAtomComp_Proc_(ac_pad_set_status, {
+FI_ Slice_MipsCode ac_pad_set_status(AtomBuilder_R ab, U4 r_tmp, U1 r_state, U4 pad_status) atom_dbg_skip MipsAtomComp_Proc_(ac_pad_set_status, ab, {
     add_ui(    r_tmp, R_0, pad_status),
     store_word(r_tmp, r_state, O_(PadState,status)),
 })
@@ -30,7 +30,7 @@ FI_ Slice_MipsCode ac_pad_set_status(U4 r_tmp, U1 r_state, U4 pad_status) atom_d
 /* Invert r_buttons (active-low → active-high) and store to PadState.buttons.
  * r_buttons must already be loaded (the caller is responsible for filling the load-delay slot of
  * the preceding load_half_u with an instruction that doesn't read r_buttons). */
-FI_ Slice_MipsCode ac_pad_store_inverted_buttons(U1 r_buttons, U1 r_pad_state) atom_dbg_skip MipsAtomComp_Proc_(ac_pad_store_inverted_buttons, {
+FI_ Slice_MipsCode ac_pad_store_inverted_buttons(AtomBuilder_R ab, U1 r_buttons, U1 r_pad_state) atom_dbg_skip MipsAtomComp_Proc_(ac_pad_store_inverted_buttons, ab, {
     nor_u(       r_buttons, r_buttons, R_0),
     store_half(  r_buttons, r_pad_state, O_(PadState,   buttons)),
 })
@@ -93,7 +93,7 @@ atom_label(disconnected) /* === Disconnected body. */
 	mac_pad_set_status(R_T4,  R_PadState, PadStatus_Disconnected),
 	store_half(        R_0,   R_PadState, O_(PadState,buttons)),
 	mac_pad_set_centered_axes(R_PadState, R_T4),
-	mac_pad_set_id_byte(      R_PadState, R_RawId, PadRawStatus_Timeout),
+	mac_pad_set_id_byte(R_PadState, R_RawId, PadRawStatus_Timeout),
 	jump_rel(atom_offset(disconnected, snap_end)),
 		/* BD-slot: load next atom's entry point (replaces the nop).
 		 * Always jumps to snap_end, where mac_yield_tail() transfers control to R_AtomJmp without re-loading it. */
@@ -181,7 +181,7 @@ atom_label(try_unsupported) /* === Case 7: Unsupported — fall through from the
 	store_word(R_T4, R_PadState, O_(PadState,status)),
 	store_half(R_0,  R_PadState, O_(PadState,buttons)),
 	mac_pad_set_centered_axes(R_PadState, R_T4),
-	mac_pad_set_id_byte(      R_PadState, R_RawId, PadUnknownId_Sentinel),
+	mac_pad_set_id_byte(R_PadState, R_RawId, PadUnknownId_Sentinel),
 	/* Fall through to snap_end. */
 
 atom_label(no_jump_fallthrough)

code/duffle/pad.c

@@ -0,0 +1,78 @@
+#ifdef INTELLISENSE_DIRECTIVES
+#	include "dsl.h"
+#	include "gcc_asm.h"
+#	include "mips.h"
+#	include "bios.h"
+#	include "pad.h"
+#endif
+
+/* Uses ONE 8-byte frame allocated via the compiler's standard prologue.
+ * 4 wasted-arg words for B(12h) InitPAD2 are at [SP+0..15] but are not explicitly allocated.
+ * Compiler handles the MIPS O32 "wasted stack" convention for us by treating the B-call as a 4-arg call.
+ *
+ * The buffer pointers are passed as arguments so the compiler keeps them in callee-saved registers;
+ * The B(12h) asm volatile block does NOT clobber those registers (it clobbers only the volatile GPRs + B-table arg registers explicitly).
+ * The C-level writes after the call re-load the pointers from their callee-saved homes.
+ *
+ * The clobber list for both B-calls names the full BIOS destroy set documented in kernelbios.md:167-174 (R1..R15, R24..R25, R31, HI/LO).
+ * The kernel-ABI "volatile GPRs" subset is clb_mem_drain; the rest of the destroy set is enumerated explicitly here. */
+NI_ void pad_bios_init_start(PadBiosRaw* raw0, PadBiosRaw* raw1)
+{
+	/* Pin raw0 + raw1 to $a0 + $a1 via rgcc; the B(12h) call uses these directly.
+	 * The `(void)` casts mark them as unread after the call so the compiler doesn't need to move them back. */
+	register PadBiosRaw* p0 rgcc(R_A0) = raw0;
+	register PadBiosRaw* p1 rgcc(R_A1) = raw1;
+	(void)p0; (void)p1;
+
+	// TODO(Ed): Properly annotate the raw values in the inline asm instructions.
+	// Use enums.
+
+	/* B(12h) InitPAD2(raw0, 0x22, raw1, 0x22)
+	 *   $a0 = raw0 (rgcc-bound; survives the sequence below)
+	 *   $a1 = raw1 (preserved into $a2 before $a1 is overwritten)
+	 *   $a2 = raw1 (moved from $a1; survives $a1's overwrite)
+	 *   $a3 = 0x22 (immediate)
+	 *   $t1 = 0x12 (function number)
+	 *   $t2 = 0xB0 (BIOS B-table address) */
+	asm volatile(
+		asm_words(
+			or_u(    R_A2, R_A0, R_0),                 /* $a2 = $a1 = raw1 */
+			add_ui(  R_A1, R_0, bios_pad_buffer_size), /* $a1 = 0x22 */
+			add_ui(  R_A3, R_0, bios_pad_buffer_size), /* $a3 = 0x22 */
+			add_ui(  R_T1, R_0, bios_init_pad_2),      /* $t1 = 0x12 */
+			add_ui(  R_T2, R_0, bios_btable_addr),     /* $t2 = 0xB0 */
+			call_reg(R_T2),                            /* jalr $t2, $ra */
+			nop                                        /* BD slot */
+		)
+		asm_rpins, r_use(p0), r_use(p1)
+		asm_clobber: 
+			rlit(R_AT), 
+			rlit(R_V0), rlit(R_V1), 
+			rlit(R_T0), rlit(R_T1), rlit(R_T2), rlit(R_T3), rlit(R_T4),
+			rlit(R_T5), rlit(R_T6), rlit(R_T7), rlit(R_T8), rlit(R_T9),
+			rlit(R_RA),
+			clb_mem_drain
+	);
+
+	/* The C-level writes re-load the pointers via the parameter names and write 0xFF to each 
+	 * buffer's status byte to mark the initial-state hazard documented in kernelbios.md:1621-1624. */
+	u1_v(raw0)[0] = 0xFF;
+	u1_v(raw1)[0] = 0xFF;
+
+	/* B(13h) StartPAD2() — no args. The BIOS preserves $sp. */
+	asm volatile(
+		asm_words(
+			add_ui(  R_T1, R_0, bios_start_pad_2), /* $t1 = 0x13 */
+			add_ui(  R_T2, R_0, bios_btable_addr), /* $t2 = 0xB0 (re-load) */
+			call_reg(R_T2),                             /* jalr $t2, $ra */
+			nop                                           /* BD slot */
+		)
+		asm_clobber:
+			rlit(R_AT),
+			rlit(R_V0), rlit(R_V1),
+			rlit(R_T0), rlit(R_T1), rlit(R_T2), rlit(R_T3), rlit(R_T4),
+			rlit(R_T5), rlit(R_T6), rlit(R_T7), rlit(R_T8), rlit(R_T9),
+			rlit(R_RA),
+			clb_mem_drain
+	);
+}

code/duffle/pad.h

@@ -1,6 +1,7 @@
 #ifdef INTELLISENSE_DIRECTIVES
 #	pragma once
 #	include "dsl.h"
+#	include "math.h"
 #endif
 
 /* PSX button bit positions — 1:1 with PSX-SPX docs at docs/psx-spx/docs/controllersandmemorycards.md:405-421.
@@ -33,9 +34,6 @@ enum {
 	Pad1 = 1 << PadId_Offset,
 };
 
-#define pad0_(btn_id) (btn_id << Pad0)
-#define pad1_(btn_id) (btn_id << Pad1)
-
 /* =============================================================================
  * BIOS pad-buffer subsystem: docs/psx-spx/docs/kernelbios.md (B(12h) + B(13h))
  * ============================================================================= */
@@ -113,3 +111,5 @@ typedef Struct_(PadState) {
 		};
 	};
 };
+
+internal void pad_bios_init_start(PadBiosRaw* raw0, PadBiosRaw* raw1);

code/duffle/psyq.h

@@ -64,9 +64,9 @@ typedef Struct_(Tile) {
 	Linear Algebra
 */
 
-M3_S2* m3s2_rotation   (V3_S2* vec, M3_S2* mat) asm("RotMatrix");
-M3_S2* m3s2_translation(M3_S2* mat, V3_S4* vec) asm("TransMatrix");
-M3_S2* m3s2_scale      (M3_S2* mat, V3_S4* vec) asm("ScaleMatrix");
+MT3_S2S4* mt3s2s4_rotation   (V3_S2*    vec, MT3_S2S4* mat) asm("RotMatrix");
+MT3_S2S4* mt3s2s4_translation(MT3_S2S4* mat, V3_S4*    vec) asm("TransMatrix");
+MT3_S2S4* mt3s2s4_scale      (MT3_S2S4* mat, V3_S4*    vec) asm("ScaleMatrix");
 
 // Rotation, Translation, Perspective
 
@@ -99,5 +99,23 @@ FI_ S4 rtp_avg_nclip_a4_v3s2(
 	);
 }
 
-void gte_matrix_set_rotation   (M3_S2* mat) asm("SetRotMatrix");
-void gte_matrix_set_translation(M3_S2* mat) asm("SetTransMatrix");
+void gte_matrix_set_rotation   (MT3_S2S4* mat) asm("SetRotMatrix");
+void gte_matrix_set_translation(MT3_S2S4* mat) asm("SetTransMatrix");
+
+// Einheit, Metrication to unit vector. "Normalization", not Orthogonal "Normal, Normalis". Directionalization.
+// RGA(Lengyel): Normalize the bulk of a zero-weight direction. This is not finite-point unitization (which forces w=1).
+S4 normalize_v3s4(V3_S4* v0, V3_S4* v1) asm("VectorNormal");
+
+// RGA(Lengyel): Apply the matrix expansion of a rigid transformation.
+// Motor antiproduct is equivalent for unitized points; LA form is what GTE consumes.
+V3_S4* mul_m3s2_v3s4(MT3_S2S4* m, V3_S4* v, V3_S4* result) asm("ApplyMatrixLV");
+
+// RGA(Lengyel): Store the full translation column. The motor translator would store half this displacement in m.xyz.
+MT3_S2S4* trans_m3s2(MT3_S2S4* m, V3_S4* off) asm("TransMatrix");
+
+MT3_S2S4* gte_comp_coord_m3s2(MT3_S2S4* m0, MT3_S2S4* m1, MT3_S2S4* result) asm("CompMatrixLV");
+
+// RGA(Lengyel): Complement(Wedge(a,b)), i.e. the Euclidean 3D complement of the exterior product, stored as a V3_S4.
+// The underlying GTE OP is a specialized signed-16-bit D x IR command; the wedge interpretation is a 3D dual of the same 3 scalars.
+void cross_v3s4(V3_S4* v0, V3_S4* v1, V3_S4* result) asm("OuterProduct12");
+

code/duffle/word_count.metadata.h

@@ -15,6 +15,8 @@
 #define WORD_COUNT(name, count)  enum { words_##name = (count) };
 
 WORD_COUNT(nop,                              1)
+WORD_COUNT(atom_label,                        0)
+WORD_COUNT(atom_offset,                       0)
 WORD_COUNT(load_upper_i,                     1)
 WORD_COUNT(jump_reg,                         1)
 WORD_COUNT(jump_link,                        1)
@@ -54,6 +56,15 @@ WORD_COUNT(gte_sw,                           1)
 WORD_COUNT(gte_cmdw_rtpt,                    1)
 WORD_COUNT(gte_cmdw_nclip,                   1)
 WORD_COUNT(gte_avg_sort_z3,                  1)
+WORD_COUNT(gte_cmdw_sqr,                     1)
+WORD_COUNT(gte_cmdw_gpf,                     1)
+WORD_COUNT(shift_lleft_var,                  1)
+WORD_COUNT(shift_aright_var,                 1)
+WORD_COUNT(li_s,                             1)
+WORD_COUNT(and_i,                            1)
+WORD_COUNT(add_si,                           1)
+WORD_COUNT(branch_lt_zero,                   1)
+WORD_COUNT(sub_s,                            1)
 WORD_COUNT(sub_u,                            1)
 WORD_COUNT(nop2,                             2)
 

code/hello_camera/gen/auto_reg.h

@@ -0,0 +1,13 @@
+#ifdef INTELLISENSE_DIRECTIVES
+#pragma once
+#endif
+// Auto-generated by ps1_meta.lua (passes/auto_reg.lua) — DO NOT EDIT
+// Directory: C:\projects\Pikuma\ps1\code\hello_camera
+//   source: C:/projects/Pikuma/ps1/code/hello_camera/hello_camera.c
+//   source: C:/projects/Pikuma/ps1/code/hello_camera/hello_camera.h
+//   source: C:/projects/Pikuma/ps1/code/hello_camera/hello_camera.atom.c
+// Per-phase register allocations resolved by the lua pass.
+// R_<Sym>_Code = <chosen GPR's _Code constant> for every marker in this directory.
+
+#define R_GpTmp_Code R_V0_Code
+

code/hello_camera/gen/offsets.h

@@ -8,7 +8,7 @@
 #pragma region hello_camera
 
 
-// --- atom: pad_apply_input (60 words) ---
+// --- atom: pad_input_cube_rotation (60 words) ---
 
 #define _atom_offset_dpad_left_exit_dpad_left         6
 #define _atom_offset_dpad_right_exit_dpad_right       6
@@ -26,6 +26,24 @@ enum {
     atom_offset_end_low_exit_stick = _atom_offset_end_low_exit_stick,
 };
 
+// --- atom: pad_input_cam (40 words) ---
+
+#define _atom_offset_left_x_exit_left_x               3
+#define _atom_offset_right_x_exit_right_x             3
+#define _atom_offset_up_y_exit_up_y                   3
+#define _atom_offset_down_y_exit_down_y               3
+#define _atom_offset_cross_z_exit_cross_z             3
+#define _atom_offset_circle_z_exit_circle_z           3
+
+enum {
+    atom_offset_left_x_exit_left_x = _atom_offset_left_x_exit_left_x,
+    atom_offset_right_x_exit_right_x = _atom_offset_right_x_exit_right_x,
+    atom_offset_up_y_exit_up_y = _atom_offset_up_y_exit_up_y,
+    atom_offset_down_y_exit_down_y = _atom_offset_down_y_exit_down_y,
+    atom_offset_cross_z_exit_cross_z = _atom_offset_cross_z_exit_cross_z,
+    atom_offset_circle_z_exit_circle_z = _atom_offset_circle_z_exit_circle_z,
+};
+
 // --- atom: cube_g4_face (76 words) ---
 
 #define _atom_offset_cull_cube_g4_face_exit           41

code/hello_camera/hello_camera.atom.c

@@ -17,6 +17,7 @@
 #	include "duffle/psyq.atom.c"
 #		include "gen/offsets.h"
 #		include "gen/macs.h"
+#		include "gen/auto_reg.h"
 #	include "hello_camera.h"
 #endif
 
@@ -24,8 +25,8 @@ ATOM_FILE_DEBUGGER_LINE_MARKER(hello_joypad_atom_c);
 
 #pragma region MACs (Mips Atom components)
 
-FI_ Slice_MipsCode ac_put_disp_env(U4 reg_transfer, U4 reg_base, U2 port)
-MipsAtomComp_Proc_(ac_put_disp_env, {
+FI_ Slice_MipsCode ac_put_disp_env(AtomBuilder_R ab, U4 reg_transfer, U4 reg_base, U2 port)
+MipsAtomComp_Proc_(ac_put_disp_env, ab, {
 	// Emits 5 GP0 commands for buffer 0 (display_area = (0,0,320,240)).
 	// Sequence per libpsyx PutDispEnv: DrawArea TL → DrawArea BR → Mask → DrawArea TL → DrawArea BR
 	mac_gcmd_push(gp0_word_draw_area_top_left_origin,      reg_transfer, reg_base, port),
@@ -35,8 +36,8 @@ MipsAtomComp_Proc_(ac_put_disp_env, {
 	mac_gcmd_push(gp0_word_draw_area_bottom_right_320x240, reg_transfer, reg_base, port),
 })
 
-FI_ Slice_MipsCode ac_put_draw_env(U4 reg_transfer, U4 reg_base, U2 port)
-MipsAtomComp_Proc_(ac_put_draw_env, {
+I_ Slice_MipsCode ac_put_draw_env(AtomBuilder_R ab, U4 reg_transfer, U4 reg_base, U2 port)
+MipsAtomComp_Proc_(ac_put_draw_env, ab, {
 	/*
 	* ORIGIN: each code word corresponds to the EXACT value libpsyx's PutDrawEnv function would compute for the same DrawEnv settings.
 	* References:
@@ -50,18 +51,18 @@ MipsAtomComp_Proc_(ac_put_draw_env, {
 	*   (binary; the PutDrawEnv implementation builds the 16-word DR_ENV from the user's DRAWENV struct and emits it via GP0 GPU commands.)
 	*
 	* Word indices (libpsyx PutDrawEnv / SetDrawEnv order):
-	*   tag      = (length << 24) | addr                — 16-word packet (1 tag + 15 code)
-	*   code[0]  = DrawMode (dfe=1, dtd=0, tpage=0)     — must come first per libpsyx
-	*   code[1]  = TextureWindow (tw=(0,0))             — bare-cmd word; GPU uses current state
-	*   code[2]  = DrawArea top-left (clip.x=0, clip.y=240)
-	*   code[3]  = DrawArea bottom-right (clip.x+w=320, clip.y+h=480)
-	*   code[4]  = DrawOffset (ofs=(0,0))               — bare-cmd word
-	*   code[5]  = Mask (dtd=0, dfe=1, isbg=1)          — 0xE6 cmd + isbg bit
-	*   code[6]  = Initial-bg-color (isbg=1, r=7, g=7, b=7)
-	*   code[7]  = DrawMode (isbg=1, tpage=0)           — re-asserts DrawMode with isbg
-	*   code[8..10]  = padding (NOP)                    — 3 words to fill the packet
-	*   code[11..12] = TextureWindow bottom-right       — defaults to (0,0,0,0)
-	*   code[13..14] = padding (NOP)                    — completes the 16-word packet
+	*   tag          = (length << 24) | addr                — 16-word packet (1 tag + 15 code)
+	*   code[0]      = DrawMode (dfe=1, dtd=0, tpage=0)     — must come first per libpsyx
+	*   code[1]      = TextureWindow (tw=(0,0))             — bare-cmd word; GPU uses current state
+	*   code[2]      = DrawArea top-left (clip.x=0, clip.y=240)
+	*   code[3]      = DrawArea bottom-right (clip.x+w=320, clip.y+h=480)
+	*   code[4]      = DrawOffset (ofs=(0,0))               — bare-cmd word
+	*   code[5]      = Mask (dtd=0, dfe=1, isbg=1)          — 0xE6 cmd + isbg bit
+	*   code[6]      = Initial-bg-color (isbg=1, r=7, g=7, b=7)
+	*   code[7]      = DrawMode (isbg=1, tpage=0)           — re-asserts DrawMode with isbg
+	*   code[8..10]  = padding (NOP)                        — 3 words to fill the packet
+	*   code[11..12] = TextureWindow bottom-right           — defaults to (0,0,0,0)
+	*   code[13..14] = padding (NOP)                        — completes the 16-word packet
 	*/
 	mac_gcmd_push(gp0_dr_env_tag,                            reg_transfer, reg_base, port), /* tag (length=15 << 24, addr=0) — packet header for the DR_ENV sequence. The GPU needs this to recognize the next 15 words as a DR_ENV packet and trigger the isbg auto-clear. */
 	mac_gcmd_push(gp0_word_draw_mode_drawing_allowed,        reg_transfer, reg_base, port), /* code[0]  DrawMode (dfe=1, dtd=0, tpage=0) */
@@ -90,6 +91,528 @@ MipsAtomComp_Proc_(ac_put_draw_env, {
 
 #pragma endregion MACs
 
+#pragma region Atom Procs
+// Modular Atoms
+
+/* Scratchpad layout for the resolve_look_at bundle.
+ * The chain atoms communicate entirely via the wave-context GPR carrier R_ResolveScratch (R_T4) + hardcoded offsets into smem.scratchpad
+ * (PS1 hardware scratchpad at 0x1F800000).
+ *
+ * Atom 0 (input_and_sub) STAGES the C-side inputs (eye, up_in) into the scratchpad;
+ * AT THE SAME TIME it computes fwd = target - eye and stores it at scratch+0.
+ * Atoms 1-6 then read/write specific scratchpad offsets internally using
+ * `r_scratch + hardcoded_offset` — no tape-data pointers are passed between atoms.
+ *   +0   fwd   (atom 0 writes; atom  1 reads)
+ *   +16  uz    (atom 1 writes; atoms 2 + 4 read)
+ *   +32  right (atom 2 writes; atom  3 reads)
+ *   +48  ux    (atom 3 writes; atoms 4 + 6 read)
+ *   +64  up    (atom 4 writes; atom  5 reads)
+ *   +80  uy    (atom 5 writes; atom  6 reads)
+ *   +96  eye   (atom 0 stages from C-side pointer; atom 6 reads)
+ *   +128 up_in (atom 0 stages from C-side pointer; atom 2 reads)
+ */
+
+// enum {
+// 	R_LookAt    = R_T0 atom_reg atom_type(MT3_S2S4*),
+// 	R_CamEye    = R_T1 atom_reg atom_type(P3_S4*),
+// 	R_CamTarget = R_T2 atom_reg atom_type(P3_S4*),
+// 	R_WorldUp   = R_T3 atom_reg atom_type(V3_S4*),
+// };
+
+enum {
+	/* Wave-context GPR carrier for the resolve_look_at bundle: the scratch base.
+	* Set by atom 0 (popped from tape), read by atoms 1-6 (used as pointer base). */
+	R_ResolveScratch = R_T4 atom_reg atom_type(U4*),
+#define R_ResolveScratch_Code R_T4_Code
+};
+typedef Struct_(Binds_ResolveLookAt) {
+	MT3_S2S4* look_at;
+	P3_S4*    eye;
+	P3_S4*    target;
+	V3_S4*    up_in;
+};
+
+/* ─── ResolveLookAtScratch — offset schema for the resolve_look_at bundle's
+ * scratchpad slots (PS1 hardware scratchpad at 0x1F800000).
+ *
+ * Each slot is 16 bytes: V3_S4 is already 16 bytes (4 × S4 = x/y/z/pad).
+ * The struct fields are contiguous — slot i starts at offset i*16.
+ * Used by the assembly via O_(ResolveLookAtScratch, fld.x/y/z) which resolves to a compile-time byte offset.
+ * NOT a runtime struct — the struct is purely a schema for offsets; the assembly uses `r_scratch + O_(...)` to compute slot addresses at runtime.
+ *
+ * Slot producers/consumers (referenced by the resolve_look_at chain atoms):
+ *   +0    fwd    0 writes (target - eye);     atom  1 (normalize) reads
+ *   +16   uz     1 writes (normalize fwd);    atoms 2 + 4 read (cross operands)
+ *   +32   right  2 writes (cross uz x up_in); atom  3 (normalize) reads
+ *   +48   ux     3 writes (normalize right);  atoms 4 + 6 read
+ *   +64   up     4 writes (cross uz x ux);    atom  5 (normalize) reads
+ *   +80   uy     5 writes (normalize up);     atom  6 reads
+ *   +96   eye    0 stages (C-side input);     atom  6 reads (translation column)
+ *   +112  target reserved (currently written nowhere — kept for symmetry w/ eye)
+ *   +128  up_in  0 stages (C-side input); atom 2 reads (cross operand)
+ *
+ * Fields use P3_S4 (point) for eye/target (RGA: affine point, implicit weight 1);
+ * V3_S4 (vector) for fwd/uz/right/ux/up/uy/up_in (RGA: Euclidean vector).
+ * P3_S4 is a storage alias of V3_S4 (see math.h comment: "Storage alias of V3_S4.
+ * Use P3_S4 when the value is a point.") — both are 16 bytes.
+ */
+typedef Struct_(ResolveLookAtScratch) {
+	V3_S4 fwd;       /* offset  +0  (16 bytes — 4 S4 fields incl. internal pad) */
+	V3_S4 uz;        /* offset +16 (16 bytes) */
+	V3_S4 right;     /* offset +32 (16 bytes) */
+	V3_S4 ux;        /* offset +48 (16 bytes) */
+	V3_S4 up;        /* offset +64 (16 bytes) */
+	V3_S4 uy;        /* offset +80 (16 bytes) */
+	P3_S4 eye;       /* offset +96 (16 bytes; storage alias of V3_S4) */
+	P3_S4 target;    /* offset +112 (16 bytes; storage alias of V3_S4) */
+	V3_S4 up_in;     /* offset +128 (16 bytes) */
+};
+
+/* ─── resolve_look_at bundle chain atoms ────────────────────────────
+ * 4 unique atom procs in the resolve_look_at bundle (4 chain atoms + 3 calls to generic normalize_v3s4_proc).
+ * All 4 chain atoms are runtime-built MipsAtom_Proc_ atoms: each function declares a static MipsCode[] body, 
+ * then calls atombuilder_unroll() to append it to the caller's MipsAtomBuilder arena. resolve_look_at_init() 
+ * uses this pattern to pre-build the bundle into the static arena (smem.resolve_look_at_arena).
+ *
+ * Atom roster:
+ *	0: resolve_look_at__input_and_sub              (chain atom)
+ *	1: normalize_v3s4_proc (gte.atom.c)            (generic normalize; called for fwd→uz)
+ *	2: resolve_look_at__cross_uz_up_in_to_right    (chain atom)
+ *	3: normalize_v3s4_proc (gte.atom.c)            (generic normalize; called for right→ux)
+ *	4: resolve_look_at__cross_uz_ux_to_up          (chain atom)
+ *	5: normalize_v3s4_proc (gte.atom.c)            (generic normalize; called for up→uy)
+ *	6: resolve_look_at__populate_and_translate     (chain atom)
+ *
+ * The generic normalize_v3s4_proc is a parameterized 4-stage GTE normalize (SQR → mfc2 → LZCS → GPF → srav);
+ * it accepts scratch base + offset args so any caller (with a scratch base + struct schema) can use it.
+ */
+
+typedef Struct_(Binds_ResolveLookAtSub) {
+	P3_S4* target;  /* U4 (C-side P3_S4* — read by atom 0 directly; NOT a scratchpad address) */
+	P3_S4* eye;     /* U4 (C-side P3_S4* — read by atom 0 directly; staged into scratchpad by atom 0) */
+	V3_S4* up_in;   /* U4 (C-side V3_S4* — read by atom 0 directly; staged into scratchpad by atom 0) */
+	ResolveLookAtScratch* scratchpad;
+};
+
+/* Atom 0 in the bundle: input_and_sub. Stages C-side inputs into the scratchpad and computes fwd = target - eye.
+ * Staging work:
+ *   * Stage eye.x/y/z   → scratch (for atom 6's translation column)
+ *   * Stage up_in.x/y/z → scratch (for atom 2's outer-product operand)
+ *   * Compute fwd = target - eye, store fwd.x/y/z → scratch+0/+4/+8 (for atom 1)
+ * GPR codes (assigned by resolve_look_at_init):
+ *   r_target_ptr : R_T0
+ *   r_eye_ptr    : R_T1
+ *   r_up_in_ptr  : R_T2
+ *   r_scratch    : R_T4 (R_ResolveScratch; wave-context carrier)
+ *   r_tmp0       : R_T3 (stage eye/up_in + load eye.y)
+ *   r_tmp1       : R_T5 (stage eye/up_in + load eye.z)
+ *   r_tmp2       : R_T6 (stage eye/up_in + load target.x)
+ *   r_tmp3       : R_T7 (stage eye/up_in + load target.y)
+ *   R_AT         : hardcoded (load eye.y / eye.z / target.z)
+ *   R_V0         : hardcoded (load eye.z / target.z)
+ * Pool cost: 8 GPRs + R_T4 (carrier) + R_AT + R_V0 (hardcoded) = 11 GPRs.
+ */
+internal MipsAtom* resolve_look_at__input_and_sub_proc(AtomArena_R aa,	
+			// TODO(Ed): We can resolve scratch at anytime its fixed to a specific address.
+			U4 r_scratch
+	,	U4 r_target_ptr,U4 r_eye_ptr, U4 r_up_in_ptr
+	,	U4 r_tmp0,      U4 r_tmp1,    U4 r_tmp2, U4 r_tmp3
+) MipsAtom_Proc_(resolve_look_at__input_and_sub, aa, {
+	load_word(r_target_ptr, R_TapePtr, O_(Binds_ResolveLookAtSub,target)),
+	load_word(r_eye_ptr,    R_TapePtr, O_(Binds_ResolveLookAtSub,eye)),
+	load_word(r_up_in_ptr,  R_TapePtr, O_(Binds_ResolveLookAtSub,up_in)),
+	load_word(r_scratch,    R_TapePtr, O_(Binds_ResolveLookAtSub,scratchpad)),
+	add_ui_self(            R_TapePtr, S_(Binds_ResolveLookAtSub)),
+
+	// Stage eye.x/y/z into the scratchpad (atom 6 reads these for the translation column).
+	mac_load_p3s4( r_tmp0, r_tmp1, r_tmp2, r_eye_ptr, 0),
+	mac_store_p3s4(r_tmp0, r_tmp1, r_tmp2, r_scratch, O_(ResolveLookAtScratch,eye)),
+
+	/* Stage up_in.x/y/z into the scratchpad. */
+	mac_load_p3s4( r_tmp0, r_tmp1, r_tmp2, r_up_in_ptr, 0),
+	mac_store_p3s4(r_tmp0, r_tmp1, r_tmp2, r_scratch, O_(ResolveLookAtScratch,up_in)),
+
+	/* Compute fwd = target - eye. */
+	mac_load_p3s4(r_tmp0, r_tmp1, r_tmp2, r_target_ptr, 0),
+	mac_load_p3s4(r_tmp3, R_AT, R_V0, r_eye_ptr, 0),
+	mac_sub_v3s4(
+		r_tmp0, r_tmp1, r_tmp2,
+		r_tmp3, R_AT,   R_V0),
+	mac_store_v3s4(r_tmp0, r_tmp1, r_tmp2, r_scratch, O_(ResolveLookAtScratch,fwd)),
+
+	mac_yield()
+})
+
+/* Atoms 2 + 4 in the bundle: out = a × b (GTE outer product on IR/D vectors).
+ * No bind pop — the three operand pointers (a, b, out) are derived in-body from r_scratch + hardcoded_offset.
+ * Each atom has its own variant because the offsets are baked into the body and each atom uses unique GPRs.
+ *
+ * GTE register layout (per PSX-SPX + duffle gte.h):
+ *   IR1/2/3  = a.x/y/z    (mtc2)
+ *   VXY0     = b.x        (mtc2)
+ *   VZ0      = b.y        (mtc2)
+ *   VXY1     = b.z        (mtc2)
+ *   OP       = outer product
+ *   MAC1/2/3 = out.x/y/z  (mfc2)
+ *
+ * Pool cost: r_scratch (R_T4 carrier) + 7 body GPRs + R_AT + R_V0 (hardcoded) = 10 GPRs.
+ */
+
+/* Atom 2: cross uz × up_in → right. */
+internal MipsAtom* resolve_look_at__cross_uz_up_in_to_right_proc(AtomArena_R aa, U4 r_scratch
+	,	U4 r_a, U4 r_b, U4 r_c /* load a.x/y/z; result out.x/y/z */
+	,	U4 r_d                 /* load b.x */
+	,	U4 r_f, U4 r_g, U4 r_h /* r_f = &right (out ptr), r_g = &uz, r_h = &up_in */
+) MipsAtom_Proc_(resolve_look_at__cross_uz_up_in_to_right, aa, {
+	/* FIX: build packed RT22+RT33 with proper sign extension. */
+	add_si(r_g, r_scratch, O_(ResolveLookAtScratch,uz)),    /* r_g = &uz */
+	add_si(r_h, r_scratch, O_(ResolveLookAtScratch,up_in)), /* r_h = &up_in */
+	add_si(r_f, r_scratch, O_(ResolveLookAtScratch,right)), /* r_f = &right (out) */
+	nop,
+
+	/* Load a (uz).x/y/z into r_a/r_b/r_c. */
+	load_word(r_a, r_g, O_(V3_S4,x)),
+	load_word(r_b, r_g, O_(V3_S4,y)),
+	load_word(r_c, r_g, O_(V3_S4,z)),
+	nop,
+
+	/* Load b (up_in).x/y/z into r_d + R_AT/R_V0 (R_AT/R_V0 are hardcoded scratch). */
+	load_word(r_d,  r_h, O_(V3_S4,x)),
+	load_word(R_AT, r_h, O_(V3_S4,y)),
+	load_word(R_V0, r_h, O_(V3_S4,z)),
+	nop,
+
+	/* Save the two RT control-register slots OP will clobber. We reuse
+	 * r_g/r_h (scratch pointers, no longer needed) as the save targets. */
+	gte_mv_from_ctrl_r(r_g, gte_cr_RT11),    /* r_g = C2 r0 (RT11|RT12) */
+	gte_mv_from_ctrl_r(r_h, gte_cr_RT22),    /* r_h = C2 r4 (RT22|RT33) */
+
+	/* Load uz.x/uz.y/uz.z into COP2 control registers.
+	 * OP reads D1 = RT11 from $0.low, D2 = RT22 from $2.high, D3 = RT33 from $4.high.
+	 * RT22 is in BOTH $2.high AND $4.low (shared bit position). OP reads from $2.high.
+	 * So set RT22 via ctc2 r_b, $2 (sets $2.high = a.y.high = RT22, $2.low = a.y.low = RT13).
+	 * Then set RT33 via ctc2 r_c, $4 (sets $4.high = a.z.high = RT33, $4.low = a.z.low).
+	 * The $2 and $4 writes don't clobber each other (separate registers).
+	 * The 2nd ctc2 DOES clobber $4.low (becomes a.z.low, NOT a.y.high), but since OP
+	 * reads RT22 from $2.high (which the 2nd ctc2 doesn't touch), D2 is still a.y.high.
+	 * This is libpsyx's OuterProduct12 convention EXACTLY. */
+	gte_mv_to_ctrl_r(r_b, gte_cr_RT13),    /* $2 = r_b = a.y. RT13=a.y.low, RT22=a.y.high. */
+	gte_mv_to_ctrl_r(r_c, gte_cr_RT22),    /* $4 = r_c = a.z. RT22=a.z.low, RT33=a.z.high. */
+
+	/* Load uz into the RT diagonal. */
+	gte_mv_to_ctrl_r(r_a, gte_cr_RT11),   /* D1 = RT11 = uz.x (low 16 of $0, sign-extended by OP). */
+	nop2,                                 /* CTC2 retirement (CPU→COP2 2-slot delay) */
+
+	/* Load up_in into IR (the second operand for OP). */
+	gte_mv_to_data_r(r_d,  C2_IR1),       /* IR1 = up_in.x */
+	gte_mv_to_data_r(R_AT, C2_IR2),       /* IR2 = up_in.y */
+	gte_mv_to_data_r(R_V0, C2_IR3),       /* IR3 = up_in.z */
+	nop2,                                 /* MTC2 retirement (CPU→COP2 2-slot delay) */
+
+	gte_cmdw_outer_product, /* OP: MAC1/2/3 = uz × up_in
+		*   MAC1 = IR3*D2 - IR2*D3 = up_in.z*uz.y.high - up_in.y*uz.z.high
+		*   MAC2 = IR1*D3 - IR3*D1 = up_in.x*uz.z.high - up_in.z*uz.x
+		*   MAC3 = IR2*D1 - IR1*D2 = up_in.y*uz.x - up_in.x*uz.y.high
+		* For up_in = (0, -fp_one, 0):
+		*   MAC1 = 0 - (-fp_one)*uz.z.high = fp_one*uz.z.high
+		*   MAC2 = 0 - 0 = 0
+		*   MAC3 = (-fp_one)*uz.x - 0 = -fp_one*uz.x */
+
+	/* Restore the RT slots we clobbered. */
+	gte_mv_to_ctrl_r(r_g, gte_cr_RT11),   /* restore C2 r0 (RT11|RT12) */
+	gte_mv_to_ctrl_r(r_h, gte_cr_RT22),   /* restore C2 r4 (RT22|RT33) */
+
+	/* mfc2 MAC1/2/3 → r_a/r_b/r_c (out.x/y/z). */
+	gte_mv_from_data_r(r_a, C2_MAC1),
+	gte_mv_from_data_r(r_b, C2_MAC2),
+	gte_mv_from_data_r(r_c, C2_MAC3),
+	nop,  /* MFC2 retirement */
+
+	/* Right-shift MAC by 12 to convert from GTE's S12.20 fixed-point scale back to libpsyx OuterProduct12 convention (S12.0, fp_one=4096=1<<12).
+	 * Without this, MAC values (~16M for unit-vector cross products) overflow the GTE's 16-bit IR registers when atom 3 normalizes via mtc2. */
+	shift_aright(r_a, r_a, 12),
+	shift_aright(r_b, r_b, 12),
+	shift_aright(r_c, r_c, 12),
+
+	/* Store out.x/y/z to r_f (out ptr = scratch+32). */
+	store_word(r_a, r_f, O_(V3_S4,x)),
+	store_word(r_b, r_f, O_(V3_S4,y)),
+	store_word(r_c, r_f, O_(V3_S4,z)),
+
+	mac_yield()
+})
+
+/* Atom 4: cross uz × ux → up. */
+internal MipsAtom* resolve_look_at__cross_uz_ux_to_up_proc(AtomArena_R aa,	U4 r_scratch
+	,	U4 r_a, U4 r_b, U4 r_c /* load a.x/y/z; result out.x/y/z */
+	,	U4 r_d                 /* load b.x */
+	,	U4 r_f, U4 r_g, U4 r_h /* r_f = &up (out ptr), r_g = &uz, r_h = &ux */
+) MipsAtom_Proc_(resolve_look_at__cross_uz_ux_to_up, aa, {
+	/* Compute the three scratch pointers from r_scratch. */
+	add_si(r_g, r_scratch, O_(ResolveLookAtScratch,uz)), /* r_g = &uz */
+	add_si(r_h, r_scratch, O_(ResolveLookAtScratch,ux)), /* r_h = &ux */
+	add_si(r_f, r_scratch, O_(ResolveLookAtScratch,up)), /* r_f = &up (out) */
+	nop,
+
+	/* Load a (uz).x/y/z into r_a/r_b/r_c. */
+	load_word(r_a, r_g, O_(V3_S4,x)),
+	load_word(r_b, r_g, O_(V3_S4,y)),
+	load_word(r_c, r_g, O_(V3_S4,z)),
+	nop,
+
+	/* Load b (ux).x/y/z into r_d + R_AT/R_V0. */
+	load_word(r_d,  r_h, O_(V3_S4,x)),
+	load_word(R_AT, r_h, O_(V3_S4,y)),
+	load_word(R_V0, r_h, O_(V3_S4,z)),
+	nop,
+
+	/* OP reads D1/D2/D3 from RT11/RT22/RT33 ($0/$2/$4), not V0/V1/V2.
+	 * Mirror atom 1: cfc2 RT save, ctc2 RT diagonal from uz, mtc2 IR from ux,
+	 * ctc2 RT restore. */
+
+	/* Save the two RT control-register slots OP will clobber (reusing
+	 * r_g/r_h — they're no longer needed as scratch pointers). */
+	gte_mv_from_ctrl_r(r_g, gte_cr_RT11),    /* r_g = C2 $0 (RT11|RT12) */
+	gte_mv_from_ctrl_r(r_h, gte_cr_RT22),    /* r_h = C2 $4 (RT22|RT33) */
+
+	/* Load uz into the RT diagonal — same packing as atom 1.
+	 * OP reads D1 = RT11 from $0.low, D2 = RT22 from $2.high, D3 = RT33 from $4.high.
+	 * RT22 is shared between $2.high and $4.low — the ctc2 sequence to $2 then $4
+	 * sets RT22 to uz.y.high (via $2), then to uz.z.low (via $4). OP reads
+	 * RT22 from $2.high which the second ctc2 doesn't touch, so D2 stays uz.y.high.
+	 * (This is libpsyx OuterProduct12 convention EXACTLY.) */
+	gte_mv_to_ctrl_r(r_b, gte_cr_RT13),    /* $2 = uz.y. RT13=uz.y.low, RT22=uz.y.high. */
+	gte_mv_to_ctrl_r(r_c, gte_cr_RT22),    /* $4 = uz.z. RT22=uz.z.low, RT33=uz.z.high. */
+	gte_mv_to_ctrl_r(r_a, gte_cr_RT11),   /* $0 = uz.x. RT11=uz.x. */
+	nop2,                                 /* CTC2 retirement (CPU→COP2 2-slot delay) */
+
+	/* Load ux into the IR registers (the second operand for OP). */
+	gte_mv_to_data_r(r_d,  C2_IR1),       /* IR1 = ux.x */
+	gte_mv_to_data_r(R_AT, C2_IR2),       /* IR2 = ux.y */
+	gte_mv_to_data_r(R_V0, C2_IR3),       /* IR3 = ux.z */
+	nop2,                                 /* MTC2 retirement (CPU→COP2 2-slot delay) */
+
+	gte_cmdw_outer_product,
+
+	/* Restore the RT slots we clobbered. */
+	gte_mv_to_ctrl_r(r_g, gte_cr_RT11),   /* restore C2 $0 (RT11|RT12) */
+	gte_mv_to_ctrl_r(r_h, gte_cr_RT22),   /* restore C2 $4 (RT22|RT33) */
+
+	gte_mv_from_data_r(r_a, C2_MAC1),
+	gte_mv_from_data_r(r_b, C2_MAC2),
+	gte_mv_from_data_r(r_c, C2_MAC3),
+	nop,
+	/* Right-shift MAC by 12 to convert from GTE's S12.20 scale back to libpsyx
+	 * OuterProduct12 convention (S12.0, fp_one=4096). See atom 1 for rationale. */
+	shift_aright(r_a, r_a, 12),
+	shift_aright(r_b, r_b, 12),
+	shift_aright(r_c, r_c, 12),
+	store_word(r_a, r_f, O_(V3_S4,x)),
+	store_word(r_b, r_f, O_(V3_S4,y)),
+	store_word(r_c, r_f, O_(V3_S4,z)),
+
+	mac_yield()
+})
+
+typedef Struct_(Binds_ResolveLookAtPopAndTrans) {
+	U4 look_at;  /* U4 (MT3_S2S4* — destination matrix address) */
+};
+/* Atom 6 in the bundle: write look_at->m[][] from ux/uy/uz, then compute the translation column t[] = R * (-eye).
+ *
+ * GPR codes (assigned by resolve_look_at_init):
+ *   r_look_at   : MT3_S2S4* (popped from tape; output matrix destination)
+ *   r_pux       : pointer to ux   (offset O_(ResolveLookAtScratch,ux))
+ *   r_puy       : pointer to uy   (offset O_(ResolveLookAtScratch,uy))
+ *   r_puz       : pointer to uz   (offset O_(ResolveLookAtScratch,uz))
+ *   r_peye      : pointer to eye  (offset O_(ResolveLookAtScratch,eye))
+ *   r_tmp0/1/2  : atom-local scratch (load + MVMVA + store temps)
+ *
+ * 4 pointer regs (r_pux/r_puy/r_puz/r_peye) are DEDICATED — they hold the scratch addresses for the entire body.
+ * They are computed in-body via `add_si(r_px, r_scratch, O_(ResolveLookAtScratch, field))` so no tape-data pointer is needed.
+ *
+ * Struct layout (per duffle/math.h):
+ *   MT3_S2S4 { A3x3_S2 m; A3_S4 t; }  →  m[][] is S2 packed (9 × 2 = 18 bytes at offset 0) 
+ *                                        t[0/1/2] is S4     (3 × 4 = 12 bytes at offset 18)
+ *
+ * Translation column: GTE MVMVA with the world rotation matrix pre-set
+ * (helper emits set_gte_world before the bundle, per the bundle design).
+ * MVMVA computes R * pos (with cv=0/mx=0/sf=0/v=0); MAC1/2/3 = R * (-eye).
+ * Pool cost: r_look_at (1) + r_scratch (R_T4 carrier) + 4 ptr regs + 3 tmp regs = 9 GPRs.
+ */
+internal MipsAtom* resolve_look_at__populate_proc(AtomArena_R aa
+	,	U4 r_look_at
+	,	U4 r_scratch
+	,	U4 r_pux, U4 r_puy, U4 r_puz
+	,	U4 r_tmp0, U4 r_tmp1, U4 r_tmp2
+) MipsAtom_Proc_(resolve_look_at__populate, aa, {
+	/* Pop look_at* (the matrix output) — advance R_TapePtr by 4 bytes. */
+	load_word(r_look_at, R_TapePtr, O_(Binds_ResolveLookAtPopAndTrans,look_at)),
+	add_ui_self(         R_TapePtr, S_(Binds_ResolveLookAtPopAndTrans)),
+
+	/* Compute the 3 scratch pointers in their dedicated GPRs (eye isn't needed by 6a — 6b reads it). */
+	add_si(r_pux, r_scratch, O_(ResolveLookAtScratch,ux)),  /* r_pux = &ux */
+	add_si(r_puy, r_scratch, O_(ResolveLookAtScratch,uy)),  /* r_puy = &uy */
+	add_si(r_puz, r_scratch, O_(ResolveLookAtScratch,uz)),  /* r_puz = &uz */
+	nop,
+
+	/* ── m[0] = (S2)ux ── */
+	load_word(r_tmp0, r_pux, O_(V3_S4,x)),
+	load_word(r_tmp1, r_pux, O_(V3_S4,y)),
+	load_word(r_tmp2, r_pux, O_(V3_S4,z)),
+	nop,
+	store_half(r_tmp0, r_look_at, O_(MT3_S2S4,m[0][0])),
+	store_half(r_tmp1, r_look_at, O_(MT3_S2S4,m[0][1])),
+	store_half(r_tmp2, r_look_at, O_(MT3_S2S4,m[0][2])),
+
+	/* ── m[1] = (S2)uy ── */
+	load_word(r_tmp0, r_puy, O_(V3_S4,x)),
+	load_word(r_tmp1, r_puy, O_(V3_S4,y)),
+	load_word(r_tmp2, r_puy, O_(V3_S4,z)),
+	nop,
+	store_half(r_tmp0, r_look_at, O_(MT3_S2S4,m[1][0])),
+	store_half(r_tmp1, r_look_at, O_(MT3_S2S4,m[1][1])),
+	store_half(r_tmp2, r_look_at, O_(MT3_S2S4,m[1][2])),
+
+	/* ── m[2] = (S2)uz ── */
+	load_word(r_tmp0, r_puz, O_(V3_S4,x)),
+	load_word(r_tmp1, r_puz, O_(V3_S4,y)),
+	load_word(r_tmp2, r_puz, O_(V3_S4,z)),
+	nop,
+	store_half(r_tmp0, r_look_at, O_(MT3_S2S4,m[2][0])),
+	store_half(r_tmp1, r_look_at, O_(MT3_S2S4,m[2][1])),
+	store_half(r_tmp2, r_look_at, O_(MT3_S2S4,m[2][2])),
+
+	/* Zero t[0..2] — atom 6c writes the final values here. */
+	store_word(R_0, r_look_at, O_(MT3_S2S4,t[0])),
+	store_word(R_0, r_look_at, O_(MT3_S2S4,t[1])),
+	store_word(R_0, r_look_at, O_(MT3_S2S4,t[2])),
+
+	mac_yield()
+})
+
+/* Atom 6b in the bundle: matrix-vector product off = R * (-eye) >> 12.
+ * Uses RTPS with V0 loaded from scratch via lwc2. The RT matrix is
+ * pre-loaded by atom 6a.5 (resolve_look_at__load_rt).
+ * Stores off to scratch+96 (overwriting the packed pos).
+ *
+ * GPR codes (assigned by resolve_look_at_init):
+ *   r_scratch : R_ResolveScratch (R_T4) — scratch base
+ *   r_peye    : pointer to eye (slot +96, reused as off destination)
+ *   r_tmp0/1/2: -eye + GTE transfer scratch
+ *
+ * Pool cost: r_scratch (carrier) + 1 ptr reg + 3 tmp regs = 5 GPRs.
+ */
+internal MipsAtom* resolve_look_at__matrix_vector_proc(AtomArena_R aa
+	,	U4 r_scratch
+	,	U4 r_peye
+	,	U4 r_look_at
+	,	U4 r_tmp0, U4 r_tmp1, U4 r_tmp2
+) MipsAtom_Proc_(resolve_look_at__matrix_vector, aa, {
+	/* === EXACT C11 ApplyMatrixLV replication ===
+	 * The C11 does:
+	 *   1. ctc2 RT matrix (5 ctc2s to C2[0..4])
+	 *   2. lw v.x/y/z from memory
+	 *   3. S15 decomposition (negu + sra 15 + negu + andi 0x7FFF + negu)
+	 *   4. mtc2 HIGH bits to IR1/2/3, nop, MVMVA pass1 (sf=0, mx=0, v=3, cv=3)
+	 *   5. mfc2 MACs
+	 *   6. mtc2 LOW bits to IR1/2/3, nop, MVMVA pass2 (sf=1, mx=0, v=3, cv=3)
+	 *   7. mfc2 MACs
+	 *   8. Combine: (pass1 << 3) + pass2
+	 *
+	 * For S16-fitting pos (|pos| < 32768), pos >> 15 = 0, so pass1 = 0.
+	 * The combine simplifies: result = 0 + pass2 = pass2.
+	 * So we skip the S15 decomposition and just do pass 2 directly.
+	 * We still use v=3 (IR input) and mx=0 (RT matrix) like the C11. */
+
+	/* Pop look_at* from tape. */
+	load_word(r_look_at, R_TapePtr, O_(Binds_ResolveLookAtPopAndTrans,look_at)),
+	add_ui_self(         R_TapePtr, S_(Binds_ResolveLookAtPopAndTrans)),
+
+	/* r_peye = &eye (slot +96, reused as off destination). */
+	add_si(r_peye, r_scratch, O_(ResolveLookAtScratch,eye)),
+	nop,
+
+	/* === Load RT matrix from look_at into C2[0..4] via ctc2 ===
+	 * Exact s  ame sequence as set_gte_mt3s2s4 / C11's ApplyMatrixLV. */
+	load_word(  r_tmp0, r_look_at,  0), nop, gte_mv_to_ctrl_r(r_tmp0, gte_cr_RT11),
+	load_word(  r_tmp0, r_look_at,  4), nop, gte_mv_to_ctrl_r(r_tmp0, gte_cr_RT12),
+	load_word(  r_tmp0, r_look_at,  8), nop, gte_mv_to_ctrl_r(r_tmp0, gte_cr_RT13),
+	load_word(  r_tmp0, r_look_at, 12), nop, gte_mv_to_ctrl_r(r_tmp0, gte_cr_RT21),
+	load_half_u(r_tmp0, r_look_at, 16), nop, gte_mv_to_ctrl_r(r_tmp0, gte_cr_RT22),
+	nop2,  /* CTC2 retirement (2 slots × 5 ctc2s) */
+
+	/* Load pos = -eye after the matrix load releases r_tmp0. */
+	load_word(r_tmp0, r_peye, O_(P3_S4,x)),
+	load_word(r_tmp1, r_peye, O_(P3_S4,y)),
+	load_word(r_tmp2, r_peye, O_(P3_S4,z)),
+	nop,
+	sub_u(r_tmp0, R_0, r_tmp0),  /* pos.x = -eye.x */
+	sub_u(r_tmp1, R_0, r_tmp1),
+	sub_u(r_tmp2, R_0, r_tmp2),
+
+	/* === mtc2 pos (as S16) to IR1/2/3 ===
+	 * The GTE takes low 16 bits. pos fits in S16. For negative pos, the
+	 * 32-bit sign-extended value's low 16 bits = correct S16. */
+	/* Mask pos to 16 bits to be safe. For S16-fitting pos, pos & 0xFFFF
+	 * gives the correct S16 value (sign bit preserved). */
+	/* r_tmp0/1/2 already have pos values. */
+	gte_mv_to_data_r(r_tmp0, C2_IR1),
+	gte_mv_to_data_r(r_tmp1, C2_IR2),
+	gte_mv_to_data_r(r_tmp2, C2_IR3),
+	nop2,  /* MTC2 retirement (2 slots) */
+
+	/* === MVMVA pass 2 EXACT C11 command: 0x4A49E012 ===
+	 * sf=1, mx=0 (RT), v=3 (IR), cv=3. Reads RT × IR >> 12. */
+	gte_cmdw_mvmva_c11_pass2_exact,
+	nop,  /* GTE interlock */
+
+	/* === mfc2 MAC1/2/3 → r_tmp0/1/2 === */
+	gte_mv_from_data_r(r_tmp0, C2_MAC1),
+	gte_mv_from_data_r(r_tmp1, C2_MAC2),
+	gte_mv_from_data_r(r_tmp2, C2_MAC3),
+	nop,
+
+	/* === Store off → scratch+96 (overwriting pos) === */
+	store_word(r_tmp0, r_peye, O_(V3_S4,x)),
+	store_word(r_tmp1, r_peye, O_(V3_S4,y)),
+	store_word(r_tmp2, r_peye, O_(V3_S4,z)),
+
+	mac_yield()
+})
+
+/* Atom 6c in the bundle: copy scratch+96 (off, written by atom 6b) → look_at->t[].
+ * Uses mac_trans_matrix component (m->t = v, libgte TransMatrix semantics = struct copy).
+ *
+ * GPR codes (assigned by resolve_look_at_init):
+ *   r_look_at : MT3_S2S4* (popped from tape; output matrix destination)
+ *   r_scratch : R_ResolveScratch (R_T4) — scratch base
+ *   r_off_ptr : pointer to off (= &scratch.eye, reused slot)
+ *   r_tmp0    : transfer reg for mac_trans_matrix
+ *
+ * Pool cost: r_look_at (1) + r_scratch (carrier) + r_off_ptr + 1 clobber = 4 GPRs.
+ */
+I_ MipsAtom* resolve_look_at__trans_matrix_proc(AtomArena_R aa
+	,	U4 r_look_at
+	,	U4 r_scratch
+	,	U4 r_off_ptr
+	,	U4 r_tmp0
+) MipsAtom_Proc_(resolve_look_at__trans_matrix, aa, {
+	/* Pop look_at* from tape. */
+	load_word(r_look_at, R_TapePtr, O_(Binds_ResolveLookAtPopAndTrans,look_at)),
+	add_ui_self(         R_TapePtr, S_(Binds_ResolveLookAtPopAndTrans)),
+
+	/* r_off_ptr = &off (= &scratch.eye since atom 6b overwrote eye with off). */
+	add_si(r_off_ptr, r_scratch, O_(ResolveLookAtScratch,eye)),
+	nop,
+
+	/* Copy off → look_at.t[] (mac_trans_matrix: m->t = v). */
+	mac_trans_matrix(r_look_at, r_off_ptr, r_tmp0),
+
+	mac_yield()
+})
+
+#pragma endregion Atom Procs
+
 #pragma region Baked Atoms
 
 enum {
@@ -106,111 +629,111 @@ internal MipsAtom_(screen_env_init) atom_info(atom_phase(screen_init)
 	/* display[0] = (0, 0, 320, 240); rest of struct zeroed. */
 	add_ui(R_ScreenX, R_0, ScreenRes_X), add_ui(R_ScreenY, R_0, ScreenRes_Y),
 	mac_store_v2s2(R_ScreenX, R_ScreenY, R_ScreenBuf, O_(DisplayEnv,display_area.width) + OA_(DoubleBuffer,display,0)),
-	store_word(R_0, R_ScreenBuf, O_(DisplayEnv,display_area) + OA_(DoubleBuffer,display,0)),
-	store_word(R_0, R_ScreenBuf, O_(DisplayEnv,screen)       + OA_(DoubleBuffer,display,0)),
-	store_word(R_0, R_ScreenBuf, O_(DisplayEnv,vinterlace)   + OA_(DoubleBuffer,display,0)),
+	store_word(R_0, R_ScreenBuf, O_(DisplayEnv,display_area) + O_(DoubleBuffer,display[0])),
+	store_word(R_0, R_ScreenBuf, O_(DisplayEnv,screen)       + O_(DoubleBuffer,display[0])),
+	store_word(R_0, R_ScreenBuf, O_(DisplayEnv,vinterlace)   + O_(DoubleBuffer,display[0])),
 
 	/* display[1] = (0, 240, 320, 240); rest of struct zeroed. */
-	mac_store_rects2(R_0, R_ScreenY, R_ScreenX, R_ScreenY, R_ScreenBuf, O_(DisplayEnv,display_area) + OA_(DoubleBuffer,display,1)),
-	store_word(R_0, R_ScreenBuf, O_(DisplayEnv,screen)     + OA_(DoubleBuffer,display,1)),
-	store_word(R_0, R_ScreenBuf, O_(DisplayEnv,vinterlace) + OA_(DoubleBuffer,display,1)),
+	mac_store_rects2(R_0, R_ScreenY, R_ScreenX, R_ScreenY, R_ScreenBuf, O_(DisplayEnv,display_area) + O_(DoubleBuffer,display[1])),
+	store_word(R_0, R_ScreenBuf, O_(DisplayEnv,screen)     + O_(DoubleBuffer,display[1])),
+	store_word(R_0, R_ScreenBuf, O_(DisplayEnv,vinterlace) + O_(DoubleBuffer,display[1])),
 
-	mac_store_rects2(R_0, R_ScreenY, R_ScreenX, R_ScreenY, R_ScreenBuf, O_(DrawEnv,clip_area)         + OA_(DoubleBuffer,draw,0)), /* draw[0].clip_area = (0, 240, 320, 240). C11's SetDefDrawEnv writes clip.y = y_arg. */
-	mac_store_v2s2(  R_0, R_ScreenY,                       R_ScreenBuf, O_(DrawEnv,drawing_offset[0]) + OA_(DoubleBuffer,draw,0)), /* draw[0].drawing_offset[0] = (0, 240); C11 passes y_arg as ofs. */
+	mac_store_rects2(R_0, R_ScreenY, R_ScreenX, R_ScreenY, R_ScreenBuf, O_(DrawEnv,clip_area)         + O_(DoubleBuffer,draw[0])), /* draw[0].clip_area = (0, 240, 320, 240). C11's SetDefDrawEnv writes clip.y = y_arg. */
+	mac_store_v2s2(  R_0, R_ScreenY,                       R_ScreenBuf, O_(DrawEnv,drawing_offset[0]) + O_(DoubleBuffer,draw[0])), /* draw[0].drawing_offset[0] = (0, 240); C11 passes y_arg as ofs. */
 
-	mac_store_v2s2(R_ScreenX, R_ScreenY, R_ScreenBuf, O_(DrawEnv,clip_area.width) + OA_(DoubleBuffer,draw,1)),
+	mac_store_v2s2(R_ScreenX, R_ScreenY, R_ScreenBuf, O_(DrawEnv,clip_area.width) + O_(DoubleBuffer,draw[1])),
 
 	/* draw[0].texture_window = (0, 0, 0, 0); two word-zeroes cover the full 8-byte tw field. */
-	store_word(R_0, R_ScreenBuf, O_(DrawEnv,texture_window.x)     + OA_(DoubleBuffer,draw,0)),
-	store_word(R_0, R_ScreenBuf, O_(DrawEnv,texture_window.width) + OA_(DoubleBuffer,draw,0)),
+	store_word(R_0, R_ScreenBuf, O_(DrawEnv,texture_window.x)     + O_(DoubleBuffer,draw[0])),
+	store_word(R_0, R_ScreenBuf, O_(DrawEnv,texture_window.width) + O_(DoubleBuffer,draw[0])),
 
-	store_word(R_0, R_ScreenBuf, O_(DrawEnv,drawing_offset[0].x)  + OA_(DoubleBuffer,draw,1)),
-	store_word(R_0, R_ScreenBuf, O_(DrawEnv,texture_window.x)     + OA_(DoubleBuffer,draw,1)),
-	store_word(R_0, R_ScreenBuf, O_(DrawEnv,texture_window.width) + OA_(DoubleBuffer,draw,1)),
+	store_word(R_0, R_ScreenBuf, O_(DrawEnv,drawing_offset[0].x)  + O_(DoubleBuffer,draw[1])),
+	store_word(R_0, R_ScreenBuf, O_(DrawEnv,texture_window.x)     + O_(DoubleBuffer,draw[1])),
+	store_word(R_0, R_ScreenBuf, O_(DrawEnv,texture_window.width) + O_(DoubleBuffer,draw[1])),
 
 	/* draw[0].texture_page = 10 (gp0_tpage_default). C11 SetDefDrawEnv at C11_only.elf:0x8001273C writes the same 0x0A. . */
 	add_ui(R_T0, R_0, gp0_tpage_default),
-	store_half(R_T0, R_ScreenBuf, O_(DrawEnv,texture_page) + OA_(DoubleBuffer,draw,0)),
-	store_half(R_T0, R_ScreenBuf, O_(DrawEnv,texture_page) + OA_(DoubleBuffer,draw,1)),
+	store_half(R_T0, R_ScreenBuf, O_(DrawEnv,texture_page) + O_(DoubleBuffer,draw[0])),
+	store_half(R_T0, R_ScreenBuf, O_(DrawEnv,texture_page) + O_(DoubleBuffer,draw[1])),
 
 	/* draw[0] control bytes: flag_dither=1, flag_draw_on_display=1 (the dfe bit per psx-spx; libpsyx sets it via `SetDefDrawEnv`'s conditional at C11_only.elf:0x80012728), enable_auto_clear=1. Each byte is named;
 	 * the previous `store_word(R_0, ..., +20)` overwrote all four with zero. */
 	add_ui(R_T0, R_0, 1),
-	store_byte(R_T0, R_ScreenBuf, O_(DrawEnv,flag_dither)          + OA_(DoubleBuffer,draw,0)),
-	store_byte(R_T0, R_ScreenBuf, O_(DrawEnv,flag_draw_on_display) + OA_(DoubleBuffer,draw,0)),
-	store_byte(R_T0, R_ScreenBuf, O_(DrawEnv,enable_auto_clear)    + OA_(DoubleBuffer,draw,0)),
-	store_byte(R_T0, R_ScreenBuf, O_(DrawEnv,flag_dither)          + OA_(DoubleBuffer,draw,1)),
-	store_byte(R_T0, R_ScreenBuf, O_(DrawEnv,flag_draw_on_display) + OA_(DoubleBuffer,draw,1)),
-	store_byte(R_T0, R_ScreenBuf, O_(DrawEnv,enable_auto_clear)    + OA_(DoubleBuffer,draw,1)),
+	store_byte(R_T0, R_ScreenBuf, O_(DrawEnv,flag_dither)          + O_(DoubleBuffer,draw[0])),
+	store_byte(R_T0, R_ScreenBuf, O_(DrawEnv,flag_draw_on_display) + O_(DoubleBuffer,draw[0])),
+	store_byte(R_T0, R_ScreenBuf, O_(DrawEnv,enable_auto_clear)    + O_(DoubleBuffer,draw[0])),
+	store_byte(R_T0, R_ScreenBuf, O_(DrawEnv,flag_dither)          + O_(DoubleBuffer,draw[1])),
+	store_byte(R_T0, R_ScreenBuf, O_(DrawEnv,flag_draw_on_display) + O_(DoubleBuffer,draw[1])),
+	store_byte(R_T0, R_ScreenBuf, O_(DrawEnv,enable_auto_clear)    + O_(DoubleBuffer,draw[1])),
 
 	/* draw[0].initial_bg_color = (r=7, g=7, b=7). */
 	add_ui(R_T0, R_0, 7),
-	mac_store_rgb8(R_T0,R_T0,R_T0, R_ScreenBuf, O_(DrawEnv,initial_bg_color) + OA_(DoubleBuffer,draw,0)),
-	mac_store_rgb8(R_T0,R_T0,R_T0, R_ScreenBuf, O_(DrawEnv,initial_bg_color) + OA_(DoubleBuffer,draw,1)),
+	mac_store_rgb8(R_T0,R_T0,R_T0, R_ScreenBuf, O_(DrawEnv,initial_bg_color) + O_(DoubleBuffer,draw[0])),
+	mac_store_rgb8(R_T0,R_T0,R_T0, R_ScreenBuf, O_(DrawEnv,initial_bg_color) + O_(DoubleBuffer,draw[1])),
 
 	mac_yield(),
 };
 
+/* gp_screen_init's GPR setup. Tests the mixed user-pinning + auto-reg pattern:
+ *   - R_IO_BaseAddr = R_T4 (user-pinned via atom_reg; pre-existing)
+ *   - R_GP1_Offset  = R_T2 (user-pinned via atom_reg; NEW -- for GPIO_PORT1_OFFSET)
+ *   - R_ScreenX     = R_T5 (user-pinned via atom_reg; used as a transfer and GTE setup reg)
+ *   - R_GpTmp       = auto-allocated by the lua pass and used for several GPU transfers;
+ *                    the C preprocessor resolves it to the chosen free pool GPR.
+ *
+ * For gp_screen_init, the auto-reg pool exclusions are:
+ *   user_pinned (from the corpus register_alias_registry) : R_T0..R_T7 (all 8 user-pinned across hello_camera.atom.c)
+ *   body-parsed physical registers                         : aliases resolve through the registry;
+ *                                                           the body uses R_ScreenX, not raw R_T5
+ *   source_pool after both subtractions                   : {R_V0, R_V1} only
+ *   R_GpTmp gets R_V0 (the first-fit choice). Its repeated GPU-transfer use proves that the
+ *   auto-reg allocation is active while the R_ScreenX references prove the pinned alias is used.
+ *   R_TapePtr (R_T9), R_AtomJmp (R_T8), R_AT are excluded from the POOL by construction in
+ *   passes/auto_reg.lua -- see the "obvious exclusions" comment block at the top of that file.
+ */
 enum {
 	R_IO_BaseAddr = R_T4 atom_reg, /* Caller-pinned: IO_BASE_ADDR = 0x1F800000 */
+	R_GP1_Offset  = R_T2 atom_reg, /* Caller-pinned: GPIO_PORT1_OFFSET = 0x10 */
+	atom_auto_reg(gp_screen_init, R_GpTmp),  /* Auto-allocated scratch; resolved to a free pool GPR by the lua pass. C-preprocessor expands to R_GpTmp = R_GpTmp_Code with an atom_auto_reg trailing comment. */
 #define R_IO_BaseAddr_Code R_T4_Code
+#define R_GP1_Offset_Code  R_T2_Code
 };
 internal MipsAtom_(gp_screen_init) atom_info(atom_phase(screen_init), atom_reads(R_IO_BaseAddr)) {
 	store_word(R_0, R_IO_BaseAddr, GPIO_PORT1_OFFSET),                                   /* GP1(00h) Reset */
-	mac_gcmd_push(gp1_word_ResetCmdBuffer(),   R_T5, R_IO_BaseAddr, GPIO_PORT1_OFFSET),  /* GP1(01h) ClearFIFO */
-	mac_gcmd_push(gp1_word_AcknowledgeIRQ(),   R_T5, R_IO_BaseAddr, GPIO_PORT1_OFFSET),  /* GP1(02h) AckIRQ */
-	mac_gcmd_push(gp1_word_DisplayOn(),        R_T5, R_IO_BaseAddr, GPIO_PORT1_OFFSET),  /* GP1(03h) Display ON */
-	mac_gcmd_push(gp1_word_dma_to_gpu(),       R_T5, R_IO_BaseAddr, GPIO_PORT1_OFFSET),  /* GP1(04h) DMADirection=2 (CPU→GPU). libpsyx's per-frame PutDrawEnv/DrawOTag use DMA2; without this the DMA queue never drains. */
-	mac_gcmd_push(gp1_word_StartDisplayArea(), R_T5, R_IO_BaseAddr, GPIO_PORT1_OFFSET),  /* GP1(05h) StartDisplayArea (X=0, Y=0) */
+	mac_gcmd_push(gp1_word_ResetCmdBuffer(),   R_ScreenX, R_IO_BaseAddr, GPIO_PORT1_OFFSET), /* GP1(01h) ClearFIFO; uses pinned R_ScreenX as the transfer reg. */
+	mac_gcmd_push(gp1_word_AcknowledgeIRQ(),   R_ScreenX, R_IO_BaseAddr, GPIO_PORT1_OFFSET), /* GP1(02h) AckIRQ; uses pinned R_ScreenX as the transfer reg. */
+	mac_gcmd_push(gp1_word_DisplayOn(),        R_ScreenX, R_IO_BaseAddr, GPIO_PORT1_OFFSET), /* GP1(03h) Display ON; uses pinned R_ScreenX as the transfer reg. */
+	mac_gcmd_push(gp1_word_dma_to_gpu(),       R_GpTmp,   R_IO_BaseAddr, GPIO_PORT1_OFFSET), /* GP1(04h) DMADirection=2 (CPU->GPU). libpsyx's per-frame PutDrawEnv/DrawOTag use DMA2; without this the DMA queue never drains. Uses auto-allocated R_GpTmp. */
+	mac_gcmd_push(gp1_word_StartDisplayArea(), R_GpTmp,   R_IO_BaseAddr, GPIO_PORT1_OFFSET), /* GP1(05h) StartDisplayArea (X=0, Y=0); uses auto-allocated R_GpTmp. */
 
-	/* GP1: DisplayMode + Display Ranges */
-	mac_gcmd_push(gp1_word_display_mode_320x240_15bit_ntsc, R_T5, R_IO_BaseAddr, GPIO_PORT1_OFFSET),
-	mac_gcmd_push(gp1_word_horizontal_range_ntsc,           R_T5, R_IO_BaseAddr, GPIO_PORT1_OFFSET),
-	mac_gcmd_push(gp1_word_vertical_range_ntsc,             R_T5, R_IO_BaseAddr, GPIO_PORT1_OFFSET),
+	/* GP1: DisplayMode + Display Ranges. */
+	mac_gcmd_push(gp1_word_display_mode_320x240_15bit_ntsc, R_ScreenX, R_IO_BaseAddr, GPIO_PORT1_OFFSET),
+	mac_gcmd_push(gp1_word_horizontal_range_ntsc,           R_ScreenX, R_IO_BaseAddr, GPIO_PORT1_OFFSET),
+	mac_gcmd_push(gp1_word_vertical_range_ntsc,             R_ScreenX, R_IO_BaseAddr, GPIO_PORT1_OFFSET),
 
 	/* GTE: SetGeomOffset (OFX, OFY) — ScreenRes_CenterX, ScreenRes_CenterY. */
-	load_upper_i(R_T5, ScreenRes_CenterX), gte_mv_to_ctrl_r(R_T5, gte_cr_OFX_Code),
-	load_upper_i(R_T5, ScreenRes_CenterY), gte_mv_to_ctrl_r(R_T5, gte_cr_OFY_Code),
+	load_upper_i(R_ScreenX, ScreenRes_CenterX), gte_mv_to_ctrl_r(R_ScreenX, gte_cr_OFX_Code),
+	load_upper_i(R_ScreenX, ScreenRes_CenterY), gte_mv_to_ctrl_r(R_ScreenX, gte_cr_OFY_Code),
 
 	/* GTE: SetGeomScreen (H) — CR26 (per PSX-SPX / libpsyx), value is the raw projection-plane distance, NOT shifted. */
-	add_ui(R_T5, R_0, ScreenZ), gte_mv_to_ctrl_r(R_T5, gte_cr_H_Code),
+	add_ui(R_ScreenX, R_0, ScreenZ), gte_mv_to_ctrl_r(R_ScreenX, gte_cr_H_Code),
 
 	/* GP1: DisplayEnable — bit 0 = 0 (Display ON). */
-	mac_gcmd_push(gp1_word_DisplayOn(), R_T5, R_IO_BaseAddr, GPIO_PORT1_OFFSET),
+	mac_gcmd_push(gp1_word_DisplayOn(), R_GpTmp, R_IO_BaseAddr, GPIO_PORT1_OFFSET), /* Uses auto-allocated R_GpTmp. */
 	mac_yield(),
 };
 
-/* ----- pad_apply_input -----
- * Reads pad[0].buttons + pad[0].left_x; 
- * Applies the input-semantics deltas to cube_rot.y + floor_rot.y:
- *   - D-pad Left:  cube_rot.y += 30, floor_rot.y += 5
- *   - D-pad Right: cube_rot.y -= 30, floor_rot.y -= 5
- *   - Analog stick X (dead zone 0x70..0x90):
- *       cube delta  = (0x80 - left_x) >> 2  (range approx -32..+32)
- *       floor delta = (0x80 - left_x) >> 5  (range approx -4..+4)
- *   - D-pad + analog deltas add when used together.
- *
- * Convention:
- *   pad_state = 0 means no buttons active. 
- *   The fail-safe zero-button value flows through unchanged, so a disconnected/fresh pad produces no rotation.
- *   The branch_le_zero pattern below matches the existing pad_input_demo convention (atom body lines 248/257).
- *
- * Signed-delta trick:
- * load_byte_u zero-extends left_x to 32 bits; sub_u from 0x80 wraps to a SIGNED two's-complement value in the negative range;
- * shift_aright (sra) then correctly sign-extends the shift for both positive (left_x < 0x80) and negative (left_x > 0x80) cases.
- * Digital pads publish left_x = 0x80 → delta = 0 → no rotation, so the analog step is naturally a no-op for digital controllers.
- */
 typedef Struct_(Binds_PadApplyInput) {
-    PadState* state;
-    V3_S2*    cube_rot;
-    V3_S2*    floor_rot;
+	PadState* state;
+	V3_S2*    cube_rot;
+	V3_S2*    floor_rot;
 };
 enum {
 	R_PadStateT5 = R_T5 atom_reg,
 	R_CubeRot    = R_T1 atom_reg,
 	R_FloorRot   = R_T2 atom_reg,
 };
-internal MipsAtom_(pad_apply_input) atom_info(atom_bind(Binds_PadApplyInput)
+internal MipsAtom_(pad_input_cube_rotation) atom_info(atom_bind(Binds_PadApplyInput)
 , atom_reads(R_T0, R_CubeRot, R_FloorRot, R_T3, R_T4, R_PadStateT5, R_TapePtr)
 , atom_writes(     R_CubeRot, R_FloorRot)
 ) {
@@ -225,7 +748,7 @@ internal MipsAtom_(pad_apply_input) atom_info(atom_bind(Binds_PadApplyInput)
 	// Note(Ed): Potential op with delay slot?
 
 	/* D-pad Left: cube_rot.y += 30, floor_rot.y += 5.  */
-	and_i(R_T3, R_T0, pad0_(Pad_Left)), branch_le_zero(R_T3, atom_offset(dpad_left, exit_dpad_left)),
+	and_i(R_T3, R_T0, Pad_Left), branch_le_zero(R_T3, atom_offset(dpad_left, exit_dpad_left)),
 		load_half( R_T4, R_CubeRot,  O_(V3_S2,y)),   /* BD-slot */
 		load_half( R_T3, R_FloorRot, O_(V3_S2,y)),
 		add_si(    R_T4, R_T4, 30),
@@ -235,7 +758,7 @@ internal MipsAtom_(pad_apply_input) atom_info(atom_bind(Binds_PadApplyInput)
 	atom_label(exit_dpad_left)
 
 	/* D-pad Right: cube_rot.y -= 30, floor_rot.y -= 5. */
-	and_i(R_T3, R_T0, pad0_(Pad_Right)), branch_le_zero(R_T3, atom_offset(dpad_right, exit_dpad_right)),
+	and_i(R_T3, R_T0, Pad_Right), branch_le_zero(R_T3, atom_offset(dpad_right, exit_dpad_right)),
 		load_half( R_T4, R_CubeRot,  O_(V3_S2,y)),   /* BD-slot */
 		load_half( R_T3, R_FloorRot, O_(V3_S2,y)),
 		add_si(    R_T4, R_T4, -30),
@@ -313,7 +836,60 @@ atom_label(exit_stick)
 };
 
 enum {
-	R_PrimCursor = R_T7 atom_reg atom_type(U4*),    /* VRAM output cursor (primitive buffer) */
+	R_Cam         = R_T4 atom_reg,
+	R_CamPadState = R_T5 atom_reg,
+};
+typedef Struct_(Binds_PadInputCam) {
+	PadState* state;
+	Camera*   cam;
+};
+internal MipsAtom_(pad_input_cam) atom_info(atom_bind(Binds_PadInputCam)
+, atom_reads( R_Cam, R_CamPadState, R_TapePtr)
+, atom_writes(R_Cam)
+) {
+	/* Bind pop: state → R_CamPadState (R_T5), cam → R_Cam (R_T4), advance R_TapePtr by 8. */
+	load_word(R_CamPadState, R_TapePtr, O_(Binds_PadInputCam,state)),
+	load_word(R_Cam,         R_TapePtr, O_(Binds_PadInputCam,cam)),
+	add_ui_self(             R_TapePtr, S_(Binds_PadInputCam)),
+
+	/* Load pad[0].buttons into R_T0; nop fills the load-delay slot. */
+	load_word(R_T0, R_CamPadState, O_(PadState,buttons)),
+	load_word(R_T1, R_Cam, O_(Camera,pos.x)), // BD-Slot.
+
+	// D-pad Left → cam.pos.x -= 50.  and_i fulfills BD-slot for load on R_Cam.
+	and_i(R_T3, R_T0, Pad_Left), branch_le_zero(R_T3, atom_offset(left_x, exit_left_x)), mac_yield_load(),
+		add_si(R_T1, R_T1, -50), store_word(R_T1, R_Cam, O_(Camera,pos.x)),
+atom_label(exit_left_x)
+	/* D-pad Right → cam.pos.x += 50. Reuses R_T1 from Left. */
+	and_i(R_T3, R_T0, Pad_Right), branch_le_zero(R_T3, atom_offset(right_x, exit_right_x)), nop,
+		add_si(R_T1, R_T1,  50), store_word(R_T1, R_Cam, O_(Camera,pos.x)),
+atom_label(exit_right_x)
+
+	/* D-pad Up → cam.pos.y -= 50. Load pos.y BEFORE the andi. */
+	load_word(R_T1, R_Cam, O_(Camera,pos.y)),
+	and_i(R_T3, R_T0, Pad_Up), branch_le_zero(R_T3, atom_offset(up_y, exit_up_y)), nop,
+		add_si(R_T1, R_T1, -50), store_word(R_T1, R_Cam, O_(Camera,pos.y)),
+atom_label(exit_up_y)
+	/* D-pad Down → cam.pos.y += 50. Reuses R_T1 from Up. */
+	and_i(R_T3, R_T0, Pad_Down), branch_le_zero(R_T3, atom_offset(down_y, exit_down_y)), nop,
+		add_si(R_T1, R_T1,  50), store_word(R_T1, R_Cam, O_(Camera,pos.y)),
+atom_label(exit_down_y)
+
+	/* D-pad Cross → cam.pos.z -= 50. Load pos.z BEFORE the andi. */
+	load_word(R_T1, R_Cam, O_(Camera,pos.z)),
+	and_i(R_T3, R_T0, Pad_Cross), branch_le_zero(R_T3, atom_offset(cross_z, exit_cross_z)), nop,
+		add_si(R_T1, R_T1, -50), store_word(R_T1, R_Cam, O_(Camera,pos.z)),
+atom_label(exit_cross_z)
+	/* D-pad Circle → cam.pos.z += 50. Reuses R_T1 from Cross. */
+	and_i(R_T3, R_T0, Pad_Circle), branch_le_zero(R_T3, atom_offset(circle_z, exit_circle_z)), nop,
+		add_si(R_T1, R_T1,  50), store_word(R_T1, R_Cam, O_(Camera,pos.z)),
+atom_label(exit_circle_z)
+
+	mac_yield_tail(),
+};
+
+enum {
+	R_PrimCursor = R_T7 atom_reg atom_type(U4*),    /* Output cursor (primitive buffer) */
 	R_FaceCursor = R_T4 atom_reg atom_type(V4_S2*), /* Cube face-index cursor (V4_S2*); floor context switches to V3_S2* via atom_phase */
 	R_VertBase   = R_T5 atom_reg atom_type(V3_S2*), /* Base address of the vertex array */
 	R_OtBase     = R_T6 atom_reg atom_type(U4*),    /* Base address of the Ordering Table */
@@ -322,7 +898,6 @@ enum {
 #define R_VertBase_Code    R_T5_Code
 #define R_OtBase_Code      R_T6_Code
 };
-
 typedef Struct_(Binds_CubeTri) {
 	U4     PrimCursor;
 	V4_S2* FaceCursor;
@@ -359,9 +934,9 @@ MipsAtom_(cube_g4_face) atom_info(atom_phase(cube_g4),
 
 	gte_mv_from_data_r(R_T0, C2_MAC0), nop,
 	branch_le_zero(R_T0, atom_offset(cull, cube_g4_face_exit)),
-		/* BD-slot: write the prim tag (R_0=0; overwrites the legacy tag word in the prim_buffer).
+		/* BD-slot: Write the prim tag (R_0=0; overwrites the legacy tag word in the prim_buffer).
 		 * If branch IS taken (face culled), the body is skipped and this 0-tag is stranded —
-		 * harmless because the OT entry that points to this prim is created later, only on the body path. */
+		 * harmless because the OT entry that points to this prim is created later. */
 		store_word(R_0, R_PrimCursor, O_(Poly_G4, tag)),
 		shift_lleft(R_AT, R_T3, v3s2_byteoff), add_u(R_AT, R_AT, R_VertBase),
 		load_word(R_V0, R_AT, O_(V3_S2, x)),   load_word(R_V1, R_AT, O_(V3_S2, z)),
@@ -418,7 +993,7 @@ MipsAtom_(floor_f3_face) atom_info(atom_phase(floor_f3)
 	, atom_reads( R_PrimCursor, R_FaceCursor, R_VertBase, R_OtBase)
 	, atom_writes(R_PrimCursor, R_FaceCursor)
 ) {
-	mac_load_tri_indices(  R_FaceCursor, R_T0, R_T1, R_T2),
+	mac_load_tri_indices(R_FaceCursor, R_T0, R_T1, R_T2),
 	mac_gte_load_tri_verts(R_VertBase,   R_T0, R_T1, R_T2),
 	nop2, gte_cmdw_rotate_translate_perspective_triple, // 2 nops retire the final cpu -> gte writes before RTPT
 	gte_cmdw_nclip,

code/hello_camera/hello_camera.c

@@ -26,10 +26,12 @@
 #include "duffle/dsl.atom.h"
 #include "duffle/lottes_tape.h"
 
+#include "duffle/bios.h"
 #include "duffle/psyq.h"
 #pragma endregion Duffle Headers
 
 #pragma region Duffle TUs
+#include "duffle/pad.c"
 #include "duffle/math.atom.c"
 #include "duffle/mips.atom.c"
 #include "duffle/gte.atom.c"
@@ -41,6 +43,7 @@
 #pragma region Hello Camera Headers
 #	include "gen/macs.h"
 #	include "gen/offsets.h"
+#	include "gen/auto_reg.h"
 
 #include "hello_camera.h"
 #pragma endregion Hello Camera Headers
@@ -50,8 +53,15 @@
 #pragma endregion Hello Joypad TUs
 
 enum {
-	Scratchpad_Len = 1024, 
-	MemTape_Len    = 512,
+	Scratchpad_Loc = 0x1F800000,
+};
+#define C_scratch(type) C_(type, Scratchpad_Loc)
+
+enum {
+	Scratchpad_Len           = 1024,
+	MemTape_Len              = 512,
+	ResolveLookAtArena_Words = 1024,
+	ResolveLookAtArena_Size  = ResolveLookAtArena_Words * S_(MipsCode),
 };
 typedef Struct_(SMemory) {
 	PrimitiveArena          primitives;
@@ -61,7 +71,10 @@ typedef Struct_(SMemory) {
 
 	U4 MemTape[MemTape_Len];
 
-	M3_S2 tform_world;
+	MT3_S2S4 tform_world;
+	MT3_S2S4 tform_view;
+
+	Camera cam;
 
 	Ent_Cube  cube;
 	Ent_Floor floor;
@@ -69,11 +82,18 @@ typedef Struct_(SMemory) {
 	PadBiosRaw pad_raw[2];
 	PadState   pad[2];
 
+	// TODO(Ed): We don't need this we can just cast at any point an address to a desired view of scratchpad, we have the address.
 	U4_V scratchpad; // d-cache
+
+	U1        resolve_look_at_mem[ResolveLookAtArena_Size];
+	MipsAtom* resolve_look_at_atom_addrs[10];
 };
 global SMemory smem;
 extern SMemory smem;
 
+#define pad0_btn_(btn) btn & smem.pad[0].buttons
+#define pad1_btn_(btn) btn & smem.pad[1].buttons
+
 I_ B1* prim__alloc(U4 type_width, Str8 type_name) {
 	gknown PrimitiveArena* pa  = & smem.primitives;
 	gknown B1*             buf = (B1*) r_(smem.primitives.buf)[smem.active_buf_id];
@@ -84,75 +104,313 @@ I_ B1* prim__alloc(U4 type_width, Str8 type_name) {
 }
 #define prim_alloc(type) (type*)prim__alloc(S_(type), slit( stringify(type)))
 
-/* Uses ONE 8-byte frame allocated via the compiler's standard prologue.
- * The 4 wasted-arg words for B(12h) InitPAD2 live at [SP+0..15] but are not explicitly allocated.
- * The compiler handles the MIPS O32 "wasted stack" convention for us by treating the B-call as a 4-arg call.
+I_ void resolve_look_at_c11(MT3_S2S4* look_at, P3_S4* eye, P3_S4* target, V3_S4* up_in) {
+// RGA(Lengyel): Build matrix expansion of a rigid transformation. Corresponding motor is not constructed; we write the LA form for GTE.
+// Preconditions: eye != target, up_in not collinear with (target - eye).
+	V3_S4 right, up, forward;
+	V3_S4 ux, uy, uz;
+	V3_S4 pos, off;
+
+	forward = target[0]; sub_v3s4(& forward, eye[0]); // RGA(Lengyel): Affine point - point = zero-weight direction.
+	normalize_v3s4(& forward, & uz);                  // RGA(Lengyel): Normalize the direction bulk. Not finite-point unitization.
+
+	cross_v3s4(& uz,   up_in, & right); normalize_v3s4(& right, & ux); // RGA(Lengyel): Complement(Wedge(forward, up_in)) -> right axis.
+	cross_v3s4(& uz, & ux,    & up);    normalize_v3s4(& up,    & uy); // RGA(Lengyel): Complement(Wedge(forward, right)) -> up axis.
+
+	// RGA(Lengyel): matrix expansion of the world-to-camera rotation (basis rows).
+	look_at->m[0][0] = ux.x; look_at->m[0][1] = ux.y; look_at->m[0][2] = ux.z;
+	look_at->m[1][0] = uy.x; look_at->m[1][1] = uy.y; look_at->m[1][2] = uy.z;
+	look_at->m[2][0] = uz.x; look_at->m[2][1] = uz.y; look_at->m[2][2] = uz.z;
+
+	pos = eye[0]; mul_v3s4(& pos, v3s4(-1,-1,-1)); // RGA(Lengyel): -eye in world coordinates (spatial bulk only; implicit weight is dropped).
+
+	// RGA(Lengyel): R * (-eye) is the full matrix translation column. 
+	// Motor translator would store half this displacement in m.xyz; GTE consumes full column.
+	mul_m3s2_v3s4(look_at, & pos, & off);
+	trans_m3s2(   look_at,        & off);
+}
+FI_ void camera_look_at_c11(Camera* c, P3_S4* target, V3_S4* up_in) { resolve_look_at_c11(& c->look_at, & c->pos, target, up_in); }
+
+/* Pre-build all 7 chain atoms of the resolve_look_at bundle into the static arena.
+ * Called ONCE from main() before the frame loop.
+ * After this returns, the smem.resolve_look_at_atom_addrs[] array contains valid MIPS atom pointers
+ * for the frame-time bundle helper to emit via tb_emit(tb, captured_addr).
  *
- * The buffer pointers are passed as arguments so the compiler keeps them in callee-saved registers;
- * The B(12h) asm volatile block does NOT clobber those registers (it clobbers only the volatile GPRs + the B-table arg registers explicitly).
- * The C-level writes after the call re-load the pointers from their callee-saved homes.
+ * 4 unique procs in hello_camera.atom.c (chain atoms 0, 2, 4, 6); atoms 1, 3, 5
+ * share the GENERIC normalize_v3s4_proc from gte.atom.c (called 3x with different
+ * O_(ResolveLookAtScratch,...) offsets):
+ * 	0: resolve_look_at__input_and_sub_proc
+ * 	1: normalize_v3s4_proc                  (fwd → uz; offsets 0, 16)
+ * 	2: resolve_look_at__cross_uz_up_in_to_right_proc
+ * 	3: normalize_v3s4_proc                  (right → ux; offsets 32, 48)
+ * 	4: resolve_look_at__cross_uz_ux_to_up_proc
+ * 	5: normalize_v3s4_proc                  (up → uy; offsets 64, 80)
+ * 	6: resolve_look_at__populate_and_translate_proc
  *
- * The clobber list for both B-calls names the full BIOS destroy set documented in kernelbios.md:167-174 (R1..R15, R24..R25, R31, HI/LO).
- * The kernel-ABI "volatile GPRs" subset is clb_system; the rest of the destroy set is enumerated explicitly here. */
-NI_ void pad_bios_init_start(PadBiosRaw* raw0, PadBiosRaw* raw1)
-{
-	/* Pin raw0 + raw1 to $a0 + $a1 via rgcc; the B(12h) call uses these directly.
-	 * The `(void)` casts mark them as unread after the call so the compiler doesn't need to move them back. */
-	register PadBiosRaw* p0 rgcc(R_A0) = raw0;
-	register PadBiosRaw* p1 rgcc(R_A1) = raw1;
-	(void)p0; (void)p1;
+ * Task 12.16 promotion: the bundle-specific resolve_look_at__chain_normalize_proc
+ * has been promoted to the generic normalize_v3s4_proc (gte.atom.c), which now
+ * takes r_scratch + r_src_offset + r_dst_offset as U4 parameters. The 3 callers
+ * pass O_(ResolveLookAtScratch,...) macros as offset args. The metaprogram emits
+ * one set of `atom_offset__normalize_v3s4__srav_path__aligned_done` defs
+ * (namespaced by atom name) in duffle/gen/offsets.h, shared by all 3 callers.
+ *
+ * GPR pool per atom: 10 free GPRs (R_T0..R_T3 + R_T5..R_T7 + R_V0 + R_V1 + R_AT).
+ * R_T4 is reserved as the wave-context carrier (R_ResolveScratch).
+ */
+/* === EXPLICIT REGISTER ALLOCATION TRACKER ===
+ * Every GPR used by every atom is tracked below. NO GPR is assigned to
+ * two atoms at overlapping lifetimes. The tape runtime preserves R_T8/R_T9
+ * (R_AtomJmp/R_TapePtr) and clobbers R_T0-R_T7, R_AT, R_V0, R_V1.
+ * R_T4 is reserved as R_ResolveScratch (wave-context carrier).
+ *
+ * GPR pool: R_T0($8), R_T1($9), R_T2($10), R_T3($11), R_T5($13),
+ *           R_T6($14), R_T7($15), R_V0($2), R_V1($3), R_AT($1)
+ * Reserved: R_T4($12) = R_ResolveScratch
+ * Tape: R_T8($24) = R_AtomJmp, R_T9($25) = R_TapePtr (preserved)
+ *
+ * === ATOM 0: input_and_sub (stages eye/up_in, computes fwd) ===
+ * Pop tape → R_T0(target), R_T1(eye), R_T2(up_in).
+ * Use R_T3,R_T5,R_T6,R_T7 as temps.
+ * NO conflict with other atoms (each atom has independent lifetime).
+ *
+ * === ATOM 1: normalize fwd→uz ===
+ * r_src_offset=0, r_dst_offset=16.
+ * r_src_ptr=R_T0, r_dst_ptr=R_T1, r_tmp=R_T2 (preserved for stage 4).
+ * r_mac1=R_T3, r_mac2=R_T5, r_recip=R_T6, r_lzcr=R_T7, r_shift=R_V0, r_branch=R_V1.
+ *
+ * === ATOM 2: cross uz×up_in→right ===
+ * r_a=R_T0, r_b=R_T1, r_c=R_T2, r_d=R_T3, r_f(out)=R_T5, r_g=R_T6, r_h=R_T7.
+ *
+ * === ATOM 3: normalize right→ux ===
+ * Same GPR pool as atom 1.
+ *
+ * === ATOM 4: cross uz×ux→up ===
+ * r_a=R_T0, r_b=R_T1, r_c=R_T2, r_d=R_T3, r_f(out)=R_T5, r_g=R_T6, r_h=R_T7.
+ *
+ * === ATOM 5: normalize up→uy ===
+ * Same GPR pool as atom 1.
+ *
+ * === ATOM 6a: populate (m[][] from ux/uy/uz, t[]=0) ===
+ * r_look_at=R_T0 (pop tape), r_scratch=R_T4.
+ * r_pux=R_T1, r_puy=R_T3, r_puz=R_T5.
+ * r_tmp0=R_T2, r_tmp1=R_T6, r_tmp2=R_V0.
+ *
+ * === ATOM 6a.5: set_gte_mt3s2s4 (ctc2 RT matrix) ===
+ * BAKED atom. Uses R_T3 internally (hardcoded in gte.atom.c).
+ * NO conflict — different GPR pool, and the atom body hardcodes R_T3
+ * as the matrix pointer. We DON'T need to assign R_T3 to atom 6a.5
+ * because it's a baked atom with its own GPR usage.
+ *
+ * === ATOM 6b: matrix_vector (RT * (-eye) >> 12) ===
+ * r_look_at=R_T0 (pop tape), r_scratch=R_T4.
+ * r_peye=R_T1.
+ * r_tmp0=R_T2, r_tmp1=R_T3, r_tmp2=R_T5.
+ * Uses mac_apply_matrix_lv which internally uses these temps.
+ *
+ * === ATOM 6c: trans_matrix (off → look_at->t[]) ===
+ * r_look_at=R_T0 (pop tape), r_scratch=R_T4.
+ * r_off_ptr=R_T1.
+ * r_tmp0=R_T2.
+ *
+ * === CONFLICT CHECK ===
+ * All atoms use the same GPR pool R_T0-R_T3, R_T5-R_T7, R_V0-R_V1.
+ * But atoms are SEQUENTIAL — each atom's lifetime is disjoint from
+ * the next atom's lifetime. The tape yield handshake between atoms
+ * preserves R_TapePtr (R_T9) and R_AtomJmp (R_T8).
+ *
+ * The GPR pool is SHARED across atoms (they run sequentially, not
+ * concurrently). Each atom's build call assigns specific R_T* codes
+ * for that atom's body. The same R_T* code can be reused across atoms
+ * because the previous atom's body has already yielded.
+ */
+internal void resolve_look_at_init(void) {
+	/* Wrap the static arena in a MipsAtomBuilder. */
+	AtomArena ab = atomarena_make(slice_ut_arr(smem.resolve_look_at_mem));
 
-	// TODO(Ed): Properly annotate the raw values in the inline asm instructions.
-	// Use enums.
+	/* === ATOM 0: input_and_sub === */
+	U4 const r_target_ptr = R_T0;  /* tape pop → target */
+	U4 const r_eye_ptr    = R_T1;  /* tape pop → eye */
+	U4 const r_up_in_ptr  = R_T2;  /* tape pop → up_in */
+	U4 const r_tmp0_0     = R_T3;
+	U4 const r_tmp1_0     = R_T5;
+	U4 const r_tmp2_0     = R_T6;
+	U4 const r_tmp3_0     = R_T7;
+	smem.resolve_look_at_atom_addrs[0] = resolve_look_at__input_and_sub_proc(& ab,
+		R_ResolveScratch,
+		r_target_ptr, r_eye_ptr, r_up_in_ptr,
+		r_tmp0_0, r_tmp1_0, r_tmp2_0, r_tmp3_0);
 
-	/* B(12h) InitPAD2(raw0, 0x22, raw1, 0x22)
-	 *   $a0 = raw0 (rgcc-bound; survives the sequence below)
-	 *   $a1 = raw1 (preserved into $a2 before $a1 is overwritten)
-	 *   $a2 = raw1 (moved from $a1; survives $a1's overwrite)
-	 *   $a3 = 0x22 (immediate)
-	 *   $t1 = 0x12 (function number)
-	 *   $t2 = 0xB0 (BIOS B-table address) */
-	asm volatile(
-		asm_words(
-			or_u(    rarg_2, rarg_1, rdiscard), /* $a2 = $a1 = raw1 */
-			add_ui(  rarg_1, rdiscard, 0x22),   /* $a1 = 0x22 */
-			add_ui(  rarg_3, rdiscard, 0x22),   /* $a3 = 0x22 */
-			add_ui(  rtmp_1, rdiscard, 0x12),   /* $t1 = 0x12 */
-			add_ui(  rtmp_2, rdiscard, 0xB0),   /* $t2 = 0xB0 */
-			call_reg(rtmp_2),                   /* jalr $t2, $ra */
-			nop                                 /* BD slot */
-		)
-		asm_rpins, r_use(p0), r_use(p1)
-		asm_clobber: 
-			rlit(R_AT), 
-			rlit(R_V0), rlit(R_V1), 
-			rlit(R_T0), rlit(R_T1), rlit(R_T2), rlit(R_T3), rlit(R_T4),
-			rlit(R_T5), rlit(R_T6), rlit(R_T7), rlit(R_T8), rlit(R_T9),
-			rlit(R_RA),
-			clb_mem_drain
-	);
+	/* === ATOM 1: normalize fwd→uz === */
+	U4 const r_src_offset_1  = O_(ResolveLookAtScratch, fwd);
+	U4 const r_dst_offset_1  = O_(ResolveLookAtScratch, uz);
+	U4 const r_src_ptr_1     = R_T0;
+	U4 const r_dst_ptr_1     = R_T1;
+	U4 const r_tmp_1         = R_T2;
+	U4 const r_mac1_1        = R_T3;
+	U4 const r_mac2_1        = R_T5;
+	U4 const r_recip_1       = R_T6;
+	U4 const r_lzcr_1        = R_T7;
+	U4 const r_shift_1       = R_V0;
+	U4 const r_branch_1      = R_V1;
+	smem.resolve_look_at_atom_addrs[1] = normalize_v3s4_proc(& ab,
+		R_ResolveScratch,
+		r_src_offset_1, r_dst_offset_1,
+		r_src_ptr_1, r_dst_ptr_1, r_tmp_1,
+		r_mac1_1, r_mac2_1, r_recip_1, r_lzcr_1,
+		r_shift_1, r_branch_1);
 
-	/* The C-level writes re-load the pointers via the parameter names and write 0xFF to each 
-	 * buffer's status byte to mark the initial-state hazard documented in kernelbios.md:1621-1624. */
-	u1_v(raw0)[0] = 0xFF;
-	u1_v(raw1)[0] = 0xFF;
+	/* === ATOM 2: cross uz×up_in→right === */
+	U4 const r_a_2 = R_T0;
+	U4 const r_b_2 = R_T1;
+	U4 const r_c_2 = R_T2;
+	U4 const r_d_2 = R_T3;
+	U4 const r_f_2 = R_T5;  /* out ptr (HARDCODED in body: scratch+32) */
+	U4 const r_g_2 = R_T6;  /* a ptr = scratch+16 */
+	U4 const r_h_2 = R_T7;  /* b ptr = scratch+128 */
+	smem.resolve_look_at_atom_addrs[2] = resolve_look_at__cross_uz_up_in_to_right_proc(& ab,
+		R_ResolveScratch,
+		r_a_2, r_b_2, r_c_2, r_d_2, r_f_2, r_g_2, r_h_2);
 
-	/* B(13h) StartPAD2() — no args. The BIOS preserves $sp. */
-	asm volatile(
-		asm_words(
-			add_ui(  rtmp_1, rdiscard, 0x13), /* $t1 = 0x13 */
-			add_ui(  rtmp_2, rdiscard, 0xB0), /* $t2 = 0xB0 (re-load) */
-			call_reg(rtmp_2),                 /* jalr $t2, $ra */
-			nop                               /* BD slot */
-		)
-		asm_clobber:
-			rlit(R_AT),
-			rlit(R_V0), rlit(R_V1),
-			rlit(R_T0), rlit(R_T1), rlit(R_T2), rlit(R_T3), rlit(R_T4),
-			rlit(R_T5), rlit(R_T6), rlit(R_T7), rlit(R_T8), rlit(R_T9),
-			rlit(R_RA),
-			clb_mem_drain
-	);
+	/* === ATOM 3: normalize right→ux === */
+	U4 const r_src_offset_3  = O_(ResolveLookAtScratch, right);
+	U4 const r_dst_offset_3  = O_(ResolveLookAtScratch, ux);
+	U4 const r_src_ptr_3     = R_T0;
+	U4 const r_dst_ptr_3     = R_T1;
+	U4 const r_tmp_3         = R_T2;
+	U4 const r_mac1_3        = R_T3;
+	U4 const r_mac2_3        = R_T5;
+	U4 const r_recip_3       = R_T6;
+	U4 const r_lzcr_3        = R_T7;
+	U4 const r_shift_3       = R_V0;
+	U4 const r_branch_3      = R_V1;
+	smem.resolve_look_at_atom_addrs[3] = normalize_v3s4_proc(& ab,
+		R_ResolveScratch,
+		r_src_offset_3, r_dst_offset_3,
+		r_src_ptr_3, r_dst_ptr_3, r_tmp_3,
+		r_mac1_3, r_mac2_3, r_recip_3, r_lzcr_3,
+		r_shift_3, r_branch_3);
+
+	/* === ATOM 4: cross uz×ux→up === */
+	U4 const r_a_4 = R_T0;
+	U4 const r_b_4 = R_T1;
+	U4 const r_c_4 = R_T2;
+	U4 const r_d_4 = R_T3;
+	U4 const r_f_4 = R_T5;  /* out ptr (HARDCODED: scratch+64) */
+	U4 const r_g_4 = R_T6;  /* a ptr = scratch+16 */
+	U4 const r_h_4 = R_T7;  /* b ptr = scratch+48 */
+	smem.resolve_look_at_atom_addrs[4] = resolve_look_at__cross_uz_ux_to_up_proc(& ab,
+		R_ResolveScratch,
+		r_a_4, r_b_4, r_c_4, r_d_4, r_f_4, r_g_4, r_h_4);
+
+	/* === ATOM 5: normalize up→uy === */
+	U4 const r_src_offset_5  = O_(ResolveLookAtScratch, up);
+	U4 const r_dst_offset_5  = O_(ResolveLookAtScratch, uy);
+	U4 const r_src_ptr_5     = R_T0;
+	U4 const r_dst_ptr_5     = R_T1;
+	U4 const r_tmp_5         = R_T2;
+	U4 const r_mac1_5        = R_T3;
+	U4 const r_mac2_5        = R_T5;
+	U4 const r_recip_5       = R_T6;
+	U4 const r_lzcr_5        = R_T7;
+	U4 const r_shift_5       = R_V0;
+	U4 const r_branch_5      = R_V1;
+	smem.resolve_look_at_atom_addrs[5] = normalize_v3s4_proc(& ab,
+		R_ResolveScratch,
+		r_src_offset_5, r_dst_offset_5,
+		r_src_ptr_5, r_dst_ptr_5, r_tmp_5,
+		r_mac1_5, r_mac2_5, r_recip_5, r_lzcr_5,
+		r_shift_5, r_branch_5);
+
+	/* === ATOM 6a: populate (m[][] from ux/uy/uz, t[]=0) === */
+	U4 const r_look_at_6a = R_T0;  /* tape pop → look_at* */
+	U4 const r_scratch_6a = R_ResolveScratch;
+	U4 const r_pux_6a      = R_T1;
+	U4 const r_puy_6a      = R_T3;
+	U4 const r_puz_6a      = R_T5;
+	U4 const r_tmp0_6a     = R_T2;
+	U4 const r_tmp1_6a     = R_T6;
+	U4 const r_tmp2_6a     = R_V0;
+	smem.resolve_look_at_atom_addrs[6] = resolve_look_at__populate_proc(& ab,
+		r_look_at_6a, r_scratch_6a,
+		r_pux_6a, r_puy_6a, r_puz_6a,
+		r_tmp0_6a, r_tmp1_6a, r_tmp2_6a);
+
+	/* === ATOM 6a.5: set_gte_mt3s2s4 (BAKED — ctc2 RT matrix) ===
+	 * This is a BAKED atom from gte.atom.c. Its body hardcodes R_T3 as
+	 * the matrix pointer (popped from tape). It does NOT need GPR
+	 * assignment from us — it has its own internal GPR usage.
+	 * We just take its address. */
+	smem.resolve_look_at_atom_addrs[7] = (MipsAtom*) & set_gte_mt3s2s4;
+
+	/* === ATOM 6b: matrix_vector (RT * (-eye) >> 12) ===
+	 * Uses mac_apply_matrix_lv component macro which internally uses
+	 * r_t0 for the RT matrix load + V0 load, then r_t0/r_t1/r_t2
+	 * for the mfc2/store. We pass our GPRs. */
+	U4 const r_scratch_6b = R_ResolveScratch;
+	U4 const r_peye_6b    = R_T1;  /* scratch+96 (packed V0 dst, then off dst) */
+	U4 const r_look_at_6b = R_T0;  /* tape pop → look_at* */
+	U4 const r_tmp0_6b    = R_T2;
+	U4 const r_tmp1_6b    = R_T3;
+	U4 const r_tmp2_6b    = R_T5;
+	smem.resolve_look_at_atom_addrs[8] = resolve_look_at__matrix_vector_proc(& ab,
+		r_scratch_6b, r_peye_6b, r_look_at_6b,
+		r_tmp0_6b, r_tmp1_6b, r_tmp2_6b);
+
+	/* === ATOM 6c: trans_matrix (off → look_at->t[]) === */
+	U4 const r_look_at_6c = R_T0;  /* tape pop → look_at* */
+	U4 const r_scratch_6c = R_ResolveScratch;
+	U4 const r_off_ptr_6c = R_T1;  /* &scratch.eye (= off dst) */
+	U4 const r_tmp0_6c    = R_T2;
+	smem.resolve_look_at_atom_addrs[9] = resolve_look_at__trans_matrix_proc(& ab,
+		r_look_at_6c, r_scratch_6c, r_off_ptr_6c, r_tmp0_6c);
+
+	/* Sanity check: arena didn't overflow. */
+	assert(ab.used <= ResolveLookAtArena_Size);
+}
+
+/* Emit the resolve_look_at bundle into the tape. Called once per frame from update().
+ * The 7 chain atoms are pre-built at init time (resolve_look_at_init) and referenced by address via smem.resolve_look_at_atom_addrs[].
+ * Per-frame work: 7 tb_emit (atom pointer emissions) + 5 tb_data (C-side pointers for atom 0 + look_at for atom 6).
+ *
+ * Binds_ contract (the field-name labels are for human readability):
+ *   Atom 0  input_and_sub              target(4) eye(4) up_in(4) scratch_base(4) = 4 words
+ *   Atoms 1-5                           (no tape data — atom uses r_scratch + offset internally)
+ *   Atom 6  populate_and_translate     look_at(4)                                = 1 word
+ *                                       ----
+ *                                       5 tb_data words total per frame.
+ */
+I_ void resolve_look_at(
+		TapeBuilder_R tb
+	,	MT3_S2S4* look_at
+	,	P3_S4*    eye
+	,	P3_S4*    target
+	,	V3_S4*    up_in
+){
+	tb_emit(tb, smem.resolve_look_at_atom_addrs[0]); {
+		tb_data(tb, u4_(target));
+		tb_data(tb, u4_(eye));
+		tb_data(tb, u4_(up_in));
+		tb_data(tb, u4_(smem.scratchpad));
+	}
+
+	tb_emit(tb, smem.resolve_look_at_atom_addrs[1]); { }
+	tb_emit(tb, smem.resolve_look_at_atom_addrs[2]); { }
+	tb_emit(tb, smem.resolve_look_at_atom_addrs[3]); { }
+	tb_emit(tb, smem.resolve_look_at_atom_addrs[4]); { }
+	tb_emit(tb, smem.resolve_look_at_atom_addrs[5]); { }
+
+	tb_emit(tb, smem.resolve_look_at_atom_addrs[6]); {
+		tb_data(tb, u4_(look_at));
+	}
+	tb_emit(tb, smem.resolve_look_at_atom_addrs[7]); {
+		tb_data(tb, u4_(look_at));
+	}
+	tb_emit(tb, smem.resolve_look_at_atom_addrs[8]); {
+		tb_data(tb, u4_(look_at));
+	}
+	tb_emit(tb, smem.resolve_look_at_atom_addrs[9]); {
+		tb_data(tb, u4_(look_at));
+	}
 }
 
 GCC_OPTIMIZATION_DISABLE
@@ -160,7 +418,7 @@ void update(PrimitiveArena* pa, U4* ordering_buf)
 {
 	TapeBuilder tb = tb_make(slice_ut_arr(smem.MemTape));
 
-	if (1) // Pad Input
+	// Pad Input
 	{
 		tb.used = 0; tb_scope_run(& tb) {
 			// Grab latest state from bios.
@@ -170,11 +428,15 @@ void update(PrimitiveArena* pa, U4* ordering_buf)
 			tb_emit_(pad_bios_snapshot);
 				tb_data_(raw,   & smem.pad_raw[1]);
 				tb_data_(state, & smem.pad[1]);
-			// Demo input
-			tb_emit_(pad_apply_input);
-				tb_data_(state,     & smem.pad[0]);
-				tb_data_(cube_rot,  & smem.cube.rot);
-				tb_data_(floor_rot, & smem.floor.rot);
+
+			tb_emit_(pad_input_cam);
+				tb_data_(state, & smem.pad[0]);
+				tb_data_(cam, & smem.cam);
+
+			// tb_emit_(pad_input_cube_rotation);
+			// 	tb_data_(state,     & smem.pad[0]);
+			// 	tb_data_(cube_rot,  & smem.cube.rot);
+			// 	tb_data_(floor_rot, & smem.floor.rot);
 		}
 	}
 
@@ -201,15 +463,31 @@ void update(PrimitiveArena* pa, U4* ordering_buf)
 	A2_S2 p;    //???
 	S4 flag; //????
 
+	B4 use_c11_path = false;
+	if (use_c11_path) {
+		camera_look_at_c11(& smem.cam, & smem.cube.pos, & v3s4(0, -fp_one, 0));
+	}
+	if (use_c11_path == false)
+	{
+		tb.used = 0; tb_scope_run(& tb) {
+			resolve_look_at(& tb, & smem.cam.look_at, & smem.cam.pos, & smem.cube.pos, & v3s4(0, -fp_one, 0));
+		}
+	}
 
 	// Draw cube
 	if (1)
 	{
-		m3s2_rotation   (& smem.cube.rot,    & smem.tform_world);
-		m3s2_translation(& smem.tform_world, & smem.cube.pos);
-		m3s2_scale      (& smem.tform_world, & smem.cube.scale);
-		gte_matrix_set_rotation   (& smem.tform_world);
-		gte_matrix_set_translation(& smem.tform_world);
+		mt3s2s4_rotation   (& smem.cube.rot,    & smem.tform_world);
+		mt3s2s4_translation(& smem.tform_world, & smem.cube.pos);
+		mt3s2s4_scale      (& smem.tform_world, & smem.cube.scale);
+
+		// Combine world and look_at matrix.
+		gte_comp_coord_m3s2(& smem.cam.look_at, & smem.tform_world, & smem.tform_view);
+		gte_matrix_set_rotation   (& smem.tform_view);
+		gte_matrix_set_translation(& smem.tform_view);
+
+		// gte_matrix_set_rotation   (& smem.tform_world);
+		// gte_matrix_set_translation(& smem.tform_world);
 
 		U4 prim_base   = u4_(pa->buf[smem.active_buf_id]);
 		U4 prim_cursor = prim_base + pa->used;
@@ -230,16 +508,22 @@ void update(PrimitiveArena* pa, U4* ordering_buf)
 				tb_data(& tb, u4_(& pa->used));
 				tb_data(& tb, prim_base);
 		}
-		tape_run(tb_slice(tb));
+		tape_run_a02_s07(tb_slice(tb));// Fire off the tape (bigger-clobber variant).
 
 		// smem.cube.rot.y += 30;
 	}
 	// Draw floor
 	if (1)
 	{
-		m3s2_rotation   (& smem.floor.rot,   & smem.tform_world);
-		m3s2_translation(& smem.tform_world, & smem.floor.pos);
-		m3s2_scale      (& smem.tform_world, & smem.floor.scale);
+		mt3s2s4_rotation   (& smem.floor.rot,   & smem.tform_world);
+		mt3s2s4_translation(& smem.tform_world, & smem.floor.pos);
+		mt3s2s4_scale      (& smem.tform_world, & smem.floor.scale);
+
+		// Combine world and look_at matrix.
+		gte_comp_coord_m3s2(& smem.cam.look_at, & smem.tform_world, & smem.tform_view);
+
+		gte_matrix_set_rotation   (& smem.tform_view);
+		gte_matrix_set_translation(& smem.tform_view);
 
 		U4 prim_base   = u4_(pa->buf[smem.active_buf_id]);
 		U4 prim_cursor = prim_base + pa->used;
@@ -249,8 +533,8 @@ void update(PrimitiveArena* pa, U4* ordering_buf)
 
 		// Prepare the tape. (Push protocol to tape)
 		tb.used = 0; tb_scope(& tb) {
-			tb_emit(& tb, set_gte_world);
-				tb_data(& tb, u4_(& smem.tform_world));
+			// tb_emit(& tb, set_gte_mt3s2s4);
+			// 	tb_data(& tb, u4_(& smem.tform_view));
 
 			tb_emit(& tb, rbind_floor_f3_face);
 			// TODO(Ed): Just use a single context struct ref?
@@ -266,7 +550,7 @@ void update(PrimitiveArena* pa, U4* ordering_buf)
 				tb_data(& tb, u4_(& pa->used));
 				tb_data(& tb, prim_base);
 		}
-		tape_run(tb_slice(tb));// Fire off the tape.
+		tape_run_a02_s07(tb_slice(tb));// Fire off the tape (bigger-clobber variant).
 
 		// C-side state (pa->used) has already been updated by the tape!
 		// smem.floor.rot.y += 5;
@@ -293,9 +577,11 @@ GCC_OPTIMIZATION_DISABLE
 int main(void)
 {
 	smem = (SMemory){0};
-	smem.scratchpad = C_(U4_V, 0x1F800000);
+	// TODO(Ed): remove this field we don't need it in smem.
+	smem.scratchpad = C_(U4_V, Scratchpad_Loc);
 	// smem.primitives.used = 0;
 	// smem.active_buf_id   = 0;
+	smem.cam.pos = v3s4(500, -1000, -1500);
 	/*Persistent Entity Setup*/{
 		ent_cube128_init(& smem.cube.verts, & smem.cube.faces); {
 			Ent_Cube* cube = & smem.cube;
@@ -315,6 +601,10 @@ int main(void)
 		reset_graph(0);
 		/* Direct BIOS: poll both ports during VBlank. */
 		pad_bios_init_start(& smem.pad_raw[0], & smem.pad_raw[1]);
+
+		/* Pre-build the resolve_look_at bundle atoms into the static arena. */
+		resolve_look_at_init();
+
 		/* Pinned registers for the GPU init atom. */
 		register U4*           io_base_addr rgcc(R_IO_BaseAddr) = u4_r(IO_BASE_ADDR);
 		register DoubleBuffer* screen_buf   rgcc(R_ScreenBuf)   = & smem.screen_buf;
@@ -334,3 +624,4 @@ int main(void)
 	return 0;
 }
 GCC_OPTIMIZATION_ENABLE
+

code/hello_camera/hello_camera.h

@@ -21,12 +21,6 @@ enum {
 	ScreenRes_CenterY = (ScreenRes_Y >> 1),
 };
 
-enum {
-	fp_one = (1 << 12),
-};
-
-#define v3s4_fp_one() v3s4(fp_one, fp_one, fp_one)
-
 typedef U4 OrderingTable_Buffer[OrderingTbl_Len];
 typedef Array_(OrderingTable_Buffer, 2);
 
@@ -67,7 +61,7 @@ I_ void ent_cube128_init(A8_V3_S2* verts, A6_V4_S2* faces) {
 typedef Struct_(Ent_Cube) {
 	V3_S4 accel;
 	V3_S4 vel;
-	V3_S4 pos;
+	V3_S4 pos; // RGA(Lengyel): affine point with implicit weight one. Storage alias of V3_S4.
 	V3_S4 scale;
 	V3_S2 rot;
 	A8_V3_S2 verts;
@@ -94,9 +88,15 @@ I_ void ent_floor_init(A4_V3_S2* verts, A2_V3_S2* faces) {
 };
 typedef Struct_(Ent_Floor) {
 	V3_S4 accel;
-	V3_S4 pos;
+	V3_S4 pos; // RGA(Lengyel): affine point with implicit weight one. Storage alias of V3_S4.
 	V3_S4 scale;
 	V3_S2 rot;
 	A4_V3_S2 verts;
 	A2_V3_S2 faces;
 };
+
+typedef Struct_(Camera) {
+	P3_S4    pos; // RGA(Lengyel): affine point with implicit weight one. Storage alias of V3_S4.
+	V3_S2    rot;
+	MT3_S2S4 look_at;
+};

code/hello_joypad/hello_joypad.atom.c

@@ -24,8 +24,8 @@ ATOM_FILE_DEBUGGER_LINE_MARKER(hello_joypad_atom_c);
 
 #pragma region MACs (Mips Atom components)
 
-FI_ Slice_MipsCode ac_put_disp_env(U4 reg_transfer, U4 reg_base, U2 port)
-MipsAtomComp_Proc_(ac_put_disp_env, {
+FI_ Slice_MipsCode ac_put_disp_env(MipsAtomBuilder_R ab, U4 reg_transfer, U4 reg_base, U2 port)
+MipsAtomComp_Proc_(ac_put_disp_env, ab, {
 	// Emits 5 GP0 commands for buffer 0 (display_area = (0,0,320,240)).
 	// Sequence per libpsyx PutDispEnv: DrawArea TL → DrawArea BR → Mask → DrawArea TL → DrawArea BR
 	mac_gcmd_push(gp0_word_draw_area_top_left_origin,      reg_transfer, reg_base, port),
@@ -35,8 +35,8 @@ MipsAtomComp_Proc_(ac_put_disp_env, {
 	mac_gcmd_push(gp0_word_draw_area_bottom_right_320x240, reg_transfer, reg_base, port),
 })
 
-FI_ Slice_MipsCode ac_put_draw_env(U4 reg_transfer, U4 reg_base, U2 port)
-MipsAtomComp_Proc_(ac_put_draw_env, {
+FI_ Slice_MipsCode ac_put_draw_env(MipsAtomBuilder_R ab, U4 reg_transfer, U4 reg_base, U2 port)
+MipsAtomComp_Proc_(ac_put_draw_env, ab, {
 	/*
 	* ORIGIN: each code word corresponds to the EXACT value libpsyx's PutDrawEnv function would compute for the same DrawEnv settings.
 	* References:
@@ -116,7 +116,7 @@ internal MipsAtom_(screen_env_init) atom_info(atom_phase(screen_init)
 	store_word(R_0, R_ScreenBuf, O_(DisplayEnv,vinterlace) + OA_(DoubleBuffer,display,1)),
 
 	mac_store_rects2(R_0, R_ScreenY, R_ScreenX, R_ScreenY, R_ScreenBuf, O_(DrawEnv,clip_area)         + OA_(DoubleBuffer,draw,0)), /* draw[0].clip_area = (0, 240, 320, 240). C11's SetDefDrawEnv writes clip.y = y_arg. */
-	mac_store_v2s2(  R_0, R_ScreenY,                       R_ScreenBuf, O_(DrawEnv,drawing_offset[0]) + OA_(DoubleBuffer,draw,0)), /* draw[0].drawing_offset[0] = (0, 240); C11 passes y_arg as ofs. */
+	mac_store_v2s2(R_0, R_ScreenY,                       R_ScreenBuf, O_(DrawEnv,drawing_offset[0]) + OA_(DoubleBuffer,draw,0)), /* draw[0].drawing_offset[0] = (0, 240); C11 passes y_arg as ofs. */
 
 	mac_store_v2s2(R_ScreenX, R_ScreenY, R_ScreenBuf, O_(DrawEnv,clip_area.width) + OA_(DoubleBuffer,draw,1)),
 
@@ -286,7 +286,7 @@ MipsAtom_(floor_f3_face) atom_info(atom_phase(floor_f3)
 	, atom_reads( R_PrimCursor, R_FaceCursor, R_VertBase, R_OtBase)
 	, atom_writes(R_PrimCursor, R_FaceCursor)
 ) {
-	mac_load_tri_indices(  R_FaceCursor, R_T0, R_T1, R_T2),
+	mac_load_tri_indices(R_FaceCursor, R_T0, R_T1, R_T2),
 	mac_gte_load_tri_verts(R_VertBase,   R_T0, R_T1, R_T2),
 	nop2, gte_cmdw_rotate_translate_perspective_triple, // 2 nops retire the final cpu -> gte writes before RTPT
 	gte_cmdw_nclip,

code/hello_joypad/sio.tape.c

@@ -24,8 +24,8 @@
  * Emits 9 instructions (status/buttons/axes/attempt stores plus the
  * two-instruction zero-extended buttons load).
  */
-FI_ Slice_MipsCode ac_pad_sio_write_pad_state(U4 status_val, U4 state_ptr_reg, U4 scratch_reg)
-MipsAtomComp_Proc_(ac_pad_sio_write_pad_state, {
+FI_ Slice_MipsCode ac_pad_sio_write_pad_state(MipsAtomBuilder_R ab, U4 status_val, U4 state_ptr_reg, U4 scratch_reg)
+MipsAtomComp_Proc_(ac_pad_sio_write_pad_state, ab, {
 	add_ui(scratch_reg, R_0, status_val),
 	store_word(scratch_reg, state_ptr_reg, O_(PadState,status)),
 	/* FIX 2026-08-02: buttons = 0x0000FFFF = "no buttons pressed" in

scripts/duffle.lua

@@ -217,7 +217,7 @@ local function parse_path_root(input)
 		if not server_end or server_end == server_start then
 			error("UNC path requires //server/share: " .. input, 3)
 		end
-		local server = input:sub(server_start, server_end - 1)
+		local server      = input:sub(server_start, server_end - 1)
 		local share_start = server_end + 1
 		while input:sub(share_start, share_start) == "/" do
 			share_start = share_start + 1
@@ -515,8 +515,7 @@ local function splice_c_lines(source)
 		local splice_len = nil
 		if byte == BYTE_BACKSLASH and source:byte(pos + 1) == BYTE_NEWLINE then
 			splice_len = 2
-		elseif byte == BYTE_BACKSLASH and source:byte(pos + 1) == BYTE_CR
-			and source:byte(pos + 2) == BYTE_NEWLINE then
+		elseif byte == BYTE_BACKSLASH and source:byte(pos + 1) == BYTE_CR and source:byte(pos + 2) == BYTE_NEWLINE then
 			splice_len = 3
 		end
 
@@ -1053,6 +1052,8 @@ M.GTE_COMMAND_ALIASES = {
 	-- gte_avg_sort_z3 / gte_avg_sort_z4 are the duffle-side aliases for AVSZ3/4.
 	["gte_avg_sort_z3"]                              = "gte_cmdw_avsz3",
 	["gte_avg_sort_z4"]                              = "gte_cmdw_avsz4",
+	["gte_cmdw_sqr"]                                 = "gte_cmdw_sqr",
+	["gte_cmdw_gpf"]                                 = "gte_cmdw_gpf",
 }
 
 -- GTE command input-set table.
@@ -1136,6 +1137,14 @@ M.GTE_COMMAND_INPUTS = {
 		"C2_SZ0", "C2_SZ1", "C2_SZ2", "C2_SZ3",
 		"gte_cr_ZSF4",
 	},
+	-- SQR: reads IR1..IR3 (per PSX-SPX gte.md SQR section; libgte disassembly 0x800160b0).
+	["gte_cmdw_sqr"] = {
+		"C2_IR1", "C2_IR2", "C2_IR3",
+	},
+	-- GPF: reads IR0 + IR1..IR3 (per PSX-SPX gte.md GPF section; libgte disassembly 0x8001613c).
+	["gte_cmdw_gpf"] = {
+		"C2_IR0", "C2_IR1", "C2_IR2", "C2_IR3",
+	},
 }
 
 -- GTE command output-set + semantic role table.
@@ -1208,6 +1217,22 @@ M.GTE_COMMAND_OUTPUTS = {
 		{ register = "C2_IR2", role = "latest_color" },
 		{ register = "C2_IR3", role = "latest_color" },
 	},
+	["gte_cmdw_sqr"] = {
+		{ register = "C2_MAC1", role = "mac_result" },
+		{ register = "C2_MAC2", role = "mac_result" },
+		{ register = "C2_MAC3", role = "mac_result" },
+		{ register = "C2_IR1",  role = "latest_color" },
+		{ register = "C2_IR2",  role = "latest_color" },
+		{ register = "C2_IR3",  role = "latest_color" },
+	},
+	["gte_cmdw_gpf"] = {
+		{ register = "C2_MAC1", role = "mac_result" },
+		{ register = "C2_MAC2", role = "mac_result" },
+		{ register = "C2_MAC3", role = "mac_result" },
+		{ register = "C2_IR1",  role = "latest_color" },
+		{ register = "C2_IR2",  role = "latest_color" },
+		{ register = "C2_IR3",  role = "latest_color" },
+	},
 }
 
 -- GTE command/post-command latch-window table.
@@ -1270,6 +1295,37 @@ M.GTE_COMMAND_LATCH_WINDOWS = {
 		{ register = "C2_IR2", required = 4 },
 		{ register = "C2_IR3", required = 4 },
 	},
+	["gte_cmdw_sqr"] = {
+		{ register = "C2_MAC1", required = 4 },
+		{ register = "C2_MAC2", required = 4 },
+		{ register = "C2_MAC3", required = 4 },
+		{ register = "C2_IR1",  required = 4 },
+		{ register = "C2_IR2",  required = 4 },
+		{ register = "C2_IR3",  required = 4 },
+	},
+	["gte_cmdw_gpf"] = {
+		{ register = "C2_MAC1", required = 4 },
+		{ register = "C2_MAC2", required = 4 },
+		{ register = "C2_MAC3", required = 4 },
+		{ register = "C2_IR1",  required = 4 },
+		{ register = "C2_IR2",  required = 4 },
+		{ register = "C2_IR3",  required = 4 },
+	},
+}
+
+--- GTE control-register alias groups.
+--- Aliases within a group write to the same C2 control-register slot on real silicon
+--- (the silicon double-maps some C2 slots across multiple PSX SDK / libgte conventions).
+--- Aliases across groups write to distinct C2 slots.
+---
+--- Cross-alias writes inside one atom body, or across the wave-context boundary,
+--- silently clobber each other. The `check_gte_cr_alias_writes` check warns about
+--- each pair per source. See `docs/gte_reference.md` §"Control-register alias table"
+--- for the silicon rationale and the libgte outer-product convention.
+M.GTE_CR_ALIAS_GROUPS = {
+	{ 24, { "gte_cr_RBK", "gte_cr_OFX" } },   -- background R vs screen offset X
+	{ 25, { "gte_cr_GBK", "gte_cr_OFY" } },   -- background G vs screen offset Y
+	{ 26, { "gte_cr_BBK", "gte_cr_H"   } },   -- background B vs projection plane distance H
 }
 
 -- Operand-class table for the COP2->GPR load-delay check.
@@ -1285,6 +1341,7 @@ M.GTE_COMMAND_LATCH_WINDOWS = {
 M.OPERAND_READ_POSITIONS = {
 	-- CPU ALU with one or two GPR operands. Reads every GPR operand.
 	["add_ui"]                 = {1, 2},
+	["li_s"]                   = {1, 2},  -- rt (write), imm16 (immediate)
 	["add_ui_self"]            = {1},
 	["add_si"]                 = {1, 2},
 	["add_u"]                  = {1, 2, 3},
@@ -1354,6 +1411,8 @@ M.OPERAND_READ_POSITIONS = {
 	["gte_mv_to_ctrl_r"]       = {},
 	["gte_lw"]                 = {},
 	["gte_sw"]                 = {},
+	["shift_lleft_var"]        = {1, 2, 3},  -- rd, rt, rs (variable shift amount)
+	["shift_aright_var"]       = {1, 2, 3},
 }
 
 -- GP0 packet sizes (total words including the 1-word tag) per GP0 cmd byte.
@@ -1435,8 +1494,10 @@ M.INSTRUCTION_LATENCY = {
 	["xor_i"]               = 1,  ["xor_u"]           = 1,
 	["nor_u"]               = 1,
 	["shift_lleft"]         = 1,  ["shift_lleft_self"]  = 1,
+	["shift_lleft_var"]     = 1,  -- sllv: 1 cycle
 	["shift_lright"]        = 1,
 	["shift_aright"]        = 1,
+	["shift_aright_var"]    = 1,  -- srav: 1 cycle
 	["mask_upper"]          = 1,
 	["mov_from_high"]       = 2,  -- mfhi: 2 cycles
 	["mov_from_low"]        = 2,  -- mflo: 2 cycles
@@ -1454,6 +1515,7 @@ M.INSTRUCTION_LATENCY = {
 	["load_half_u"]         = 1,  ["load_half"]   = 1,
 	["load_byte_u"]         = 1,  ["load_byte"]   = 1,
 	["load_upper_i"]        = 1,
+	["li_s"]                = 1,  -- aliased to add_ui(rt, R_0, imm); 1 cycle
 	-- 2-word loads (lui + ori) used for >16-bit immediates
 	["load_imm"]                = 2,
 	["load_imm_1w"]             = 1,
@@ -1497,6 +1559,8 @@ M.INSTRUCTION_LATENCY = {
 	["gte_cmdw_op"]            = 6,   -- OP: 6 cycles (PSX-SPX)
 	["gte_cmdw_outer_product"] = 6,   -- alias for OP
 	["gte_cmdw_wedge"]         = 6,   -- alias for OP
+	["gte_cmdw_sqr"]           = 5,   -- SQR(sf): 5 cycles (PSX-SPX); +2 nops for pre-fill if sf=0/1
+	["gte_cmdw_gpf"]           = 5,   -- GPF(sf,lm): 5 cycles (PSX-SPX); +2 nops for pre-fill if needed
 	-- Long-form aliases (same cycle cost as their short form)
 	["gte_cmdw_rotate_translate_perspective_single"] = 15,  -- alias for rtps
 	["gte_cmdw_rotate_translate_perspective_triple"] = 23,  -- alias for rtpt
@@ -1777,6 +1841,7 @@ M.CU2_TRANSITION_POLICY = {
 M.INSTRUCTION_GPR_EFFECTS = {
 	-- CPU ALU with one or two GPR operands. Reads every GPR operand position.
 	add_ui                  = { reads = {1, 2}, writes = {1} },
+	li_s                    = { reads = {1, 2}, writes = {1} },  -- RMW: rt is both read + written
 	add_ui_self             = { reads = {1},    writes = {1} },
 	add_si                  = { reads = {1, 2}, writes = {1} },
 	add_u                   = { reads = {2, 3}, writes = {1} },
@@ -1893,6 +1958,8 @@ M.INSTRUCTION_GPR_EFFECTS = {
 	atom_writes             = { reads = {},     writes = {}  },
 	-- mac_yield transfers control to the next atom; zero GPR effects.
 	mac_yield               = { reads = {},     writes = {}  },
+	shift_lleft_var         = { reads = {2, 3}, writes = {1} },
+	shift_aright_var        = { reads = {2, 3}, writes = {1} },
 }
 
 -- Bounded GPR-value rules consumed by the same forward event walk as `INSTRUCTION_GPR_EFFECTS`.
@@ -1903,18 +1970,19 @@ M.INSTRUCTION_GPR_EFFECTS = {
 --   * passes/static_analysis.lua::apply_gpr_effects
 -- No second `bounded_value_pass` is permitted.
 M.GPR_VALUE_RULES = {
-	load_upper_i = { op = "load_upper_i", dest = 1,             immediate = 2, },
-	add_ui       = { op = "add_ui",       dest = 1, source = 2, immediate = 3, },
-	or_i         = { op = "or_i",         dest = 1, source = 2, immediate = 3, },
-	and_i        = { op = "and_i",        dest = 1, source = 2, immediate = 3, },
-	xor_i        = { op = "xor_i",        dest = 1, source = 2, immediate = 3, },
-	add_ui_self  = { op = "add_ui",       dest = 1, source = 1, immediate = 2, },
-	or_i_self    = { op = "or_i",         dest = 1, source = 1, immediate = 2, },
+	load_upper_i     = { op = "load_upper_i", dest = 1,             immediate = 2, },
+	add_ui           = { op = "add_ui",       dest = 1, source = 2, immediate = 3, },
+	li_s             = { op = "add_ui",       dest = 1, source = 2, immediate = 3 },  -- R_0 + sign-ext(imm) folds into a constant
+	or_i             = { op = "or_i",         dest = 1, source = 2, immediate = 3, },
+	and_i            = { op = "and_i",        dest = 1, source = 2, immediate = 3, },
+	xor_i            = { op = "xor_i",        dest = 1, source = 2, immediate = 3, },
+	add_ui_self      = { op = "add_ui",       dest = 1, source = 1, immediate = 2, },
+	or_i_self        = { op = "or_i",         dest = 1, source = 1, immediate = 2, },
 	-- Present register-form self variants. They are included here so a
 	-- known value is not needlessly lost when these encoders are used.
-	add_u_self       = { op = "add_u",       dest = 1, sources = {1, 2}, },
-	or_u_self        = { op = "or",          dest = 1, sources = {1, 2}, },
-	shift_lleft_self = { op = "shift_lleft", dest = 1, source = 1, immediate = 2, },
+	add_u_self       = { op = "add_u",        dest = 1, sources = {1, 2}, },
+	or_u_self        = { op = "or",           dest = 1, sources = {1, 2}, },
+	shift_lleft_self = { op = "shift_lleft",  dest = 1, source = 1, immediate = 2, },
 }
 
 -- Control-transfer (branch/jump/call) delay-slot policy table.
@@ -2041,7 +2109,8 @@ local E_MAC_PREFIX_LEN = 4
 ---   * Unknown `mac_X` (not in `component_index`): fall back to `word_counts[ident]` if present; otherwise emit one opaque event so the cycle budget accounts for the word.
 ---   * Marker Tokens (`atom_label(...)` / `atom_offset(...)`): Zero events (they are pure metaprogram hints).
 ---
---- Cycle protection: a per-expansion `visiting` set tracks components currently on the expansion stack; a re-entry produces a deterministic `{kind = "cycle", ...}` error and aborts that branch (does NOT hang, does NOT recurse).
+--- Cycle protection: a per-expansion `visiting` set tracks components currently on the expansion stack;
+--- a re-entry produces a deterministic `{kind = "cycle", ...}` error and aborts that branch (does NOT hang, does NOT recurse).
 ---
 --- Pure: reads `body_entry` / `component_index` / `word_counts`. Memoization is the caller's responsibility.
 --- Callers wanting `word_events` / `word_event_errors` precomputed for many atoms should memoize them per atom.

scripts/duffle_paths.lua

@@ -47,15 +47,14 @@ local function find_repo_root()
 	return root
 end
 
---- Set `package.path` (for `require("duffle")` + `require("passes.X")`) and
---- `package.cpath` (for `lpeg.dll`).
+--- Set `package.path` (for `require("duffle")` + `require("passes.X")`) and `package.cpath` (for `lpeg.dll`).
 ---
 --- This script does NOT touch the OS environment: no `os.setenv`, no `os.putenv`, no `$PATH` mods. 
 --- It just sets `package.path` and `package.cpath` (the standard Lua way to register module search dirs). 
 --- lpeg is built by `update_deps.ps1` to `toolchain/lpeg/`, 
 --- which we wire into `package.cpath` here (so `require("lpeg")` from `duffle.lua` resolves without any global state).
 function M.setup()
-	local repo_root = find_repo_root()
+	local  repo_root = find_repo_root()
 	if not repo_root then
 		-- Unreachable in practice: find_repo_root() derives the repo root from this script's
 		-- own source path via debug.getinfo(1, "S").source (no subprocess, no git CLI, <1ms).

scripts/passes/auto_reg.lua

@@ -0,0 +1,355 @@
+--- passes/auto_reg.lua — Per-phase automatic GPR allocator + gen/auto_reg.h emitter.
+---
+--- Reads the per-source + corpus-level `atom_auto_regs` + `phase_auto_regs` registries populated by `passes/scan_source.lua`.
+--- Runs a deterministic first-fit allocator in the `R_T0..R_T7 + R_V0..R_V1` pool (10 physical GPRs).
+--- Emits one `#define R_<Sym>_Code R_Tn_Code` per marker into per-directory `gen/auto_reg.h`.
+---
+--- User-pinned GPRs : The corpus's `register_alias_registry` is consulted to exclude GPRs the user has pinned via 
+--- `atom_reg` + `_Code` defs (e.g. carriers like `R_ResolveScratch = R_T4 atom_reg`). 
+--- These GPRs are unavailable to EVERY atom's source pool.
+--- Carriers are preserved across atoms by context discipline and must never be reallocated.
+--- Per-atom body parsing also catches alias references (R_<Alias>) and hardcoded R_Tn references,
+--- so the user can write either `R_T4` or `R_ResolveScratch` in an atom body and the pass will
+--- exclude R_T4 from that atom's pool.
+---
+--- Conflict detection: If the user hardcodes `R_Tn` in an atom body that shares a phase with an auto-reg that picked `R_Tn`,
+--- emit `phase_register_clash` as an info finding (no build stop).
+--- Should be unreachable after the user-pinning + body-parsing fix above; kept as a defensive safety net.
+---
+--- Pool exhaustion: If a phase declares more `R_<Sym>` mappings than the 10-register pool can hold,
+--- emit `phase_register_pool_exhausted` as a build-stopping error.
+
+--- @class AutoRegResult
+--- @field outputs  table[]  -- {kind=, path=} entries
+--- @field errors   table[]  -- {line=, msg=}  entries (build-stops)
+--- @field warnings table[]  -- {line=, msg=}  entries (build-continues)
+
+local _bootstrap_dir = debug.getinfo(1, "S").source:match("^@?(.*[/\\])") or "./"
+local duffle         = dofile(_bootstrap_dir .. "../duffle_paths.lua")
+
+--- ════════════════════════════════════════════════════════════════════════════
+--- THE GPR ALLOCATION POOL — what is allocatable, and (more importantly) WHY
+--- ════════════════════════════════════════════════════════════════════════════
+---
+--- The auto-reg pass picks physical GPRs for `atom_auto_reg(...)` / `phase_auto_reg(...)` markers.
+--- It allocates from a FIXED 10-register pool.
+--- This comment block makes the inclusion AND exclusion criteria obvious so a reader doesn't have 
+--- to grep lottes_tape.h + mips.h to understand the design.
+---
+--- ── WHAT'S IN THE POOL (10 GPRs, all caller-trash per the O32 ABI) ────────
+---     R_T0..R_T7  (GPR codes 8..15), R_V0..R_V1 (GPR codes 2..3)  
+---      The workhorse of every atom body. The uesr should be aware of atom allocation across atoms they chain. 
+---      If they have a collision it means either they didn't saturate the register file optimally for a phase,
+---      or the may have made the workload to large for the run.
+---
+--- ── WHAT'S NOT IN THE POOL — and WHY (the "obvious exclusions") ────────────
+---   R_T9  (GPR code 25)  — R_TapePtr, the tape instruction stream pointer.
+---     Owned by the tape runtime (in tape_run / tape_run_a02_s07).
+---     `rgcc(R_TapePtr)` register-variable ties the C compiler's view to $t9 across the whole tape_run.
+---     The auto-reg pass MUST NOT clobber this; doing so would desync the C-side tape pointer from the
+---     hardware pointer and crash on the next tape_run.
+---
+---   R_T8  (GPR code 24)  — R_AtomJmp, the atom-jump register used by the 4-word yield handshake.
+---     Every `mac_yield()` / `mac_yield_tail` does `load_word R_AtomJmp, R_TapePtr, 0` then
+---     `jump_reg R_AtomJmp`. The auto-reg pass MUST NOT clobber this either, or the atom dispatcher breaks.
+---     Owned by the tape runtime, same family as R_TapePtr.
+---
+---   R_AT  (GPR code 1)   — Assembler temporary. Reserved by the MIPS O32 ABI for pseudoinstruction expansion
+---     (lottes_tape.h:86, mips.h:93). The ISA's psuedo instructions use it as a scratch temporary.
+---
+---   R_A0..A3 (codes 4..7)   — Function arguments. Used in tape_run_a02_s07, see below.
+---   R_S0..S7 (codes 16..23) — Callee-saved. Preserved across C-ABI calls by convention.
+---     The `tape_run_a02_s07` variant clobbers them deliberately, but the default `tape_run` does NOT.
+---     Kept out of POOL to preserve the conservative default.
+---     Add them in a separate "big clobber" pool if/when needed.
+---
+---   R_K0/K1       (codes 26..27) — Kernel / interrupt handler reserves. Never touched by user code; OS-internal.
+---   R_GP/SP/FP/RA (codes 28..31) — Stack frame + return-address. Owned by the C compiler; never allocatable.
+---   R_0           (code 0)       — Hardwired zero. Cannot be written.
+---
+local POOL = {
+    "R_T0", "R_T1", "R_T2", "R_T3",
+    "R_T4", "R_T5", "R_T6", "R_T7",
+    "R_V0", "R_V1",
+}
+
+-- Map from integer MIPS GPR code (the `code` field on AliasEntry) to the physical GPR ident in POOL.
+-- The standard MIPS O32 ABI register numbering matches mips.h's R_*_Code #defines (mips.h).
+-- Only the POOL entries matter for auto_reg — non-pool aliases
+-- (R_AT=1, R_A0..A3=4..7, R_T8=24, R_T9=25, R_K0/K1=26..27, R_GP/SP/FP/RA=28..31) 
+-- are deliberately omitted — see the comment block above for the WHY of each exclusion.
+local INT_CODE_TO_POOL_GPR = {
+    [2]  = "R_V0", [3]  = "R_V1",
+    [8]  = "R_T0", [9]  = "R_T1", [10] = "R_T2", [11] = "R_T3",
+    [12] = "R_T4", [13] = "R_T5", [14] = "R_T6", [15] = "R_T7",
+}
+
+-- Stable sort for deterministic allocation order.
+local function stable_sort_keys(tbl)
+    local keys = {}
+    for k in pairs(tbl) do keys[#keys + 1] = k end
+    table.sort(keys)
+    return keys
+end
+
+-- Allocate one phase's auto-reg mappings.
+-- Returns (allocated_map, errors). On pool exhaustion, errors is populated and the function halts.
+local function allocate_phase(phase_label, decls)
+    -- Deep-copy POOL into a fresh sequence table. The original `table.unpack and table.unpack(POOL) or { unpack(POOL) }`
+    -- idiom wraps the unpacked values in a single inner table under LuaJIT 5.1 (`table.unpack` is nil; the `or` returns one value),
+    -- which corrupts the pool into `{ {R_T0, R_T1, ...} }` — making `table.remove(pool, 1)` return the inner table on iteration.
+    local pool   = {}
+    for i = 1, #POOL do pool[i] = POOL[i] end
+    local result = {}
+    local errors = {}
+    for _, sym in ipairs(stable_sort_keys(decls)) do
+        local next_gpr = table.remove(pool, 1)
+        if not next_gpr then
+            errors[#errors + 1] = {
+                line = 0,
+                msg  = string.format("phase_register_pool_exhausted: "
+									.. "phase '%s' requested symbol '%s' but the pool has no remaining registers "
+									.. "(max 10 per phase: R_T0..R_T7 + R_V0..R_V1). Split the phase or use hardcoded GPRs."
+                  , phase_label, sym),
+            }
+            return result, errors
+        end
+        result[sym] = next_gpr
+    end
+    return result, errors
+end
+
+-- Build two projections from corpus.register_alias_registry:
+--   user_pinned   -- { [physical_gpr_ident] = true } -- GPRs unavailable to auto_reg globally (wave-context carriers, file-scope pinned aliases)
+--   alias_to_gpr  -- { [alias_ident]        = physical_gpr_ident } -- for body parsing
+-- Both projections are derived from the same set of entries: every AliasEntry in register_alias_registry has `has_atom_reg = true` 
+-- (only those entries are added to the registry; see passes/scan_source.lua parse_enum_entry).
+-- Each entry's `code` is the integer MIPS GPR number (0..31); INT_CODE_TO_POOL_GPR translates it back to the physical GPR ident.
+-- Aliases whose `code` points to a non-POOL GPR (e.g. R_S0, R_T8, R_K1) are ignored — 
+-- they don't affect the auto_reg pool, and they're already excluded from POOL above.
+local function build_user_pins(corpus)
+    local user_pinned  = {}
+    local alias_to_gpr = {}
+    if not corpus.register_alias_registry then return user_pinned, alias_to_gpr end
+    for alias_name, alias_entry in pairs(corpus.register_alias_registry) do
+        if alias_entry.has_atom_reg and alias_entry.code then
+            local gpr = INT_CODE_TO_POOL_GPR[alias_entry.code]
+            if gpr then
+                user_pinned[gpr]         = true
+                alias_to_gpr[alias_name] = gpr
+            end
+        end
+    end
+    return user_pinned, alias_to_gpr
+end
+
+-- Find every physical GPR referenced in the atom body, via EITHER:
+--   (a) A hardcoded physical GPR ident (R_T\d+|R_V\d+|R_A\d+|R_S\d+) — the existing regex;
+--   (b) An alias ident (R_<Alias>) resolved via alias_to_gpr back to its physical GPR ident.
+-- Returns { [physical_gpr_ident] = count }. Clash-detection and source-pool-exclusion logic
+-- only needs the presence of each GPR (boolean test), but keeping count preserves the
+-- original find_hardcoded_rn shape so callers can switch without churn.
+-- The alias pattern is sorted lexicographically to keep the regex deterministic.
+local function find_used_gprs(body_text, alias_to_gpr)
+    local found = {}
+    -- (a) Hardcoded physical GPRs (R_T0..R_T7, R_V0..R_V1, R_A0..R_A3, R_S0..R_S7).
+    for gpr in body_text:gmatch("(R_T%d+|R_V%d+|R_A%d+|R_S%d+)") do
+        found[gpr] = (found[gpr] or 0) + 1
+    end
+    -- (b) Alias references (R_<Alias>) resolved to physical GPRs via the registry.
+    --      Sorted by name so the regex is byte-stable across runs.
+    if alias_to_gpr and next(alias_to_gpr) then
+        local aliases = {}
+        for alias_name in pairs(alias_to_gpr) do
+            aliases[#aliases + 1] = alias_name
+        end
+        table.sort(aliases)
+        local pattern = "(" .. table.concat(aliases, "|") .. ")"
+        for alias_name in body_text:gmatch(pattern) do
+            local gpr = alias_to_gpr[alias_name]
+            if gpr and not found[gpr] then
+                found[gpr] = 1
+            end
+        end
+    end
+    return found
+end
+
+-- Emit one gen/auto_reg.h header per directory.
+local function emit_auto_reg_h(out_dir, dir, sources, mappings)
+    if not mappings or next(mappings) == nil then return end
+    local out_path = out_dir .. "/" .. "auto_reg.h"
+    duffle.ensure_dir(out_dir)
+    local lines = {
+        "#ifdef INTELLISENSE_DIRECTIVES",
+        "#pragma once",
+        "#endif",
+        "// Auto-generated by ps1_meta.lua (passes/auto_reg.lua) — DO NOT EDIT",
+        "// Directory: " .. dir:gsub("/", "\\"),
+    }
+    for _, src in ipairs(sources) do
+        lines[#lines + 1] = "//   source: " .. src.path
+    end
+    lines[#lines + 1] = "// Per-phase register allocations resolved by the lua pass."
+    lines[#lines + 1] = "// R_<Sym>_Code = <chosen GPR's _Code constant> for every marker in this directory."
+    lines[#lines + 1] = ""
+    for _, sym in ipairs(stable_sort_keys(mappings)) do
+        local gpr         = mappings[sym]
+        local gpr_code    = gpr .. "_Code"
+        lines[#lines + 1] = "#define " .. sym .. "_Code " .. gpr_code
+    end
+    lines[#lines + 1] = ""
+    duffle.write_file_lf(out_path, table.concat(lines, "\n") .. "\n")
+    print("  -> " .. out_path)
+    return out_path
+end
+
+-- ════════════════════════════════════════════════════════════════════════════
+-- Pass entry
+-- ════════════════════════════════════════════════════════════════════════════
+
+local M = {}
+
+--- @param ctx PassCtx
+--- @return AutoRegResult
+function M.run(ctx)
+    local outputs  = {}
+    local errors   = {}
+    local warnings = {}
+
+    local corpus = ctx.shared and ctx.shared.corpus
+    if type(corpus) ~= "table" then
+        error("auto_reg.run requires ctx.shared.corpus", 0)
+    end
+
+    -- 0. Build the user-pinned GPR exclusion set + alias-to-GPR resolution map.
+    --  Wave-context carriers (e.g. `R_ResolveScratch = R_T4 atom_reg` in hello_camera.atom.c)
+    --  MUST NOT be allocated to any auto-reg marker — they're preserved across atoms by the wave-context discipline.
+		--  The corpus's register_alias_registry is the source of truth for these opt-in pins.
+    --  Body references to those aliases (via alias_to_gpr) are also excluded on a per-atom basis in step 2 below.
+    local user_pinned, alias_to_gpr = build_user_pins(corpus)
+
+    -- 1. Allocate phase pools first (phase declarations take precedence over per-atom declarations).
+    local phase_allocations = {}
+    for phase_label, decls in pairs(corpus.phase_auto_regs or {}) do
+        local mapping, errs = allocate_phase(phase_label, decls)
+        for sym, gpr in pairs(mapping) do
+            phase_allocations[phase_label]      = phase_allocations[phase_label] or {}
+            phase_allocations[phase_label][sym] = gpr
+        end
+        for _, e in ipairs(errs) do
+            errors[#errors + 1] = e
+        end
+    end
+
+    -- 2. Allocate per-atom auto-regs. If the atom scope matches a phase, reuse the phase pool.
+    -- Otherwise, allocate a private pool for the atom.
+    -- The phase membership is in `corpus.atom_phases[phase_label].atoms` (an array of atom names declared via `atom_phase(<phase>)`
+		-- in the atom's `atom_info` line). Build a reverse map `atom_name -> phase_label` so the lookup is O(1) per atom scope.
+    local atom_name_to_phase = {}
+    for phase_label, entry in pairs(corpus.atom_phases or {}) do
+        for _, atom_name in ipairs(entry.atoms or {}) do
+            atom_name_to_phase[atom_name] = phase_label
+        end
+    end
+
+    local atom_allocations = {}
+    for atom_scope, decls in pairs(corpus.atom_auto_regs or {}) do
+        local phase_label = atom_name_to_phase[atom_scope]
+        -- Build the atom's source pool: start with the full POOL, subtract:
+        --   (a) every GPR already committed (phase allocations + prior atom allocations)
+        --   (b) every USER-PINNED GPR (wave-context carriers + file-scope pinned aliases)
+        --   (c) every GPR referenced in the atom's body — either hardcoded R_X or alias R_Xxx
+        --       (the latter resolved via alias_to_gpr; this catches cases where the user wrote R_ResolveScratch instead of R_T4 directly)
+        -- Atoms whose scope matches a phase share the global pool with the phase allocations;
+        -- the original `source_pool = phase_allocations[phase_label]` form used the phase
+        -- allocation MAP as a pool, but that map has no array part, so `table.remove(source_pool, 1)`
+        -- returned nil and every atom-with-phase marker errored with `phase_register_pool_exhausted`.
+        local used = {}
+        for _, m in pairs(phase_allocations) do for _, gpr in pairs(m) do used[gpr] = true end end
+        for _, m in pairs(atom_allocations)  do for _, gpr in pairs(m) do used[gpr] = true end end
+        -- (c) Body references — scan the atom body for hardcoded + alias-resolved GPRs.
+        --     Folded into `used` so the source_pool exclusion is a single check.
+        local atom = corpus.atoms_by_name and corpus.atoms_by_name[atom_scope]
+        if atom and atom.body then
+            local body_used = find_used_gprs(atom.body, alias_to_gpr)
+            for gpr in pairs(body_used) do used[gpr] = true end
+        end
+        local source_pool = {}
+        for _, gpr in ipairs(POOL) do
+            -- Exclude (a) prior commitments, (b) USER-PINNED GPRs (wave-context carriers
+            -- declared via atom_reg + _Code defs, preserved across atoms globally).
+            if not used[gpr] and not user_pinned[gpr] then
+                source_pool[#source_pool + 1] = gpr
+            end
+        end
+        local result = {}
+        for _, sym in ipairs(stable_sort_keys(decls)) do
+            local next_gpr = table.remove(source_pool, 1)
+            if not next_gpr then
+                errors[#errors + 1] = {
+                    line = 0,
+                    msg  = string.format("phase_register_pool_exhausted: atom '%s' requested symbol '%s' "
+											.. "but no free registers remain in its scope pool."
+                    	, atom_scope, sym),
+                }
+            else
+                result[sym] = next_gpr
+            end
+        end
+        atom_allocations[atom_scope] = result
+    end
+
+    -- 3. Conflict-with-hardcoded detection (defensive — should be unreachable now).
+    -- The source_pool exclusion in step 2 (b) + (c) already accounts for both user-pinned GPRs
+    -- and body-referenced GPRs (hardcoded R_Tn OR alias R_<Alias>).
+		-- An auto-reg allocation that matched an existing body reference would be impossible by construction.
+		-- This warning is kept as a defensive safety net for cases the body scanner might miss
+		-- (e.g. macros that expand to register references the scanner cannot resolve).
+    -- For each resolved (scope, sym) -> R_Tn mapping, scan the atom body source for used GPRs.
+    for atom_scope, decls in pairs(atom_allocations) do
+        local atom = corpus.atoms_by_name and corpus.atoms_by_name[atom_scope]
+        if atom and atom.body then
+            local used_in_body = find_used_gprs(atom.body, alias_to_gpr)
+            for sym, allocated_gpr in pairs(decls) do
+                if used_in_body[allocated_gpr] and used_in_body[allocated_gpr] > 0 then
+                    warnings[#warnings + 1] = {
+                        line  = atom.line or 0,
+                        msg   = string.format("phase_register_clash: atom '%s' has hardcoded '%s' in its body AND an auto-reg marker '%s' "
+													.. "that was allocated to '%s' (same phase). Resolve by removing the hardcoded reference or renaming the auto-reg."
+                        	, atom_scope, allocated_gpr, sym, allocated_gpr),
+                    }
+                end
+            end
+        end
+    end
+
+    -- 4. Emit per-directory gen/auto_reg.h.
+    -- For each source directory that has atom_auto_regs or phase_auto_regs entries, emit one header.
+    local sources_by_dir = corpus.sources_by_dir or {}
+    for dir, sources in pairs(sources_by_dir) do
+        local per_dir_mappings = {}
+        for _, src in ipairs(sources) do
+            -- Collect every (sym -> gpr) entry that originated from a source in this directory.
+            -- `src.scan.atom_auto_regs` is keyed by ATOM SCOPE NAME; `pairs(t)` iterates KEYS so `scope_name` here is the scope ident (e.g. "cube_g4_face").
+						-- The previous `for _, scan_atom_auto` form silently assigned the VALUE (a `{sym = sym}` table) to the variable,
+						-- which made `atom_allocations[scan_atom_auto]` a table-indexed lookup that never resolved.
+            for scope_name in pairs(src.scan and src.scan.atom_auto_regs or {}) do
+                for sym, gpr in pairs(atom_allocations[scope_name] or {}) do
+                    per_dir_mappings[sym] = gpr
+                end
+            end
+            for scope_name in pairs(src.scan and src.scan.phase_auto_regs or {}) do
+                for sym, gpr in pairs(phase_allocations[scope_name] or {}) do
+                    per_dir_mappings[sym] = gpr
+                end
+            end
+        end
+        local out_dir  = dir .. "/gen"
+        local out_path = emit_auto_reg_h(out_dir, dir, sources, per_dir_mappings)
+        if out_path then outputs[#outputs + 1] = { auto_reg_h = out_path } end
+    end
+    return { outputs = outputs, errors = errors, warnings = warnings }
+end
+
+return M

scripts/passes/components.lua

@@ -3,9 +3,12 @@
 --- Ownership: `corpus.word_counts`, `corpus.components`, and `corpus.component_body_index`.
 --- Scanner owns `declaration_comment` and `debug_skip` on each declaration record; this pass projects both forward.
 ---
---- Reads the pre-scanned SourceScan payload from `duffle.scan_source` for `MipsAtomComp_(ac_X)` and `MipsAtomComp_Proc_(ac_X, { body })` declarations,
+--- Reads the pre-scanned SourceScan payload from `duffle.scan_source` for `MipsAtomComp_(ac_X)` and `MipsAtomComp_Proc_(ac_X, { body })` declarations (kind="comp_bare" / "comp_proc"),
 --- then resolves the function-args string from the preceding `FI_ Slice_MipsCode ac_X(...)` declaration via a backward walk.
 ---
+--- `MipsAtom_Proc_(X, ab, { body })` declarations (kind="atom_proc") are ATOMS, not components, and are deliberately excluded —
+--- atoms get emitted via `tb_emit(tb, code_<name>)` linker symbols, not inlined as `mac_*` macros.
+---
 --- Emits one `gen/macs.h` per *immediate source directory* with `#define mac_X(sig) \` macros plus `WORD_COUNT(mac_X, N)` entries for downstream offset computation.
 --- All sources inside the same directory contribute to the same file (per-directory aggregation).
 --- The directory itself is the namespace, so the filename does not repeat the module name.
@@ -76,7 +79,7 @@ local MACS_FILENAME   = "macs.h"
 --- @field args       string|nil -- Function-args string (function form only)
 --- @field line       integer    -- Source line of the declaration
 --- @field comment    string|nil -- Scanner-owned `declaration_comment`; the components pass reads it from the scanner record
---- @field kind       string     -- "comp_bare" | "comp_proc"
+--- @field kind       string     -- "comp_bare" | "comp_proc"  (atom_proc is NOT a component — see `project_components`)
 --- @field debug_skip boolean    -- Mirror of `a.debug_skip` (scanner-owned); true iff a bare `atom_dbg_skip` marker immediately preceded the declaration
 
 -- ════════════════════════════════════════════════════════════════════════════
@@ -200,7 +203,16 @@ end
 local function project_components(source, scan)
 	local out = {}
 	for _, a in ipairs(scan.atoms) do
+		-- Only `MipsAtomComp_(ac_X)` (kind="comp_bare") and `MipsAtomComp_Proc_(ac_X, ...)` (kind="comp_proc")
+		-- are COMPONENTS — they get inlined via `mac_<name>` aliases inside atom bodies.
+		-- `MipsAtom_Proc_` (kind="atom_proc") is an ATOM (ends with `mac_yield()`); it gets emitted via
+		-- `tb_emit(tb, code_<name>)` (linker symbol), NOT inlined as a macro. Including `atom_proc` here
+		-- would incorrectly emit `mac_<name>` aliases for atoms, polluting `gen/macs.h`.
+		-- See `docs/duffle_dsl_primer.md` §"mac_* aliases" for the contract.
 		if a.kind == "comp_bare" or a.kind == "comp_proc" then
+			-- Function-args lookup is meaningful for `MipsAtomComp_Proc_` components
+			-- (the macro sits inside `FI_ Slice_MipsCode ac_X(...)`); the alias expansion
+			-- discards the `ab` (atom-builder) arg the same way both forms do.
 			local args = find_function_args_for(source, a.raw_name, a.ident_pos)
 			-- Comment ownership: scan_source.lua stamps `declaration_comment` on the record by walking backward past any associated bare marker.
 			-- The pass reads `declaration_comment` directly.
@@ -299,7 +311,9 @@ local function word_count_rec(name, comp_by_name, wc, cache)
 			local trimmed = t.tok
 			if trimmed ~= "" then
 				local lookup = strip_mac_prefix(duffle.read_ident(trimmed, 1))
-				if    lookup and comp_by_name[lookup] then
+				if lookup == "atom_label" or lookup == "atom_offset" then
+					-- Pure metaprogram anchors; emit zero words.
+				elseif lookup and comp_by_name[lookup] then
 					-- It's a `mac_X(...)` call. Recurse.
 					n = n + word_count_rec(lookup, comp_by_name, wc, cache)
 				elseif lookup and wc and wc[lookup] then
@@ -390,8 +404,7 @@ local function cycle_cost_rec(name, comp_by_name, latency, cache)
 end
 
 --- (internal) Recursive GP0 prim-buffer contribution. Count `store_word` / `store_half` / `store_byte` 
---- calls in the component body that target `R_PrimCursor` (these are the
---- RAM-side prim-buffer words the macro contributes), recursing through nested `mac_*` calls.
+--- calls in the component body that target `R_PrimCursor` (these are the RAM-side prim-buffer words the macro contributes), recursing through nested `mac_*` calls.
 --- Only `R_PrimCursor`-targeting stores count. Stores targeting other registers (e.g. `R_OtBase`, heap pointers) are not prim-buffer contributions.
 --- @param name         string
 --- @param comp_by_name table<string, Component>
@@ -473,12 +486,25 @@ local function split_comment_lines(s)
 end
 
 --- Determine the macro signature: function-args list (function form) or variadic-ignored (bare form).
+--- For `MipsAtomComp_Proc_` components, the leading `ab` (atom-builder) arg is dropped:
+--- the generated `mac_<name>` macros are inline-expansion aliases for baked atoms; their bodies don't reference `ab`
+--- (the builder is only consumed by the procedural `atombuilder_unroll` line that `MipsAtomComp_Proc_` appends after the body).
+--- Inline callers therefore don't need to thread a builder context.
 --- @param args_str string|nil
 --- @return string
 local function signature_from_args(args_str)
 	local arg_names = extract_arg_names(args_str)
 	if    arg_names and #arg_names > 0 then
-		return table.concat(arg_names, ", ")
+		-- Drop the leading `ab` (atom-builder) first arg if present.
+		-- Convention: `MipsAtomComp_Proc_` components always declare `ab` as the first function-arg
+		-- (type `MipsAtomBuilder_R`), mirroring the macro signature in `lottes_tape.h`.
+		if arg_names[1] == "ab" then
+			table.remove(arg_names, 1)
+		end
+		if #arg_names > 0 then
+			return table.concat(arg_names, ", ")
+		end
+		return "..."  -- `ab` was the only arg; fall through to variadic
 	end
 	return "..."
 end
@@ -520,7 +546,7 @@ local function build_component_lines(c, counts)
 
 	-- Marker comment: emitted once for every skipped component.
 	-- The marker is scanner-owned (declared by `atom_dbg_skip` immediately before the declaration in the source);
-	-- the components pass projects `c.debug_skip` and emits the marker as a generated comment.
+	-- This pass projects `c.debug_skip` and emits the marker as a generated comment.
 	if c.debug_skip then
 		lines[#lines + 1] = "/* atom_dbg_skip */"
 	end
@@ -554,8 +580,8 @@ end
 
 --- Build the boilerplate header lines (the `#ifdef INTELLISENSE_DIRECTIVES` block,
 --- the `// Auto-generated` comment, the `// Source:` line, and the self-contained `WORD_COUNT` macro definition).
---- @param dir     string       -- the absolute source directory
---- @param sources SourceFile[] -- sources contributing to this directory (for the header comment)
+--- @param dir     string       -- Absolute source directory
+--- @param sources SourceFile[] -- Sources contributing to this directory (for the header comment)
 --- @return string[]
 local function header_boilerplate(dir, sources)
 	local source_lines = { "// Directory: " .. duffle.to_absolute_path(dir) .. "/" }
@@ -586,9 +612,9 @@ end
 --- Compute the per-directory output path for `.macs.h`.
 ---  e.g. any source in `code/duffle/` produces `code/duffle/gen/macs.h` regardless of source filename.
 --- The directory name is the namespace; the filename does not repeat it.
---- @param dir string  -- the absolute source directory
---- @return string  -- the output directory
---- @return string  -- the full output path
+--- @param dir string  -- Absolute source directory
+--- @return string  -- Output directory
+--- @return string  -- Full output path
 local function compute_macs_h_path(dir)
 	local  out_dir  = dir .. "/" .. GEN_SUBDIR
 	local  out_path = out_dir .. "/" .. MACS_FILENAME
@@ -598,11 +624,11 @@ end
 --- Emit a per-directory `.macs.h` header with the aggregated `mac_X` macros + `WORD_COUNT` entries.
 --- Writes in BINARY mode so LF line endings are preserved (the git blob is LF; Windows text-mode would emit CRLF and break the byte-identical diff).
 --- @param ctx        PassCtx
---- @param dir        string                  -- the absolute source directory
---- @param sources    SourceFile[]            -- sources contributing to this directory (for the header comment)
---- @param components Component[]             -- aggregated components from all sources in this directory
---- @param counts     table<string, integer>  -- precomputed word counts (from count_all_components)
---- @return string|nil  -- path to the written file (nil if no components)
+--- @param dir        string                  -- Absolute source directory
+--- @param sources    SourceFile[]            -- Sources contributing to this directory (for the header comment)
+--- @param components Component[]             -- Aggregated components from all sources in this directory
+--- @param counts     table<string, integer>  -- Precomputed word counts (from count_all_components)
+--- @return string|nil -- Path to the written file (nil if no components)
 local function emit_component_macros_h(ctx, dir, sources, components, counts)
 	if #components == 0 then return nil end
 	local out_dir, out_path = compute_macs_h_path(dir)
@@ -641,11 +667,11 @@ local function update_canonical_word_counts(corpus, components, counts)
 end
 
 --- @class ComponentDef
---- @field name       string  -- bare name (without ac_/mac_ prefix)
---- @field line       integer -- definition source line (line of `MipsAtomComp_(ac_X)` / `MipsAtomComp_Proc_(ac_X, ...)`)
---- @field path       string  -- absolute source path of the definition
---- @field kind       string  -- "comp_bare" | "comp_proc"
---- @field debug_skip boolean -- mirror of the scanner-owned `a.debug_skip`; consumers read this directly
+--- @field name       string  -- Bare name (without ac_/mac_ prefix)
+--- @field line       integer -- Definition source line (line of `MipsAtomComp_(ac_X)` / `MipsAtomComp_Proc_(ac_X, ...)`)
+--- @field path       string  -- Absolute source path of the definition
+--- @field kind       string  -- "comp_bare" | "comp_proc"  (atom_proc is NOT a component)
+--- @field debug_skip boolean -- Mirror of the scanner-owned `a.debug_skip`; consumers read this directly
 
 --- (internal) Populate `corpus.components` with this source's components-by-name map.
 --- First declaration wins; later declarations of the same bare name are dropped and recorded as a collision via `corpus.collisions` (kind = "component").

scripts/passes/dwarf_injection.lua

@@ -703,9 +703,9 @@ end
 ---     `{comp_name, call_file, call_line, comp_file, comp_line, start_pos, end_pos, body_lines, debug_skip}`. `body_lines[k]`
 ---     is the k-th word's source line within the component body.
 ---
---- @param corpus table -- the corpus from `ctx.shared.corpus`
+--- @param corpus table -- From `ctx.shared.corpus`
 --- @param addrs  table -- ELF symbols keyed by atom name from `elf_dwarf.read_nm`
---- @return table[]  -- list of {name, addr, size_bytes, words, entries, invocations, debug_skip?}
+--- @return table[]  -- List of {name, addr, size_bytes, words, entries, invocations, debug_skip?}
 local function build_atom_table(corpus, addrs)
 	-- Cross-ref: keep only atoms present in BOTH the nm symbol table AND `corpus.atoms_by_name`. Output is sorted by ascending addr.
 	local atoms_by_name = corpus.atoms_by_name or {}
@@ -834,10 +834,10 @@ end
 --- This is intentional: silently falling back to a hardcoded GPR would mask the missing opt-in.
 ---
 --- Pre-tokenized: `body_tokens` is the scan-source pass's pre-split list of top-level statements (each entry is a single `load_*` call or other statement).
---- @param body_tokens table[]  -- the atom's pre-tokenized body statements (from atom.body_tokens)
---- @param binds_name  string   -- expected Binds_X name (skip pairs with mismatching binds)
---- @param registries  table    -- merged registries from collect_per_source_registries
---- @return table[]             -- list of {reg = <MIPS index>, field = <field name>}
+--- @param body_tokens table[]  -- The atom's pre-tokenized body statements (from atom.body_tokens)
+--- @param binds_name  string   -- Expected Binds_X name (skip pairs with mismatching binds)
+--- @param registries  table    -- Merged registries from collect_per_source_registries
+--- @return table[]             -- List of {reg = <MIPS index>, field = <field name>}
 local function parse_body_load_pairs(body_tokens, binds_name, registries)
 	local pairs = {}
 	local reg_index_by_name = (registries and registries.register_alias_registry) or {}
@@ -880,9 +880,9 @@ end
 --- The piece chain uses (DW_OP_regN, DW_OP_piece, ULEB128(field_size)).
 ---
 --- Binds fields come from `scan.binds`; the per-source `scan.binds[i].fields` already carries the typed-field record after the scan-source generalization.
---- @param corpus     table   -- the corpus from `ctx.shared.corpus`
---- @param atom_table table[] -- the cross-ref'd atom table from build_atom_table
---- @param registries table   -- merged registries from collect_per_source_registries
+--- @param corpus     table   -- From `ctx.shared.corpus`
+--- @param atom_table table[] -- Cross-ref'd atom table from build_atom_table
+--- @param registries table   -- Merged registries from collect_per_source_registries
 --- @return table, table      -- (rbind_atoms, rbind_structs)
 local function parse_rbind_atoms(corpus, atom_table, registries)
 	registries = registries or {}
@@ -944,7 +944,7 @@ local function parse_rbind_atoms(corpus, atom_table, registries)
 						binds     = ai.binds,
 						fields    = struct.fields, -- {name, offset} from scan.binds
 						bytes     = struct.bytes,
-						regs      = pairs,         -- ordered list of {reg, field}
+						regs      = pairs,         -- Ordered list of {reg, field}
 						info_line = ai.info_line,
 					}
 					table.insert(struct.atom_names, atom_name)
@@ -1036,13 +1036,13 @@ local function build_dwarf_aranges_section(existing, atom_table)
 	-- We bump the unit's length field accordingly.
 	--
 	-- Unit structure (DWARF4 §7.21):
-	--   unit_length (4)
-	--   version (2)
+	--   unit_length       (4)
+	--   version           (2)
 	--   debug_info_offset (4)  -- CU DIE offset in .debug_info
-	--   address_size (1)
-	--   segment_size (1)
-	--   entries... (4-byte addr + 4-byte length)
-	--   terminator (8 bytes: addr=0, length=0)
+	--   address_size      (1)
+	--   segment_size      (1)
+	--   entries...        (4-byte addr + 4-byte length)
+	--   terminator        (8 bytes: addr=0, length=0)
 
 	-- Walk all units and emit each one (preserving existing structure).
 	-- For the LAST unit, replace the terminator with my entries + new term.
@@ -1780,7 +1780,8 @@ local function build_inserted_children(main_cu_offset, main_cu_end_excl, atom_ta
 	emit(uleb128(ABBREV_TYPED_VIEW_POINTER))  -- DW_TAG_pointer_type (abbrev 110; NOT 9; void chain target)
 	emit(elf_dwarf.write_u32_le(ref4_of(void_chain_offset)))  -- 4-byte ref4: points at the void base_type's tag byte
 	-- type_chain_offsets["void|1"] is what step (f) of the per-RR_<R_Name> chain looks up.
-	type_chain_offsets["void|1"] = void_chain_offset  -- both the base_type offset and the pointer_type are emitted consecutively; the OUTERMOST is the pointer_type. The variable's DW_AT_type must reference the pointer_type, not the base_type. Patch below.
+	type_chain_offsets["void|1"] = void_chain_offset  -- both the base_type offset and the pointer_type are emitted consecutively; the OUTERMOST is the pointer_type.
+	-- The variable's DW_AT_type must reference the pointer_type, not the base_type. Patch below.
 	-- Capture the pointer_type's offset (the last-thing-emitted DIE start) and overwrite the lookup.
 	-- The pointer_type was emitted as: uleb(9) (1 byte) + 4-byte ref4 = 5 bytes. Its tag byte is at void_chain_offset + 8 (the base_type's 8 bytes: 1 tag + 5 name + 1 byte_size + 1 encoding).
 	local ptr_void_offset = void_chain_offset + 8

scripts/passes/emission_model.lua

@@ -188,11 +188,11 @@ function M.run(ctx)
 	if type(corpus.source_order) ~= "table" then error("emission_model: ctx.shared.corpus.source_order is required", 0) end
 
 	-- Project once, collect errors + warnings for one atom.
-	-- Kind must be one of: atom | raw_atom | comp_bare | comp_proc.
+	-- Kind must be one of: atom | atom_proc | raw_atom | comp_bare | comp_proc.
 	local function process_atom(atom, src)
 		if not (atom and atom.body) then return end
 		local kind = atom.kind
-		if kind ~= "atom" and kind ~= "raw_atom" and kind ~= "comp_bare" and kind ~= "comp_proc" then
+		if kind ~= "atom" and kind ~= "atom_proc" and kind ~= "raw_atom" and kind ~= "comp_bare" and kind ~= "comp_proc" then
 			return
 		end
 		local proj = project_atom(atom, src, corpus)
@@ -215,7 +215,7 @@ function M.run(ctx)
 	end
 
 	-- Walk `corpus.source_order`; within each source, visit atoms followed by raw_atoms.
-	-- Recognized kinds (atom | raw_atom | comp_bare | comp_proc) each receive the atom.paths projection via duffle.project_emission.
+	-- Recognized kinds (atom | atom_proc | raw_atom | comp_bare | comp_proc) each receive the atom.paths projection via duffle.project_emission.
 	-- Components are macros inlined into atom bodies; focused tests and isolated component analyses consume atom.paths directly.
 	for _, src in ipairs(corpus.source_order) do
 		local scan = src.scan or {}

scripts/passes/offsets.lua

@@ -4,9 +4,17 @@
 --- for `MipsAtom_(name)` and `MipsCode code_<name>` declarations, computes the word offset
 --- from each `atom_offset(F, T)` marker to its target `atom_label(T)` declaration, and emits
 --- `gen/offsets.h` with one `#define _atom_offset_F_T = N` per branch.
+---
 --- Per-directory aggregation: every source in the same directory contributes to the same `gen/offsets.h`.
 --- The directory itself is the namespace; the filename does not repeat the module name.
 ---
+--- (Task 12.16 note: atom-namespaced enum names — e.g., `atom_offset__normalize_v3s4__srav_path__aligned_done` —
+--- were considered to prevent cross-atom label collisions, but the C-side `atom_offset(F, T)` macro in
+--- `code/duffle/dsl.atom.h` doesn't know the current atom_name at expansion time, so any namespacing
+--- on the metaprogram side breaks the C build. Reverted. The C-side would need a per-atom
+--- `CURRENT_ATOM` #define (set by `MipsAtom_`/`MipsAtom_Proc_` macros) plus an updated `atom_offset`
+--- macro that uses it. That's a coordinated refactor — deferred to a future track.)
+---
 --- The offset is `target_word - branch_word - 1` (the standard MIPS branch-immediate encoding: branch_offset = relative_pc_in_words - 1).
 
 -- ════════════════════════════════════════════════════════════════════════════

scripts/passes/scan_source.lua

@@ -3,6 +3,7 @@
 --- Single source-walk pass that produces the fat `SourceScan` payload consumed by all downstream passes. Walks each corpus source record once,
 --- extracting every construct type the metaprograms need:
 ---   MipsAtom_              (kind = "atom", with optional atom_info inner)
+---   MipsAtom_Proc_         (kind = "atom_proc", body inside last {})
 ---   MipsAtomComp_          (kind = "comp_bare")
 ---   MipsAtomComp_Proc_     (kind = "comp_proc", body inside last {})
 ---   atom_dbg_skip          — bare whole-atom/component debug-step marker; following declaration disambiguates
@@ -34,7 +35,7 @@ local parse_enum_int_literal
 -- ════════════════════════════════════════════════════════════════════════════
 
 --- @class SourceScan
---- @field atoms             AtomEntry[]     -- MipsAtom_ + MipsAtomComp_ + MipsAtomComp_Proc_
+--- @field atoms             AtomEntry[]     -- MipsAtom_ + MipsAtom_Proc_ + MipsAtomComp_ + MipsAtomComp_Proc_
 --- @field raw_atoms         AtomEntry[]     -- MipsCode code_<name> { body } (offsets pass only)
 --- @field binds             BindsEntry[]    -- typedef Struct_(Binds_X) { fields } (fields pre-parsed)
 --- @field atom_infos        AtomInfoEntry[] -- MipsAtom_(name) atom_info(...) (sub-calls pre-parsed)
@@ -55,7 +56,7 @@ local parse_enum_int_literal
 --- @field args           string|nil  -- Trimmed args inside the `(...)` (nil when has_parens is false)
 --- @field pending        boolean     -- true while awaiting the following declaration
 --- @field superseded_by_marker_line integer|nil -- set when a newer marker bumped this one out of the pending slot
---- @field target_kind    string|nil  -- "atom" | "comp_bare" | "comp_proc" | "unrelated" once observed (nil if no declaration ever followed)
+--- @field target_kind    string|nil  -- "atom" | "atom_proc" | "comp_bare" | "comp_proc" | "unrelated" once observed (nil if no declaration ever followed)
 --- @field proc_prelude   boolean|nil -- true after the marker crossed an `FI_` prelude and awaits `MipsAtomComp_Proc_`
 
 --- @class RegTypeDefault
@@ -111,7 +112,7 @@ local parse_enum_int_literal
 --- @field name              string       -- Atom name (for components: without ac_ prefix)
 --- @field body              string       -- Brace-delimited body (without the braces)
 --- @field body_off          integer      -- Char offset of body[1] in source
---- @field kind              string       -- "atom" | "comp_bare" | "comp_proc" | "raw_atom"
+--- @field kind              string       -- "atom" | "atom_proc" | "comp_bare" | "comp_proc" | "raw_atom"
 --- @field raw_name          string       -- Un-stripped name (for components: with ac_ prefix)
 --- @field ident_pos         integer      -- Position of the MipsAtom_/MipsAtomComp_ ident start
 --- @field after_paren       integer      -- Position past the closing paren
@@ -268,7 +269,7 @@ end
 ---   marker_kind == "atom_dbg_skip" AND is_bare == true
 --- Any other spelling or shape (parenthesized form, legacy name) is recorded as a raw marker for annotation validation but never stamps `debug_skip`.
 --- @param out         SourceScan
---- @param target_kind string|nil -- "atom" | "comp_bare" | "comp_proc" | "unrelated" once observed
+--- @param target_kind string|nil -- "atom" | "atom_proc" | "comp_bare" | "comp_proc" | "unrelated" once observed
 --- @return boolean|nil -- true iff the marker is the positive bare form
 local function attach_debug_skip_marker(out, target_kind)
 	local markers = out.debug_skip_markers
@@ -799,6 +800,11 @@ local BYTE_x          = 0x78   -- 'x'
 local BYTE_X          = 0x58   -- 'X'
 local BYTE_OPEN_BRACE = 0x7B   -- '{'
 local BYTE_CLOSE_BRACE= 0x7D   -- '}'
+local BYTE_SLASH      = 0x2F   -- '/'
+local BYTE_STAR       = 0x2A   -- '*'
+local BYTE_SPACE      = 0x20   -- ' '
+local BYTE_TAB        = 0x09   -- '\t'
+local BYTE_CR         = 0x0D   -- '\r'
 
 -- Maximum chain depth when resolving `R_*_Code` symbol RHS references.
 -- Eight hops is enough for any production chain (R_TapePtr_Code -> R_T8_Code -> ...).
@@ -822,6 +828,44 @@ local function hex_digit_value(b)
 	return nil
 end
 
+-- Read one trailing C-comment that appears immediately after `pos` in `body`,
+-- skipping horizontal whitespace and newlines first. Used by `parse_enum_entry` to
+-- recover the `atom_auto_reg:` / `phase_auto_reg:` scope annotation embedded by
+-- the `atom_auto_reg` / `phase_auto_reg` macros' RHS expansion
+-- (`R_<Sym> = R_<Sym>_Code /* atom_auto_reg: <scope> */`).
+-- Handles both block (`/* ... */`) and line (`// ...`) forms.
+-- Returns the comment text (without delimiters), or nil if no comment is adjacent.
+local function read_trailing_cmt_after(body, pos)
+	local body_len = #body
+	while pos <= body_len do
+		local b = body:byte(pos)
+		if b == BYTE_SPACE or b == BYTE_TAB or b == BYTE_NEWLINE or b == BYTE_CR then
+			pos = pos + 1
+		elseif b == BYTE_SLASH then
+			local b2 = body:byte(pos + 1)
+			if b2 == BYTE_STAR then
+				-- Block comment /* ... */
+				local i = pos + 2
+				while i < body_len do
+					if body:byte(i) == BYTE_STAR and body:byte(i + 1) == BYTE_SLASH then
+						return body:sub(pos + 2, i - 1)
+					end
+					i = i + 1
+				end
+				return nil  -- unterminated; treat as no comment
+			elseif b2 == BYTE_SLASH then
+				-- Line comment // ... (strip the trailing newline)
+				local end_pos = duffle.find_byte(body, BYTE_NEWLINE, pos + 2) or (body_len + 1)
+				return body:sub(pos + 2, end_pos - 1)
+			end
+			return nil
+		else
+			return nil
+		end
+	end
+	return nil
+end
+
 --- Parse a decimal/negative-decimal/hex integer literal starting at byte position `start`.
 --- Returns (value, end_pos) on success, or (nil, start) on failure / no match.
 --- Accepts: 12, -1, 0, 0x10, 0X1F, -0x10.
@@ -1128,6 +1172,46 @@ local function parse_dbg_skip_marker(source, pos, ident_end, line_of, out)
 	return marker_end
 end
 
+--- Parse `atom_auto_reg(<atom>, R_<Sym>)` and `phase_auto_reg(<phase>, R_<Sym>)` markers.
+---
+--- The macros expand to `sym = sym##_Code` per their definition in dsl.atom.h.
+--- After preprocessing, the marker renders as a full enum entry of the form `R_<Sym> = R_<Sym>_Code,`.
+--- This parser detects the macro invocation site, extracts `(scope_name, sym)`, and stores it
+--- in the per-source table (atom_auto_regs or phase_auto_regs) under the scope's name.
+---
+--- @param source    string
+--- @param pos       integer
+--- @param ident_end integer
+--- @param line_of   fun(pos: integer): integer
+--- @param out       SourceScan
+--- @return integer
+local function parse_auto_reg_marker(source, pos, ident_end, line_of, out)
+	local marker_kind = source:sub(pos, ident_end - 1)  -- "atom_auto_reg" or "phase_auto_reg"
+	local scope_kind  = marker_kind == "atom_auto_reg" and "atom" or "phase"
+
+	local inner, after_paren = read_parens_after(source, ident_end)
+	if not inner then return after_paren end
+
+	local args = duffle.split_top_level_commas(inner)
+	local scope_name = args[1] and duffle.trim(args[1]) or nil
+	local sym        = args[2] and duffle.trim(args[2]) or nil
+
+	-- Filter: only accept `R_<Sym>` form (matches `^R_[%w_]+$`).
+	if scope_name and sym and sym:match("^R_[%w_]+$") then
+		if scope_kind == "atom" then
+			out.atom_auto_regs = out.atom_auto_regs or {}
+			out.atom_auto_regs[scope_name] = out.atom_auto_regs[scope_name] or {}
+			out.atom_auto_regs[scope_name][sym] = sym
+		else
+			out.phase_auto_regs = out.phase_auto_regs or {}
+			out.phase_auto_regs[scope_name] = out.phase_auto_regs[scope_name] or {}
+			out.phase_auto_regs[scope_name][sym] = sym
+		end
+	end
+
+	return after_paren
+end
+
 -- Parse `atom_dbg_reg_default(R_X, <type>...)`;
 -- the second argument may be a `Type` or `Type*`/`Type**` chain. Records in `out.types[R_X]`.
 local function parse_atom_dbg_reg_default(source, pos, ident_end, line_of, out)
@@ -1282,6 +1366,49 @@ local function parse_mips_atom_comp_proc(source, pos, ident_end, line_of, out)
 	return after_paren
 end
 
+--- Parse: `MipsAtom_Proc_(<name>, <abuilder>, { <body> })` — body is inside the LAST `{` in args.
+--- Per Task 12.10: full support for the runtime-proc atom form. Registers the atom
+--- with kind `"atom_proc"` so offsets.lua / components.lua can emit
+---   * `mac_<name>` aliases in `gen/macs.h` (the components pass)
+---   * `atom_offset__X__Y` defs in `gen/offsets.h` (the offsets pass)
+--- The atom name is the FIRST ident of the args (the second arg `ab` is the
+--- atom-builder, not the name). Unlike `MipsAtomComp_Proc_`, there is no `ac_`
+--- prefix on the symbol — `MipsAtom_Proc_` is the runtime-proc wrapper, so the
+--- symbol IS the bare atom name (e.g. `normalize_v3s4`, not `ac_normalize_v3s4`).
+--- @param source    string
+--- @param pos       integer
+--- @param ident_end integer
+--- @param line_of   fun(pos: integer): integer
+--- @param out       SourceScan
+--- @return integer
+local function parse_mips_atom_proc(source, pos, ident_end, line_of, out)
+	local  inner, after_paren, open_paren = read_parens_after(source, ident_end)
+	if not inner then return after_paren end
+
+	-- Find the LAST `{` in inner (the body brace, not any potential embedded braces in expressions).
+	local last_brace_pos = nil
+	for search_pos = #inner, 1, -1 do
+		if inner:sub(search_pos, search_pos) == "{" then last_brace_pos = search_pos; break end
+	end
+	if not last_brace_pos then return after_paren end
+
+	-- Use duffle.read_braces to find the matching close brace.
+	-- Uses `read_balanced` for delimiter-depth tracking.
+	-- If close_pos is past the end of inner, the brace didn't match (malformed input); skip.
+	local body, close_pos = duffle.read_braces(inner, last_brace_pos)
+	if close_pos > #inner + 1 then return after_paren end
+
+	-- The atom name is the FIRST ident of the args (matches MipsAtomComp_Proc_'s "first ident" rule).
+	-- MipsAtom_Proc_ has no `ac_` prefix; `strip_ac_prefix` is a no-op for unprefixed names.
+	local raw_name = inner:match("^%s*([%w_]+)") or "?"
+	local name     = strip_ac_prefix(raw_name)
+	-- Position of body[1] in source = open_paren + 1 (start of inner) + last_brace_pos + 1 (past '{').
+	local body_off = open_paren + 2 + last_brace_pos
+	register_atom(out, "atom_proc", line_of(pos), name, body, body_off, raw_name, pos, after_paren, source)
+
+	return after_paren
+end
+
 --- Parse: `MipsCode code_<name> { <body> }` (raw atom form — offsets pass only).
 --- @param source    string
 --- @param pos       integer
@@ -1602,6 +1729,16 @@ local function parse_enum_entry(source, body, body_offset, line_of, out, entry_n
 	local value, value_end = parse_enum_value(body, after_ws, out)
 	if value == nil then return value_start end
 
+	-- Capture the trailing C-comment (if any) before `skip_ws_and_cmt` discards it.
+	-- The `atom_auto_reg(<scope>, <sym>)` macro expands to `R_<Sym> = R_<Sym>_Code /* atom_auto_reg: <scope> */`,
+	-- so the scope name lives in the comment after the RHS value. Routes through `out.atom_entry_comments`
+	-- for downstream `parse_enum` to split into `out.atom_auto_regs` / `out.phase_auto_regs`.
+	local trailing_cmt = read_trailing_cmt_after(body, value_end)
+	if trailing_cmt then
+		out.atom_entry_comments = out.atom_entry_comments or {}
+		out.atom_entry_comments[entry_name] = trailing_cmt
+	end
+
 	local after_value       = duffle.skip_ws_and_cmt(body, value_end)
 	local has_atom_reg, end_after_atom_reg = check_bare_atom_reg(body, after_value)
 
@@ -1657,15 +1794,24 @@ local function parse_enum_body(source, body, body_offset, line_of, out)
 		else
 			local entry_name, name_end = duffle.read_ident(body, pos)
 			if entry_name then
-				local after_name = duffle.skip_ws_and_cmt(body, name_end)
-				if body:byte(after_name) == BYTE_EQUAL then
-					local new_pos = parse_enum_entry(
-						source, body, body_offset, line_of, out,
-						entry_name, pos, after_name + 1
-					)
-					if new_pos > pos then pos = new_pos else pos = after_name + 1 end
+				-- In-enum `atom_auto_reg(<scope>, R_<Sym>)` / `phase_auto_reg(<scope>, R_<Sym>)` markers:
+				-- the C preprocessor expands them to `R_<Sym> = R_<Sym>_Code /* atom_auto_reg: <scope> */`,
+				-- but the metaprogram reads source-as-written so we must dispatch the parser here too.
+				-- Mirrors the top-level `DECL_PARSERS` entry for `atom_auto_reg` / `phase_auto_reg`.
+				if entry_name == "atom_auto_reg" or entry_name == "phase_auto_reg" then
+					local new_pos = parse_auto_reg_marker(body, pos, name_end, line_of, out)
+					if new_pos > pos then pos = new_pos else pos = name_end end
 				else
-					pos = name_end
+					local after_name = duffle.skip_ws_and_cmt(body, name_end)
+					if body:byte(after_name) == BYTE_EQUAL then
+						local new_pos = parse_enum_entry(
+							source, body, body_offset, line_of, out,
+							entry_name, pos, after_name + 1
+						)
+						if new_pos > pos then pos = new_pos else pos = after_name + 1 end
+					else
+						pos = name_end
+					end
 				end
 			else
 				pos = pos + 1
@@ -1695,6 +1841,25 @@ local function parse_enum(source, pos, ident_end, line_of, out)
 	if not body then return after_brace end
 	parse_enum_body(source, body, body_off, line_of, out)
 
+	-- Route `atom_auto_reg:` / `phase_auto_reg:` markers discovered in trailing C-comments
+	-- into the per-source `atom_auto_regs` / `phase_auto_regs` projections.
+	-- Pattern matches the RHS expansion `R_<Sym> = R_<Sym>_Code /* <kind>_auto_reg: <scope> */`
+	-- emitted by the `atom_auto_reg` / `phase_auto_reg` macros in dsl.atom.h.
+	for entry_name, cmt_text in pairs(out.atom_entry_comments or {}) do
+		local atom_scope = cmt_text:match("atom_auto_reg:%s*([%w_]+)")
+		if atom_scope then
+			out.atom_auto_regs = out.atom_auto_regs or {}
+			out.atom_auto_regs[atom_scope] = out.atom_auto_regs[atom_scope] or {}
+			out.atom_auto_regs[atom_scope][entry_name] = entry_name
+		end
+		local phase_scope = cmt_text:match("phase_auto_reg:%s*([%w_]+)")
+		if phase_scope then
+			out.phase_auto_regs = out.phase_auto_regs or {}
+			out.phase_auto_regs[phase_scope] = out.phase_auto_regs[phase_scope] or {}
+			out.phase_auto_regs[phase_scope][entry_name] = entry_name
+		end
+	end
+
 	return after_brace
 end
 
@@ -1708,12 +1873,18 @@ end
 
 local DECL_PARSERS = {
 	MipsAtom_                  = parse_mips_atom,
+	MipsAtom_Proc_             = parse_mips_atom_proc,
 	MipsAtomComp_              = parse_mips_atom_comp,
 	MipsAtomComp_Proc_         = parse_mips_atom_comp_proc,
 	-- `atom_dbg_skip` is the only debug-skip parser entry. Every other
 	-- identifier follows the ordinary unrelated-token path; there is no alias.
 	atom_dbg_skip              = parse_dbg_skip_marker,
 	atom_dbg_reg_default       = parse_atom_dbg_reg_default,
+	-- `atom_auto_reg(atom, R_<Sym>)` and `phase_auto_reg(phase, R_<Sym>)` populate per-source
+	-- `out.atom_auto_regs` / `out.phase_auto_regs`; the cross-source merge lands in
+	-- `corpus.atom_auto_regs` / `corpus.phase_auto_regs` (first-wins).
+	atom_auto_reg              = parse_auto_reg_marker,
+	phase_auto_reg             = parse_auto_reg_marker,
 	MipsCode                   = parse_mips_code,
 	typedef                    = parse_typedef_binds,
 	_Pragma                    = parse_pragma_macro,
@@ -1748,6 +1919,14 @@ local function scan_source(source, source_file, code_macros, code_macro_bodies)
 		debug_skip_markers = {},
 		types             = {},
 		atom_views        = {},
+		-- Per-source projection for `atom_auto_reg(<atom>, R_<Sym>)` markers.
+		-- Each entry is keyed by atom_name; the inner table maps `R_<Sym>` -> `R_<Sym>` (raw LHS sym).
+		-- Merged cross-source into `corpus.atom_auto_regs` (first-wins).
+		atom_auto_regs    = {},
+		-- Per-source projection for `phase_auto_reg(<phase>, R_<Sym>)` markers.
+		-- Each entry is keyed by phase_label; the inner table maps `R_<Sym>` -> `R_<Sym>` (raw LHS sym).
+		-- Merged cross-source into `corpus.phase_auto_regs` (first-wins).
+		phase_auto_regs   = {},
 		line_of           = line_of,
 		-- Source-derived register-alias registry (atom_reg opt-in entries).
 		-- Keys are full R_* idents (never stripped); see parse_enum / parse_enum_body.
@@ -1987,6 +2166,8 @@ local function merge_corpus_registries(corpus)
 	corpus.atom_ctxs               = corpus.atom_ctxs               or {}
 	corpus.atom_phases             = corpus.atom_phases             or {}
 	corpus.atom_infos              = corpus.atom_infos              or {}
+	corpus.atom_auto_regs          = corpus.atom_auto_regs          or {}
+	corpus.phase_auto_regs         = corpus.phase_auto_regs         or {}
 	corpus.collisions              = corpus.collisions              or {}
 
 	-- Replace the existing corpus collections with empty tables so a re-run on the same corpus produces identical state (deterministic merge).
@@ -2030,7 +2211,7 @@ local function merge_corpus_registries(corpus)
 					corpus.collisions, "binds", bind_shape)
 			end
 
-			-- atoms_by_name: MipsAtom_(name) + MipsAtomComp_(name) + MipsAtomComp_Proc_(name).
+			-- atoms_by_name: MipsAtom_(name) + MipsAtom_Proc_(name) + MipsAtomComp_(name) + MipsAtomComp_Proc_(name).
 			-- Each atom carries `{line, name, body, body_off, kind, raw_name, ...}`.
 			-- Duplicate atom names across sources are first-wins + collision; see the atom_infos block below for the evidence list.
 			for _, atom_entry in ipairs(scan.atoms or {}) do
@@ -2065,6 +2246,22 @@ local function merge_corpus_registries(corpus)
 					corpus.collisions, "phase", phase_shape)
 			end
 
+			-- atom_auto_regs: keyed by atom scope name; each carries a `{R_<Sym> = R_<Sym>}` map.
+			-- Per-source entries are simple inner maps (no body / no shape comparison); first-wins suffices.
+			for atom_scope, syms in pairs(scan.atom_auto_regs or {}) do
+				if corpus.atom_auto_regs[atom_scope] == nil then
+					corpus.atom_auto_regs[atom_scope] = syms
+				end
+			end
+
+			-- phase_auto_regs: keyed by phase label; each carries a `{R_<Sym> = R_<Sym>}` map.
+			-- Per-source entries are simple inner maps (no body / no shape comparison); first-wins suffices.
+			for phase_label, syms in pairs(scan.phase_auto_regs or {}) do
+				if corpus.phase_auto_regs[phase_label] == nil then
+					corpus.phase_auto_regs[phase_label] = syms
+				end
+			end
+
 			-- atom_infos: ALWAYS append every record in source/declaration order.
 			-- Duplicates are preserved so the annotation pass can flag them via `check_unique_annotation`;
 			-- The merge is purely order-preserving.

scripts/passes/static_analysis.lua

@@ -39,8 +39,8 @@
 --- `── Info` section renders finding-level info between `── Warnings` and the per-atom cycle counts.
 ---
 --- The structural handshake checks (`mac_yield_uniformity`, `hazard_nop_use`, `control_transfer_delay_slot_use`) skip atoms/components with `debug_skip == true`.
---- The `atom_dbg_skip` marker designates runtime-helper declarations whose structure is fixed by the tape runtime (e.g. `tape_exit`, `ac_yield`).
---- Flagging them as "missing mac_yield" or "BD slot is redundant" is signal noise, not a logic failure. 
+--- `atom_dbg_skip` marker designates runtime-helper declarations whose structure is fixed by the tape runtime (e.g. `tape_exit`, `ac_yield`).
+--- Flagging them as "missing mac_yield" or "BD slot is redundant".
 --- Other checks (transfer_hazards, gpu_portstore_shape, abi_handoff, enum_alias_membership, …) still apply to debug_skip declarations because real hazards / typos can still surface in them.
 ---
 --- The orchestrator (`ps1_meta.lua`) wires this module in via the PASSES table:
@@ -256,8 +256,21 @@ local BRANCH_PATTERN          = "^branch_[%w_]+%s*%("
 -- The C preprocessor expands it BEFORE the metaprogram sees the source, but for source-level metadata consistency we still match it here and classify it as a branch_equal.
 -- This keeps `consuming_encoder` canonical for any downstream tooling that consults the metadata field.
 local JUMP_REL_PATTERN      = "^jump_rel%s*%("
-local UNCOND_JUMP_PATTERN   = "^%f[%w](jump|call_addr)%f[%W]"
-local TERMINAL_JUMP_PATTERN = "^%f[%w](jump_reg|call_reg|jump_link)%f[%W]"
+local UNCOND_JUMP_PATTERNS = {
+    "^%f[%w]jump%f[%W]",
+    "^%f[%w]call_addr%f[%W]",
+}
+local TERMINAL_JUMP_PATTERNS = {
+    "^%f[%w]jump_reg%f[%W]",
+    "^%f[%w]call_reg%f[%W]",
+    "^%f[%w]jump_link%f[%W]",
+}
+local function matches_any(tok, patterns)
+    for i = 1, #patterns do
+        if tok:match(patterns[i]) then return true end
+    end
+    return false
+end
 
 local function classify_tokens(tokens)
 	local n       = #tokens
@@ -301,13 +314,13 @@ local function classify_tokens(tokens)
 			-- Both encode a 16-bit signed relative word offset.
 			is_branch    = true
 			branch_label = tok:match("atom_offset%s*%([^,]+,%s*([%w_]+)%s*%)") or false
-		elseif tok:match(UNCOND_JUMP_PATTERN) then
+		elseif matches_any(tok, UNCOND_JUMP_PATTERNS) then
 			-- Unconditional absolute jump / call: `jump(off)` / `call_addr(off)`.
 			-- One immediate offset field; can carry an `atom_offset(F, T)` marker (the offsets pass dispatches on `consuming_encoder` — see `passes/offsets.lua::compute_offsets`).
 			is_branch              = true
 			is_unconditional_jump = true
 			branch_label           = tok:match("atom_offset%s*%([^,]+,%s*([%w_]+)%s*%)") or false
-		elseif tok:match(TERMINAL_JUMP_PATTERN) then
+		elseif matches_any(tok, TERMINAL_JUMP_PATTERNS) then
 			-- Register-form jump / call: no offset field; `atom_offset` is invalid here (the offsets pass will error if one is supplied).
 			-- Transfers control OUT of the current atom — the CFG treats this as a path terminator.
 			is_terminal_jump = true
@@ -439,7 +452,7 @@ local function is_cop2_consumer_of(consumer_event, destination, producer_rel)
 end
 
 -- True iff `consumer_event` reads the GPR operand at any position the destination register occupies.
--- The read-position lookup consults `duffle.OPERAND_READ_POSITIONS` for the consumer's encoder and walks each `args[pos]` to find an operand-equal match.
+-- read_pos lookup consults `duffle.OPERAND_READ_POSITIONS` for the consumer's encoder and walks each `args[pos]` to find an operand-equal match.
 local function is_gpr_consumer_of(consumer_event, destination)
 	local consumer_token = consumer_event.encoder or consumer_event.ident
 	local read_pos       = duffle.OPERAND_READ_POSITIONS or {}
@@ -567,13 +580,31 @@ local function evaluate_gpr_value_rule(rule, ev_args, gpr_values)
 		return shift_left_u4(immediate % 0x10000, 16)
 	end
 
-	local source = nil
+	-- Encoders that take `R_0` implicitly (e.g. `li_s(rt, imm)` which is `add_ui(rt, R_0, imm)`) have a non-GPR operand at the source position.
+	-- Fall back to R_0 = 0.
+	-- The implicit-R_0 macros also use a different immediate position (e.g. `li_s`'s `add_ui` rule has source = 2 / immediate = 3
+	-- but the macro takes 2 args); when the configured immediate position is out of bounds.
+	-- Fall back instead to scanning the macro's args for the first integer literal and use that as the immediate.
+	local source = 0
 	if rule.source then
-		source = constant_for_operand(gpr_values, ev_args[rule.source])
-		if source == nil then return nil end
+		if is_gpr_operand(ev_args[rule.source]) then
+			source = constant_for_operand(gpr_values, ev_args[rule.source])
+			if source == nil then return nil end
+		end
+		-- Non-GPR at source position = implicit R_0; source stays 0.
+	end
+	local immediate = nil
+	if rule.immediate and ev_args[rule.immediate] ~= nil then
+		immediate = parse_integer_literal(ev_args[rule.immediate])
+		if immediate == nil then return nil end
+	elseif rule.immediate then
+		-- Immediate position out of bounds: scan for the first integer literal in the args.
+		for _, arg in ipairs(ev_args) do
+			immediate = parse_integer_literal(arg)
+			if immediate ~= nil then break end
+		end
+		if immediate == nil then return nil end
 	end
-	local immediate = rule.immediate and parse_integer_literal(ev_args[rule.immediate]) or nil
-	if rule.immediate and immediate == nil then return nil end
 	if     operation == "add_ui"      then return wrap_u4(      source + sign_extend_i16(immediate))
 	elseif operation == "or_i"        then return bit_binary(   source, immediate % 0x10000, "or")
 	elseif operation == "and_i"       then return bit_binary(   source, immediate % 0x10000, "and")
@@ -1433,17 +1464,21 @@ end
 --- The register becomes non-volatile again at word N+2 (the load has retired), OR sooner if a non-load instruction overwrites the register
 --- (the overwriter's write is the fresh producer; the load's value is shadowed and never observed by any reader).
 ---
---- Runtime-helper atoms / components (`debug_skip == true`) are exempt: their internal load-then-use sequences
---- are part of the fixed handshake (e.g. `ac_load_tri_indices` loads into R_T0..R_T2, but those are caller-supplied).
+--- Runtime-helper atoms / components (`debug_skip == true`) are exempt from some checks, but load-delay
+--- safety applies to their emitted instructions as well.
 ---
 --- The walker reads `duffle.OPERAND_READ_POSITIONS[event.encoder]` to determine which args are read-source
 --- (the destination of a load is in `writes`, not `reads` — see `duffle.INSTRUCTION_GPR_EFFECTS`).
---- The check is purely structural; it does not consult the GPR-value lattice (no constant propagation needed for load-delay detection — the volatility window is unconditional).
+--- The check is purely structural; it does not consult the GPR-value lattice
+--- (no constant propagation needed for load-delay detection — the volatility window is unconditional).
 local function check_load_delay_slots(atom, pipe_ctx, findings)
-	if atom.kind ~= "atom" then return end
-	local events = atom.paths.word_events or {}
+	-- The load-delay check applies to every atom and component body, including debug-skipped components (`ac_*` and `atom_dbg_skip MipsAtom_(...)`).
+	-- The `atom_dbg_skip` marker controls debugger stepping, not instruction safety.
+	-- `atom_proc` atoms have full bodies with loads that need delay slots, so the check applies to them too.
+	local p = atom.paths or {}
+	if atom.kind ~= "atom" and atom.kind ~= "atom_proc" then return end
+	local events = p.word_events or {}
 	if   #events == 0 then return end
-	if is_runtime_helper(atom) then return end
 
 	local gpr_effects = duffle.INSTRUCTION_GPR_EFFECTS or {}
 	local read_positions = duffle.OPERAND_READ_POSITIONS or {}
@@ -1545,6 +1580,8 @@ local function check_mac_yield_uniformity(atom, pipe_ctx, findings)
 	if is_runtime_helper(atom) then return end
 	-- Per-kind semantics:
 	--   MipsAtom_          (baked atom): exactly 1 mac_yield at the end of the body. Control transfer is the atom's job.
+	--   MipsAtom_Proc_     (runtime-proc atom): exactly 1 mac_yield at the end of the body. Same as baked atom;
+	--                      the proc IS the atom; the runtime call to `atombuilder_unroll` doesn't introduce a parent atom.
 	--   MipsAtomComp_      (bare static-array component): ZERO mac_yield.
 	--                      The component is invoked from inside an atom body; the parent atom does the yield.
 	--   MipsAtomComp_Proc_ (procedural component): ZERO mac_yield.
@@ -1568,7 +1605,7 @@ local function check_mac_yield_uniformity(atom, pipe_ctx, findings)
 		return atom.line + line_in_body[tokens[idx].rel]
 	end
 
-	if atom.kind == "atom" then
+	if atom.kind == "atom" or atom.kind == "atom_proc" then
 		-- Baked atom: exactly 1 yield at the end.
 		if count == 0 then
 			findings[#findings + 1] = {
@@ -1613,6 +1650,7 @@ local function check_mac_yield_uniformity(atom, pipe_ctx, findings)
 		-- The parent atom does the yield.
 		-- A yield inside a component would either be dead code (bare) or prematurely terminate the function (proc).
 		-- Both are bugs.
+		-- `atom_proc` atoms are NOT components; they're runtime-proc atoms that own their own yield (handled in the `if` branch above).
 		if count > 0 then
 			findings[#findings + 1] = {
 				atom  = atom.name,
@@ -1644,7 +1682,7 @@ end
 --- Per-atom. Runtime-helper atoms (`debug_skip`) are exempt.
 --- Takes `(atom, pipe_ctx, findings)`; `pipe_ctx` is unused.
 local function check_yield_load_tail_pairing(atom, _pipe_ctx, findings)
-	if atom.kind ~= "atom" then return end
+	if atom.kind ~= "atom" and atom.kind ~= "atom_proc" then return end
 	if is_runtime_helper(atom) then return end
 
 	local tokens       = atom.paths.tokens
@@ -1656,21 +1694,39 @@ local function check_yield_load_tail_pairing(atom, _pipe_ctx, findings)
 		return atom.line + line_in_body[tokens[idx].rel]
 	end
 
-	-- ── Rule 1: every `mac_yield_load()` must be in a branch BD-slot.
+	-- ── Rule 1: every `mac_yield_load()` must be in a branch BD-slot, OR sit between two `atom_label`s (natural fall-through load pattern).
+	-- When the pattern is satisfied, the check stays silent; only violations emit findings.
 	for tok_idx = 1, n do
 		local c = tc[tok_idx]
 		if c.ident == "mac_yield_load" then
-			if tok_idx < 2 or not tc[tok_idx - 1].is_branch then
-				local prev_ident = (tok_idx >= 2) and (tc[tok_idx - 1].ident or "?") or "<none>"
-				findings[#findings + 1] = {
-					atom  = atom.name,
-					line  = tok_idx >= 2 and line_for(tok_idx) or atom.line,
-					check = "yield_load_tail_pairing",
-					kind  = "error",
-					msg   = string.format(
-						"%s at line %d has `mac_yield_load()` at word %d but the previous token is `%s`, not a branch — `mac_yield_load()` must fill a branch BD-slot."
-						, atom.name, tok_idx >= 2 and line_for(tok_idx) or atom.line, tok_idx, prev_ident),
-				}
+			local prev_tc = (tok_idx >= 2) and tc[tok_idx - 1] or nil
+			-- Look for the next `atom_label()` token (skip `atom_offset` markers; check immediately-adjacent first).
+			local next_label_tc = (tok_idx + 1 <= n) and tc[tok_idx + 1] or nil
+			if    next_label_tc and next_label_tc.ident ~= "atom_label" then
+				next_label_tc = nil
+				for j = tok_idx + 1, n do
+					local t = tc[j]
+					if t.ident == "atom_label" then
+						next_label_tc = t
+						break
+					end
+				end
+			end
+			local  natural_fallthrough = prev_tc and prev_tc.is_atom_label and next_label_tc ~= nil
+			if not natural_fallthrough then
+				if tok_idx < 2 or not prev_tc.is_branch then
+					local prev_ident = prev_tc and (prev_tc.ident or "?") or "<none>"
+					local next_ident = next_label_tc and (next_label_tc.ident .. "(" .. (next_label_tc.label_name or "?") .. ")") or "<no following label>"
+					findings[#findings + 1] = {
+						atom  = atom.name,
+						line  = tok_idx >= 2 and line_for(tok_idx) or atom.line,
+						check = "yield_load_tail_pairing",
+						kind  = "error",
+						msg   = string.format(
+							"%s at line %d has `mac_yield_load()` at word %d but the previous token is `%s`, not a branch — and the next `atom_label()` token is `%s` — `mac_yield_load()` must fill a branch BD-slot or sit between two `atom_label`s for the natural fall-through load."
+							, atom.name, tok_idx >= 2 and line_for(tok_idx) or atom.line, tok_idx, prev_ident, next_ident),
+					}
+				end
 			end
 		end
 	end
@@ -1845,9 +1901,9 @@ end
 ---   - Atoms containing a `mac_<name>(...)` call whose `name` is not registered in `pipe_ctx.components_by_name` emit a "new macro;
 ---     Not in corpus.components" advisory — the auto-derivation returned nil for that name.
 ---
---- Applies only to `kind = "atom"` (baked atoms). Components don't emit full primitives.
+--- Applies only to `kind = "atom"` or `kind = "atom_proc"` (full-atom bodies). Components don't emit full primitives.
 local function check_gpu_portstore_shape(atom, pipe_ctx, findings)
-	if atom.kind ~= "atom" then return end
+	if atom.kind ~= "atom" and atom.kind ~= "atom_proc" then return end
 	local tokens         = atom.paths.tokens
 	local line_in_body   = atom.paths.line_in_body
 	local tc             = atom.paths.tok_class
@@ -2015,8 +2071,9 @@ local function analyze_atom_paths(atom, pipe_ctx)
 						succ[#succ + 1] = label_pos + 1
 					end
 				end
-				-- For literal-offset jumps (label == false), the target is a non-tracked address; conservatively omit.
-				return succ, nil
+				-- For literal-offset jumps (label == false), control transfers out unconditionally.
+				-- Treat as a terminator so the path is recorded (NOT as a silent fall-through to the next token, which is unreachable in this atom's execution).
+				return {}, tok_idx
 			end
 			-- Conditional branch: BD slot absorbed; two successors — fall-through (tok_idx+2) + taken (if known).
 			if tok_idx + 2 <= n then
@@ -2032,9 +2089,11 @@ local function analyze_atom_paths(atom, pipe_ctx)
 			-- Return (succ, nil), the second value is the terminator marker (nil = not a terminator).
 			return succ, nil
 		end
-		-- Normal token: just the next one
+		-- Normal token: just the next one.
+		-- The final ordinary word of the body has no successor and terminates the path;
+		-- record it as an implicit endpoint so the cycle budget for non-yield components is not silently zeroed.
 		if tok_idx + 1 <= n then return { tok_idx + 1 }, nil end
-		return {}, nil
+		return {}, tok_idx
 	end
 
 	-- DFS through all paths. Track the current cycle sum, a visited set scoped to the current path (to detect loops), and a count of paths.
@@ -2329,6 +2388,184 @@ end
 
 
 -- ════════════════════════════════════════════════════════════════════════════
+-- ════════════════════════════════════════════════════════════════════════════
+-- GTE control-register alias + RT-diagonal + TR-naming helpers and checks
+-- ════════════════════════════════════════════════════════════════════════════
+
+--- Resolve a `gte_cr_<Alias>` ident to its alias-group entry, or nil if the alias
+--- is in a distinct-slot group (or the alias name is not a known C2 control-register alias).
+--- Reads `M.GTE_CR_ALIAS_GROUPS` from `duffle.lua`.
+local function find_alias_pair_for(alias_name, duffle)
+	local groups = (duffle and duffle.GTE_CR_ALIAS_GROUPS) or {}
+	for _, group in ipairs(groups) do
+		for _, name in ipairs(group[2] or {}) do
+			if name == alias_name then return group end
+		end
+	end
+	return nil
+end
+
+-- True iff `c` (a TokClass entry) is a CPU→COP2 control-register transfer
+-- (`gte_mv_to_ctrl_r` / `gte_mv_from_ctrl_r`).
+local function is_ctrl_r_transfer(c)
+	if c == nil then return false end
+	return c.ident == "gte_mv_to_ctrl_r" or c.ident == "gte_mv_from_ctrl_r"
+end
+
+-- Resolve a token's source line. The per-token `line` is the body-relative
+-- line; `atom.line` is the source line of the atom declaration; `line_in_body`
+-- (atom.paths) maps a body-relative line to its source line. The arithmetic
+-- `atom.line + line_in_body[tok.rel] - 1` matches the convention used by
+-- check_abi_handoff and check_control_transfer_delay_slot_use elsewhere.
+local function atom_body_token_source_line(atom, token, line_in_body)
+	if line_in_body == nil or token == nil or token.rel == nil then
+		return atom.line or 0
+	end
+	local body_line = line_in_body[token.rel]
+	if body_line == nil then return atom.line or 0 end
+	return (atom.line or 0) + body_line - 1
+end
+
+-- Check #N: gte_cr_alias_writes
+-- Fires one warning per atom per alias-group when the atom body touches two
+-- distinct aliases from the same group. Aliases within a group write to the
+-- same C2 control-register slot on real silicon; cross-alias writes inside
+-- one atom body silently clobber each other.
+--
+-- Severity: warning. Build continues. The libgte outer-product convention
+-- uses only RT-row aliases (which are NOT in `M.GTE_CR_ALIAS_GROUPS`), so
+-- the canonical convention does not trigger this check.
+local function check_gte_cr_alias_writes(atom, pipe_ctx, findings)
+	local groups = pipe_ctx.gte_cr_alias_groups or {}
+	if not next(groups) then return end
+
+	local tokens = atom.paths and atom.paths.tokens or {}
+	local tc     = atom.paths and atom.paths.tok_class or {}
+	local line_in_body = atom.paths and atom.paths.line_in_body
+	if not next(tokens) then return end
+
+	-- Build a per-group set of (alias, source_line) pairs touched in this atom body.
+	-- Walks every token; when the token is a ctrl-r transfer, the alias is at
+	-- position tok_idx + 2 (rt, alias, [imm-or-arg]). The pre-classified
+	-- `tc` table tells us whether the token is a ctrl-r transfer and what its
+	-- source line is.
+	local touched = {}
+	for tok_idx, token in ipairs(tokens) do
+		local c = tc[tok_idx]
+		if is_ctrl_r_transfer(c) and tokens[tok_idx + 2] then
+			local alias = tokens[tok_idx + 2].tok
+			local group = find_alias_pair_for(alias, pipe_ctx.duffle)
+			if group then
+				touched[group[1]] = touched[group[1]] or {}
+				touched[group[1]][#touched[group[1]] + 1] = {
+					alias = alias,
+					line  = atom_body_token_source_line(atom, token, line_in_body),
+				}
+			end
+		end
+	end
+
+	-- Fire one warning per group touched with 2+ distinct aliases.
+	for slot, hits in pairs(touched) do
+		local seen = {}
+		local distinct = {}
+		for _, h in ipairs(hits) do
+			if not seen[h.alias] then
+				seen[h.alias] = true
+				distinct[#distinct + 1] = h
+			end
+		end
+		if #distinct >= 2 then
+			local aliases = {}
+			for _, d in ipairs(distinct) do aliases[#aliases + 1] = d.alias end
+			findings[#findings + 1] = {
+				atom  = atom.name or "",
+				line  = distinct[1].line,
+				check = "gte_cr_alias_writes",
+				kind  = "warning",
+				msg   = string.format(
+					"atom '%s' touches %d aliases that share C2[%d]: %s; verify the intent"
+					, atom.name or "", #distinct, slot, table.concat(aliases, ", ")),
+			}
+		end
+	end
+end
+
+-- Check #N+1: rtdiagonal_completeness
+-- Fires one info per atom body when the bare `gte_cmdw_mvmva` macro is used.
+-- The bare macro encodes only the cmd field; the canonical libgte-2-pass
+-- shape uses `gte_cmdw_mvmva_c11_pass2_exact = 0x4A49E012` (gte.h:430).
+--
+-- Severity: info by default. Escalates to warning when
+-- `GTE_RT_DIAGONAL_STRICT=1` env var is set (CI / production builds).
+--
+-- The bare macro IS the right call for the canonical libgte outer-product
+-- convention, so this is an opt-out hint rather than a hard warning.
+local function check_rtdiagonal_completeness(atom, _pipe_ctx, findings)
+	local tokens = atom.paths and atom.paths.tokens or {}
+	local tc     = atom.paths and atom.paths.tok_class or {}
+	local line_in_body = atom.paths and atom.paths.line_in_body
+	if not next(tokens) then return end
+	local strict = os.getenv("GTE_RT_DIAGONAL_STRICT") == "1"
+	for tok_idx, token in ipairs(tokens) do
+		local c = tc[tok_idx]
+		if c and c.ident == "gte_cmdw_mvmva" then
+			findings[#findings + 1] = {
+				atom  = atom.name or "",
+				line  = atom_body_token_source_line(atom, token, line_in_body),
+				check = "rtdiagonal_completeness",
+				kind  = strict and "warning" or "info",
+				msg   = string.format(
+					"atom '%s' uses the bare gte_cmdw_mvmva macro; "
+					.. "the canonical libgte-2-pass shape is gte_cmdw_mvmva_c11_pass2_exact = 0x4A49E012 "
+					.. "(gte.h:430). The bare macro does not encode RT23/RT31/RT32/RT33; "
+					.. "for a full 3x3 matrix, use the dedicated literal or hand-build via enc_gte_*()."
+					, atom.name or ""),
+			}
+		end
+	end
+end
+
+-- Check #N+2: gte_cr_TR_naming
+-- Fires one info per atom body when a `gte_cr_TR[XYZ]` alias is used.
+-- Translation-vector registers are the only 3-letter-suffix C2 aliases
+-- (`TRX/TRY/TRZ`); an agent who reads `TRX` might typo it as `RT_X` or
+-- `RTX0` and either get a compile error (best case) or a build that
+-- links but routes the `ctc2` write to the wrong C2 slot.
+--
+-- Severity: info. The convention is correct; this is a documentation-pointer check.
+local function check_gte_cr_TR_naming(atom, _pipe_ctx, findings)
+	local tokens = atom.paths and atom.paths.tokens or {}
+	local tc     = atom.paths and atom.paths.tok_class or {}
+	local line_in_body = atom.paths and atom.paths.line_in_body
+	if not next(tokens) then return end
+	local touched = false
+	local first_line = 0
+	for tok_idx, token in ipairs(tokens) do
+		local c = tc[tok_idx]
+		if c and c.ident and c.ident:match("^gte_cr_TR[XYZ]$") then
+			touched = true
+			if first_line == 0 then
+				first_line = atom_body_token_source_line(atom, token, line_in_body)
+			end
+		end
+	end
+	if touched then
+		findings[#findings + 1] = {
+			atom  = atom.name or "",
+			line  = first_line,
+			check = "gte_cr_TR_naming",
+			kind  = "info",
+			msg   = string.format(
+				"atom '%s' uses gte_cr_TR[XYZ]; translation-vector registers are the only "
+				.. "3-letter-suffix C2 aliases (TRX/TRY/TRZ). See docs/gte_reference.md §"
+				.. "\"The `gte_cmdw_mvmva_c11_pass2_exact` literal\" for the libgte outer-product "
+				.. "convention that uses these names."
+				, atom.name or ""),
+		}
+	end
+end
+
 -- CHECK_RULES — data-driven check dispatch (Muratori: data over control flow)
 -- ════════════════════════════════════════════════════════════════════════════
 
@@ -2355,6 +2592,9 @@ local CHECK_RULES = {
 	{ name = "abi_handoff",                     per_atom   = check_abi_handoff                     },
 	{ name = "gpu_portstore_shape",             per_atom   = check_gpu_portstore_shape             },
 	{ name = "per_atom_cycle_budget",           per_atom   = check_per_atom_cycle_budget           },
+	{ name = "gte_cr_alias_writes",             per_atom   = check_gte_cr_alias_writes             },
+	{ name = "rtdiagonal_completeness",         per_atom   = check_rtdiagonal_completeness         },
+	{ name = "gte_cr_TR_naming",                per_atom   = check_gte_cr_TR_naming                },
 	{ name = "enum_alias_membership",           per_source = check_enum_alias_membership           },
 	{ name = "atom_type_consistency",           per_source = check_atom_type_consistency           },
 	{ name = "binds_no_substruct_deref",        per_source = check_binds_no_substruct_deref        },
@@ -2398,6 +2638,11 @@ local function build_corpus_pipe_ctx(ctx)
 		atom_infos_list         = corpus.atom_infos              or {},
 		-- Corpus-wide collisions (recorded by scan_source.merge_corpus_registries).
 		collisions              = corpus.collisions              or {},
+		-- GTE control-register alias groups (from `duffle.GTE_CR_ALIAS_GROUPS`).
+		-- The three new per_atom checks (gte_cr_alias_writes, rtdiagonal_completeness,
+		-- gte_cr_TR_naming) read from this view. `duffle` is exposed alongside so
+		-- `find_alias_pair_for` can resolve alias → group without a separate registry.
+		gte_cr_alias_groups     = duffle.GTE_CR_ALIAS_GROUPS or {},
 	}
 end
 

scripts/ps1_meta.lua

@@ -118,6 +118,12 @@ local PASSES = {
 		kind   = "header-output",
 		deps   = {"scan-source", "word-counts"},
 	},
+	auto_reg = {
+		module = "passes.auto_reg",
+		kind   = "header-output",
+		deps   = {"components"},
+		groups = { "pre-link" },
+	},
 	["emission-model"] = {
 		module = "passes.emission_model",
 		kind   = "validation",

scripts/update_deps.ps1

@@ -14,16 +14,21 @@ $url_armips     = 'https://github.com/Kingcom/armips.git'
 $url_pcsx_redux = 'https://github.com/grumpycoders/pcsx-redux.git'
 $url_psyq_iwyu  = 'https://github.com/johnbaumann/psyq_include_what_you_use.git'
 $url_lpeg       = 'https://github.com/roberto-ieru/LPeg.git'
+# $url_mkpsxiso   = 'https://github.com/Lameguy64/mkpsxiso.git'
+
+$url_mkpsxiso_win64 = 'https://github.com/Lameguy64/mkpsxiso/releases/download/v2.30/mkpsxiso-2.30-win64.zip'
 
 $path_armips     = join-path $path_toolchain 'armips'
 $path_pcsx_redux = join-path $path_toolchain 'pcsx-redux'
 $path_psyq_iwyu  = join-path $path_toolchain 'psyq_iwyu'
 $path_lpeg       = join-path $path_toolchain 'lpeg'
+$path_mkpsxiso   = join-path $path_toolchain 'mkpsxiso'
 
 clone-gitrepo $path_armips     $url_armips
 clone-gitrepo $path_lpeg       $url_lpeg
 clone-gitrepo $path_pcsx_redux $url_pcsx_redux
 clone-gitrepo $path_psyq_iwyu  $url_psyq_iwyu
+# clone-gitrepo $path_mkpsxiso   $url_mkpsxiso
 
 $path_armips_build = join-path $path_armips 'build'
 verify-path $path_armips_build
@@ -56,6 +61,119 @@ if (-not $msbuild_exe) {
 }
 
 $path_pcsx_sln = join-path $path_pcsx_redux 'vsprojects\pcsx-redux.sln'
+
+# ════════════════════════════════════════════════════════════════════════════
+# NuGet restore — required before MSBuild.
+# pcsx-redux's .vcxproj files use the legacy packages.config style with
+# hardcoded `<Import Project="..\packages\{id}.{ver}\...">` directives.
+# MSBuild's `/t:Restore` won't fetch missing packages here (the local
+# packages\ dir is checked but no package-source lookup happens), and
+# `dotnet restore` errors on packages.config projects, so we walk every
+# packages.config, parse out the <package id version/> entries, and pull
+# any missing .nupkg directly from api.nuget.org's flat container.
+# ════════════════════════════════════════════════════════════════════════════
+$path_pcsx_packages = join-path $path_pcsx_redux 'vsprojects\packages'
+$nuget_flat_container = 'https://api.nuget.org/v3-flatcontainer'
+
+# Collect required (id, version) pairs from every packages.config.
+$required_packages = @{}
+Get-ChildItem -Path (join-path $path_pcsx_redux 'vsprojects') -Filter 'packages.config' -Recurse -ErrorAction SilentlyContinue |
+    ForEach-Object {
+        [xml]$xml = Get-Content -LiteralPath $_.FullName -Raw
+        foreach ($pkg in $xml.packages.package) {
+            $key = '{0}|{1}' -f $pkg.id, $pkg.version
+            $required_packages[$key] = @{ id = $pkg.id; version = $pkg.version }
+        }
+    }
+
+# Ensure the packages root exists.
+if (-not (Test-Path -LiteralPath $path_pcsx_packages)) {
+    New-Item -ItemType Directory -Path $path_pcsx_packages -Force | Out-Null
+}
+
+# Download anything missing. Skip the package entirely if its dir already has
+# any contents (the legacy packages.config style means the targets file
+# location varies per package — `luajit.native` puts it at build/native/,
+# `glfw` puts it elsewhere — so we can't probe a specific path; just check
+# whether the dir is non-empty).
+Add-Type -AssemblyName System.IO.Compression.FileSystem
+foreach ($pkg in $required_packages.Values) {
+    $pkgDir = Join-Path $path_pcsx_packages ('{0}.{1}' -f $pkg.id, $pkg.version)
+    if ((Test-Path -LiteralPath $pkgDir) -and `
+        (@(Get-ChildItem -LiteralPath $pkgDir -Recurse -ErrorAction SilentlyContinue).Count -gt 0)) {
+        continue
+    }
+    $url = '{0}/{1}/{2}/{1}.{2}.nupkg' -f $nuget_flat_container, $pkg.id, $pkg.version
+    $nupkg = Join-Path $pkgDir ('{0}.{1}.nupkg' -f $pkg.id, $pkg.version)
+    New-Item -ItemType Directory -Path $pkgDir -Force | Out-Null
+    Write-Host "Fetching NuGet package: $($pkg.id) $($pkg.version)"
+    try {
+        Invoke-WebRequest -Uri $url -OutFile $nupkg -UseBasicParsing -ErrorAction Stop
+        [System.IO.Compression.ZipFile]::ExtractToDirectory($nupkg, $pkgDir)
+        Remove-Item -LiteralPath $nupkg -Force
+    } catch {
+        $msg = $_.Exception.Message
+        if ($msg -match '404') {
+            Write-Host "  Not on nuget.org (vendored?) — skipping $url"
+        } else {
+            Write-Warning "Failed to fetch $url — $msg"
+        }
+        if (Test-Path -LiteralPath $nupkg) { Remove-Item -LiteralPath $nupkg -Force }
+    }
+}
+
+# ════════════════════════════════════════════════════════════════════════════
+# isoffi.lua size guard — `core.vcxproj` #includes src/core/isoffi.lua into
+# luaiso.cc via the `-- lualoader, R"EOF(...)EOF"` trick. The raw string
+# literal between R"EOF(-- and -- )EOF" must stay under ~16,379 bytes or
+# MSVC (19.44) fails with C2026 (its actual raw-string limit is 16,384,
+# minus 5 bytes for the `-- lualoader, ` prefix). If the upstream file
+# grows past that, trim it: remove license header, trailing whitespace,
+# blank separators, inline comments, and shrink 4-space indent to 2-space.
+# Idempotent — only writes when the raw string exceeds the limit.
+# ════════════════════════════════════════════════════════════════════════════
+$path_isoffi = join-path $path_pcsx_redux 'src\core\isoffi.lua'
+if (Test-Path -LiteralPath $path_isoffi) {
+    $content = Get-Content -LiteralPath $path_isoffi -Raw -Encoding utf8
+    $startMarker = $content.IndexOf('R"EOF(--')
+    $endMarker   = $content.IndexOf('-- )EOF"')
+    $literalLen  = if ($startMarker -ge 0 -and $endMarker -gt $startMarker) {
+        $endMarker - ($startMarker + 8)
+    } else { -1 }
+    # Effective MSVC raw-string limit for the lualoader prefix is 16379 bytes.
+    if ($literalLen -gt 16379) {
+        Write-Host "isoffi.lua raw string is $literalLen bytes (>16379); trimming for MSVC C2026 limit."
+        $lines     = $content -split "`n"
+        $markerIdx = -1
+        for ($i = 0; $i -lt $lines.Length; $i++) {
+            if ($lines[$i] -match '^-- \)EOF"') { $markerIdx = $i; break }
+        }
+        $newLines = @()
+        for ($i = 0; $i -lt $lines.Length; $i++) {
+            $lineNum = $i + 1
+            $line    = $lines[$i]
+            # Keep the first line and the EOF-marker line untouched.
+            if ($i -eq 0 -or $i -eq $markerIdx) { $newLines += $line; continue }
+            # Drop the GPL license header (lines 2-17).
+            if ($lineNum -ge 2 -and $lineNum -le 17) { continue }
+            # Drop blank separator lines.
+            if ($line -match '^\s*$') { continue }
+            # Drop trailing whitespace.
+            $line = $line -replace '\s+$', ''
+            # Drop inline comments (anything from `--` to end of line).
+            $line = $line -replace '\s*--.*$', ''
+            # Shrink 4-space indent to 2-space.
+            $line = $line -replace '^(    )', '  '
+            if ($line -match '^\s*$') { continue }
+            $newLines += $line
+        }
+        ($newLines -join "`n") | Out-File -LiteralPath $path_isoffi -Encoding utf8 -NoNewline
+        $newLen = ((Get-Content -LiteralPath $path_isoffi -Raw -Encoding utf8) `
+            -replace '.*R"EOF\(--', '' -replace '-- \)EOF".*', '').Length
+        Write-Host "isoffi.lua trimmed: $literalLen -> $newLen bytes of raw string content."
+    }
+}
+
 & $msbuild_exe $path_pcsx_sln /p:Configuration=Release /p:Platform=x64 /p:PlatformToolset=v143 /m /v:minimal
 
 # Locate luajit via scoop. `luajit.exe` is on PATH via scoop's shim;
@@ -112,6 +230,17 @@ $lfs_dll_import = join-path $luajit_lib_dir 'libluajit-5.1.dll.a'
 # ════════════════════════════════════════════════════════════════════════════
 
 $path_openbios = join-path $path_pcsx_redux 'src\mips\openbios'
+
+# Wipe stale *.dep files across src\mips. These cache absolute paths to the
+# GCC headers directory; if the toolchain was upgraded (e.g. v14.2.0 → v16.1.0)
+# Make reads the stale paths and aborts with "no rule to make target .../stddef.h".
+# `make clean` in openbios only clears its own dir — subdirs like
+# common/crt0/, modplayer/, and shell/ keep their stale .dep files. Easier to
+# just delete the lot before each build than to teach every Makefile about
+# deepclean recursion.
+Get-ChildItem -Path (join-path $path_pcsx_redux 'src\mips') -Recurse -Filter '*.dep' -ErrorAction SilentlyContinue |
+    ForEach-Object { Remove-Item -LiteralPath $_.FullName -Force }
+
 push-location $path_openbios
 &	make clean
 &	make