last stuff for the night (need to clean up later)

code/duffle/dsl.h

@@ -28,6 +28,8 @@
 #define internal static // internal
 
 #define asm           __asm__
+#define align_(value) __attribute__((aligned (value)))             // for easy alignment
+
 #define align_(value) __attribute__((aligned (value)))             // for easy alignment
 #define C_(type,data) ((type)(data))                               // for enforced precedence
 #define expect_(x, y) __builtin_expect(x, y)                       // so compiler knows the common path

code/duffle/gcc_asm.h

@@ -32,106 +32,112 @@
     19, 18, 17, 16, 15, 14, 13, 12, 11, 10, \
     9,  8,  7,  6,  5,  4,  3,  2,  1,  0))
 
-/* --- 2. String Concatenation Helpers --- */
-#define _STR1  "%c0"
-#define _STR2  _STR1  ", %c1"
-#define _STR3  _STR2  ", %c2"
-#define _STR4  _STR3  ", %c3"
-#define _STR5  _STR4  ", %c4"
-#define _STR6  _STR5  ", %c5"
-#define _STR7  _STR6  ", %c6"
-#define _STR8  _STR7  ", %c7"
-#define _STR9  _STR8  ", %c8"
-#define _STR10 _STR9  ", %c9"
-#define _STR11 _STR10 ", %c10"
-#define _STR12 _STR11 ", %c11"
-#define _STR13 _STR12 ", %c12"
-#define _STR14 _STR13 ", %c13"
-#define _STR15 _STR14 ", %c14"
-#define _STR16 _STR15 ", %c15"
-#define _STR17 _STR16 ", %c16"
-#define _STR18 _STR17 ", %c17"
-#define _STR19 _STR18 ", %c18"
-#define _STR20 _STR19 ", %c19"
-#define _STR21 _STR20 ", %c20"
-#define _STR22 _STR21 ", %c21"
-#define _STR23 _STR22 ", %c22"
-#define _STR24 _STR23 ", %c23"
-#define _STR25 _STR24 ", %c24"
-#define _STR26 _STR25 ", %c25"
-#define _STR27 _STR26 ", %c26"
-#define _STR28 _STR27 ", %c27"
-#define _STR29 _STR28 ", %c28"
-#define _STR30 _STR29 ", %c29"
-#define _STR31 _STR30 ", %c30"
-#define _STR32 _STR31 ", %c31"
-#define _STR33 _STR32 ", %c32"
-#define _STR34 _STR33 ", %c33"
-#define _STR35 _STR34 ", %c34"
-#define _STR36 _STR35 ", %c35"
-#define _STR37 _STR36 ", %c36"
-#define _STR38 _STR37 ", %c37"
-#define _STR39 _STR38 ", %c38"
-#define _STR40 _STR39 ", %c39"
-#define _STR41 _STR40 ", %c40"
-#define _STR42 _STR41 ", %c41"
-#define _STR43 _STR42 ", %c42"
-#define _STR44 _STR43 ", %c43"
-#define _STR45 _STR44 ", %c44"
-#define _STR46 _STR45 ", %c45"
-#define _STR47 _STR46 ", %c46"
-#define _STR48 _STR47 ", %c47"
-#define _STR49 _STR48 ", %c48"
-#define _STR50 _STR49 ", %c49"
-#define _STR51 _STR50 ", %c50"
-#define _STR52 _STR51 ", %c51"
-#define _STR53 _STR52 ", %c52"
-#define _STR54 _STR53 ", %c53"
-#define _STR55 _STR54 ", %c54"
-#define _STR56 _STR55 ", %c55"
-#define _STR57 _STR56 ", %c56"
-#define _STR58 _STR57 ", %c57"
-#define _STR59 _STR58 ", %c58"
-#define _STR60 _STR59 ", %c59"
-#define _STR61 _STR60 ", %c60"
-#define _STR62 _STR61 ", %c61"
-#define _STR63 _STR62 ", %c62"
-#define _STR64 _STR63 ", %c63"
-#define _STR65 _STR64 ", %c64"
-#define _STR66 _STR65 ", %c65"
-#define _STR67 _STR66 ", %c66"
-#define _STR68 _STR67 ", %c67"
-#define _STR69 _STR68 ", %c68"
-#define _STR70 _STR69 ", %c69"
-#define _STR71 _STR70 ", %c70"
-#define _STR72 _STR71 ", %c71"
-#define _STR73 _STR72 ", %c72"
-#define _STR74 _STR73 ", %c73"
-#define _STR75 _STR74 ", %c74"
-#define _STR76 _STR75 ", %c75"
-#define _STR77 _STR76 ", %c76"
-#define _STR78 _STR77 ", %c77"
-#define _STR79 _STR78 ", %c78"
-#define _STR80 _STR79 ", %c79"
-#define _STR81 _STR80 ", %c80"
-#define _STR82 _STR81 ", %c81"
-#define _STR83 _STR82 ", %c82"
-#define _STR84 _STR83 ", %c83"
-#define _STR85 _STR84 ", %c84"
-#define _STR86 _STR85 ", %c85"
-#define _STR87 _STR86 ", %c86"
-#define _STR88 _STR87 ", %c87"
-#define _STR89 _STR88 ", %c88"
-#define _STR90 _STR89 ", %c89"
-#define _STR91 _STR90 ", %c90"
-#define _STR92 _STR91 ", %c91"
-#define _STR93 _STR92 ", %c92"
-#define _STR94 _STR93 ", %c93"
-#define _STR95 _STR94 ", %c94"
-#define _STR96 _STR95 ", %c95"
-#define _STR97 _STR96 ", %c96"
-#define _STR98 _STR97 ", %c97"
-#define _STR99 _STR98 ", %c98"
+/* --- 2. String Concatenation Helpers --- *
+ * NOTE: we use `%0`, `%1`, ... not `%c0`, `%c1`, ... because GCC's
+ * asm-parser rejects `%cN` in this position with "invalid use of '%c'".
+ * The `%cN` form is for printing *character* constants; for arbitrary
+ * integer immediates (the only kind `"i"(...)` produces), the plain
+ * `%N` form is the right one. Both expand to the bare immediate.
+ */
+#define _STR1  "%0"
+#define _STR2  _STR1  ", %1"
+#define _STR3  _STR2  ", %2"
+#define _STR4  _STR3  ", %3"
+#define _STR5  _STR4  ", %4"
+#define _STR6  _STR5  ", %5"
+#define _STR7  _STR6  ", %6"
+#define _STR8  _STR7  ", %7"
+#define _STR9  _STR8  ", %8"
+#define _STR10 _STR9  ", %9"
+#define _STR11 _STR10 ", %10"
+#define _STR12 _STR11 ", %11"
+#define _STR13 _STR12 ", %12"
+#define _STR14 _STR13 ", %13"
+#define _STR15 _STR14 ", %14"
+#define _STR16 _STR15 ", %15"
+#define _STR17 _STR16 ", %16"
+#define _STR18 _STR17 ", %17"
+#define _STR19 _STR18 ", %18"
+#define _STR20 _STR19 ", %19"
+#define _STR21 _STR20 ", %20"
+#define _STR22 _STR21 ", %21"
+#define _STR23 _STR22 ", %22"
+#define _STR24 _STR23 ", %23"
+#define _STR25 _STR24 ", %24"
+#define _STR26 _STR25 ", %25"
+#define _STR27 _STR26 ", %26"
+#define _STR28 _STR27 ", %27"
+#define _STR29 _STR28 ", %28"
+#define _STR30 _STR29 ", %29"
+#define _STR31 _STR30 ", %30"
+#define _STR32 _STR31 ", %31"
+#define _STR33 _STR32 ", %32"
+#define _STR34 _STR33 ", %33"
+#define _STR35 _STR34 ", %34"
+#define _STR36 _STR35 ", %35"
+#define _STR37 _STR36 ", %36"
+#define _STR38 _STR37 ", %37"
+#define _STR39 _STR38 ", %38"
+#define _STR40 _STR39 ", %39"
+#define _STR41 _STR40 ", %40"
+#define _STR42 _STR41 ", %41"
+#define _STR43 _STR42 ", %42"
+#define _STR44 _STR43 ", %43"
+#define _STR45 _STR44 ", %44"
+#define _STR46 _STR45 ", %45"
+#define _STR47 _STR46 ", %46"
+#define _STR48 _STR47 ", %47"
+#define _STR49 _STR48 ", %48"
+#define _STR50 _STR49 ", %49"
+#define _STR51 _STR50 ", %50"
+#define _STR52 _STR51 ", %51"
+#define _STR53 _STR52 ", %52"
+#define _STR54 _STR53 ", %53"
+#define _STR55 _STR54 ", %54"
+#define _STR56 _STR55 ", %55"
+#define _STR57 _STR56 ", %56"
+#define _STR58 _STR57 ", %57"
+#define _STR59 _STR58 ", %58"
+#define _STR60 _STR59 ", %59"
+#define _STR61 _STR60 ", %60"
+#define _STR62 _STR61 ", %61"
+#define _STR63 _STR62 ", %62"
+#define _STR64 _STR63 ", %63"
+#define _STR65 _STR64 ", %64"
+#define _STR66 _STR65 ", %65"
+#define _STR67 _STR66 ", %66"
+#define _STR68 _STR67 ", %67"
+#define _STR69 _STR68 ", %68"
+#define _STR70 _STR69 ", %69"
+#define _STR71 _STR70 ", %70"
+#define _STR72 _STR71 ", %71"
+#define _STR73 _STR72 ", %72"
+#define _STR74 _STR73 ", %73"
+#define _STR75 _STR74 ", %74"
+#define _STR76 _STR75 ", %75"
+#define _STR77 _STR76 ", %76"
+#define _STR78 _STR77 ", %77"
+#define _STR79 _STR78 ", %78"
+#define _STR80 _STR79 ", %79"
+#define _STR81 _STR80 ", %80"
+#define _STR82 _STR81 ", %81"
+#define _STR83 _STR82 ", %82"
+#define _STR84 _STR83 ", %83"
+#define _STR85 _STR84 ", %84"
+#define _STR86 _STR85 ", %85"
+#define _STR87 _STR86 ", %86"
+#define _STR88 _STR87 ", %87"
+#define _STR89 _STR88 ", %88"
+#define _STR90 _STR89 ", %89"
+#define _STR91 _STR90 ", %90"
+#define _STR92 _STR91 ", %91"
+#define _STR93 _STR92 ", %92"
+#define _STR94 _STR93 ", %93"
+#define _STR95 _STR94 ", %94"
+#define _STR96 _STR95 ", %95"
+#define _STR97 _STR96 ", %96"
+#define _STR98 _STR97 ", %97"
+#define _STR99 _STR98 ", %98"
 
 /* Utilizing cascading operand strings to compress the payload */
 #define _OP10 "i"(p0),"i"(p1),"i"(p2),"i"(p3),"i"(p4),"i"(p5),"i"(p6),"i"(p7),"i"(p8),"i"(p9)
@@ -254,9 +260,143 @@
 #define _INL_98(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82,p83,p84,p85,p86,p87,p88,p89,p90,p91,p92,p93,p94,p95,p96,p97) ".word " _STR98 : : _OP90,"i"(p90),"i"(p91),"i"(p92),"i"(p93),"i"(p94),"i"(p95),"i"(p96),"i"(p97)
 #define _INL_99(p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p44,p45,p46,p47,p48,p49,p50,p51,p52,p53,p54,p55,p56,p57,p58,p59,p60,p61,p62,p63,p64,p65,p66,p67,p68,p69,p70,p71,p72,p73,p74,p75,p76,p77,p78,p79,p80,p81,p82,p83,p84,p85,p86,p87,p88,p89,p90,p91,p92,p93,p94,p95,p96,p97,p98) ".word " _STR99 : : _OP90,"i"(p90),"i"(p91),"i"(p92),"i"(p93),"i"(p94),"i"(p95),"i"(p96),"i"(p97),"i"(p98)
 
-/* The AST Builders */
-#define asm_clobber(...) : __VA_ARGS__
-#define asm_inline(...)  m_expand(glue(_INL_, _ASM_COUNT_ARGS(__VA_ARGS__))(__VA_ARGS__))
+/* ============================================================================
+ * AST BUILDERS — assemble a complete inline-asm block
+ * ============================================================================
+ *
+ * A complete GCC inline-asm statement has up to 4 sections separated by `:`:
+ *
+ *   asm volatile ( "code" : OUTPUTS : INPUTS : CLOBBERS );
+ *
+ * Every section-builder below prepends the `:` separator that GCC requires,
+ * so you can compose them inline without thinking about punctuation. The
+ * master `asm_block(...)` then wraps the four sections in `asm volatile (...)`.
+ *
+ *   asm_block(
+ *       asm_code( "..." ),
+ *       asm_out  ( "=r"(x), "+m"(y) ),   // optional
+ *       asm_in   ( "r"(a),  "m"(b)  ),   // optional
+ *       asm_clb  ( "$8", "memory"  )    // optional
+ *   );
+ *
+ * Common idioms (kept for back-compat / terseness):
+ *
+ *   asm_blob(asm_inline(...), asm_clobber(...))   // 2-section, no I/O
+ *   asm_block(asm_inline(...), , , )              // 4-section, empty
+ */
 
-/* The Shell */
-#define asm_blob(inlines, clobbers) asm volatile ( inlines clobbers )
+/* `asm_code` is a passthrough — it does NOT prepend a colon, since the code
+ * section is always the first (no separator needed before it). The format
+ * string + `"i"(...)` operand list are produced by `asm_inline(...)` and
+ * just pass through unchanged. */
+#define asm_code(...)         __VA_ARGS__
+
+/* `asm_out`  prepends `:` — separates code/outputs/inputs/clobbers */
+#define asm_out(...)          : __VA_ARGS__
+/* `asm_in`   prepends `:` */
+#define asm_in(...)           : __VA_ARGS__
+/* `asm_clb`  prepends `:` */
+#define asm_clb(...)          : __VA_ARGS__
+
+/* `asm_clobber` is the legacy single-section name. Kept for existing
+ * call-sites that put inputs *before* clobbers and want both as one colon-
+ * prefixed block (i.e. the user wrote `: "r"(x) ... : "..."` by hand). */
+#define asm_clobber(...)      : __VA_ARGS__
+
+/* `asm_inline(...)` dispatches into `_INL_<count>` to emit up to 99 encoded
+ * instruction words. This is the "compiled-instruction" form of `asm_code`.
+ *
+ * Result is a 2-colon body WITHOUT the final clobber section:
+ *   ".word %c0, %c1, ..." : : "i"(p0), "i"(p1)
+ *   |----- code -----|   |--- empty ---|  |------- inputs -------|
+ *
+ * Use it inside `asm volatile( ... )` like so:
+ *
+ *   asm volatile(
+ *       asm_inline(w0, w1, w3)
+ *       : clobbers
+ *   )
+ *
+ * which expands to:
+ *
+ *   asm volatile(
+ *       ".word %c0, %c1, %c2" : : "i"(w0), "i"(w1), "i"(w2)
+ *       : "$2", "$8", ...
+ *   )
+ *
+ * 3 colons total. Always valid. */
+#define asm_inline(...)       m_expand(glue(_INL_, _ASM_COUNT_ARGS(__VA_ARGS__))(__VA_ARGS__))
+
+/* reg_str(n) — Stringify an integer register id into the GCC asm
+ * string form (e.g. 12 → "$12"). Use this anywhere GCC's parser
+ * expects a literal string identifying a register: clobber lists,
+ * asm templates, etc. The two-level macro is the standard preprocessor
+ * idiom for forcing one level of expansion before stringify — without
+ * it, `#n` would stringify the macro name `R_T4` to `"R_T4"` instead
+ * of expanding `R_T4` to its value first.
+ *
+ * For declaring a register variable bound to a specific GPR, use the
+ * `rgcc(n)` bundle from gcc_asm.h instead — it adds the `__asm__()`
+ * qualifier around the string.
+ *
+ *   register V3_S2* p0 __asm__(reg_str(R_T4)) = ...;        // verbose
+ *   register V3_S2* p0 rgcc(R_T4) = ...;                    // bundled
+ *
+ *   asm volatile("nop" : : : reg_str(R_RA), "memory");      // clobber list */
+#define reg_str_(n)  "$" #n
+#define reg_str(n)   reg_str_(n)
+
+/* ------------------------------------------------------------------------ *
+ *  rgcc(n) — GCC-specific bundle for register-variable declarations.
+ *
+ *  Produces `__asm__(reg_str(tmpl(n, Code)))` at expansion time. The
+ *  `tmpl(n, Code)` indirection derives the preprocessor-visible `_Code`
+ *  form from the enum name (which the preprocessor can't expand on
+ *  its own). So a call like
+ *
+ *      register V3_S2* p rgcc(R_T4) = verts[0].ptr;
+ *
+ *  expands (via tmpl) to
+ *
+ *      register V3_S2* p __asm__(reg_str(R_T4_Code))
+ *                                = verts[0].ptr;
+ *
+ *  which (via reg_str) becomes
+ *
+ *      register V3_S2* p __asm__("$12") = verts[0].ptr;
+ *
+ *  Why bundle the `__asm__()` wrapper?
+ *    - The integer R_T4 (= 12, via R_T4_Code) is the canonical truth.
+ *    - The string "$12" is derived from it via reg_str, so they
+ *      cannot drift apart.
+ *    - Spelling `__asm__(reg_str(R_T4_Code))` at every call site is
+ *      noise. `rgcc(R_T4)` says what you mean.
+ *
+ *  The two-level form (rgcc_/rgcc) is the standard preprocessor idiom
+ *  for forcing one level of expansion before the bundle's `__asm__`
+ *  token is written; without it, `rgcc(R_T4)` would expand to
+ *  `__asm__(reg_str(tmpl(R_T4, Code)))` but the inner `tmpl(R_T4, Code)`
+ *  would token-paste prematurely.
+ *
+ *  Layering: reg_str lives in dsl.h (the integer-to-string primitive,
+ *  compiler-agnostic in name). tmpl lives in dsl.h (the token-paste
+ *  glue). rgcc lives here (gcc_asm.h) because the `__asm__` keyword
+ *  is GCC-specific. Anyone porting to a different compiler's asm
+ *  dialect overrides rgcc, and the integer→string derivation in
+ *  reg_str can be retargeted in one place.
+ *
+ *  For clobber lists and asm-template strings, use the bare
+ *  `reg_str(R_T4_Code)` — you don't want __asm__() there, you just
+ *  want the string.
+ * ------------------------------------------------------------------------ */
+#define rgcc_(n)       __asm__(reg_str(tmpl(n, Code)))
+#define rgcc(n)        rgcc_(n)
+
+/* rgcc_ref(n) — GCC operand-reference form "%N". Not currently used
+ * by the placeholder-pun macros (the .word bodies are fully baked
+ * at compile time and have no runtime operand references), but kept
+ * here for completeness in case a future asm template needs to refer
+ * to a runtime input by position. Mirror of rgcc but produces "%N"
+ * instead of "$N". */
+#define rgcc_ref_(n)   "%" #n
+#define rgcc_ref(n)    rgcc_ref_(n)

code/duffle/gte.h

@@ -5,18 +5,123 @@
 #	include "mips.h"
 #endif
 
+/* ============================================================================
+ *  gte.h — Geometry Transformation Engine (COP2) for the PS1
+ * ============================================================================
+ *
+ *  Hand-rolled DSL for emitting GTE/MIPS instruction words as raw `.word`
+ *  constants from C. No GCC inline-assembly string syntax in the code body.
+ *
+ *  PHILOSOPHY
+ *  ----------
+ *  1. A 32-bit instruction word is composed from per-field encoders. Each
+ *     encoder knows only its own bit range; the composite ORs them together.
+ *     No magic numbers inside any encoder body — every shift and mask is a
+ *     named constant from the bitfield-layout enum below.
+ *
+ *  2. Pure (compile-time) instructions — every GTE *command* (RTPS, RTPT,
+ *     NCLIP, MVMVA, …) and every COP2 *transfer* (ctc2/cfc2) with a constant
+ *     rs/rt/rd — are emitted as a single integer constant via
+ *     `asm_inline(...)` from gcc_asm.h. The C compiler constant-folds
+ *     these into `.word` directives in .rodata.
+ *
+ *  3. Runtime-base-register instructions (lwc2, swc2, lw, sw, …) cannot be
+ *     a pure compile-time word because the `rs` field is chosen by the
+ *     compiler at codegen. For these we use a "placeholder-pun" pattern:
+ *     a fixed register number (R_T4 = $12) is baked into the rs field of
+ *     the `.word` constant, and the macro declares a `"r"(arg)` input
+ *     constraint plus a clobber on the same register. The compiler is
+ *     therefore *forced* to bind `arg` to that exact register, and the
+ *     constant is correct.
+ *
+ *  USAGE
+ *  -----
+ *      // Pure command sequence — all bits compile-time:
+ *      asm volatile(
+ *          asm_inline( gte_cmd_rtpt , gte_cmd_nclip , gte_cmd_avsz3 )
+ *          asm_clobber( clb_system )
+ *      );
+ *
+ *      // Runtime-base-register load — caller picks the base GPR:
+ *      register V3_S2* p_in_12 __asm__("$12") = verts[0].ptr;
+ *      gte_load_v0(p_in_12, R_T4);   // R_T4 = 12 = $t4 = $12
+ *
+ *      // Three independent bases for an RTPT pipeline:
+ *      register V3_S2* p0 __asm__("$12") = verts[0].ptr;
+ *      register V3_S2* p1 __asm__("$13") = verts[1].ptr;
+ *      register V3_S2* p2 __asm__("$14") = verts[2].ptr;
+ *      gte_load_v0(p0, R_T4);
+ *      gte_load_v1(p1, R_T5);
+ *      gte_load_v2(p2, R_T6);
+ *      gte_rtpt();
+ *
+ *  STYLE NOTES
+ *  -----------
+ *  - Per-field encoders are named `enc_gte_<field>(value)` and each one
+ *    self-masks its argument before shifting. Mirrors the `enc_op / enc_rs
+ *    / enc_rt / ...` family in mips.h.
+ *  - The composite `enc_gte_cmdw(sf, mx, v, cv, lm, cmd)` is a flat OR of
+ *    the per-field encoders, plus the COP2/CO base.
+ *  - Pre-baked shortcuts (`gte_cmd_rtpt`, `gte_cmd_rtps`, …) are defined
+ *    for the common cases so call sites read like assembly source.
+ *  - All register/field values are enums (not `#define`s) so they show up
+ *    in debugger symbol tables and IDE autocomplete.
+ *
+ *  SEE ALSO
+ *  --------
+ *  - gcc_asm.h: the `.word` emitter (`asm_inline`, `asm_clobber`, clobbers)
+ *  - mips.h:    the MIPS encoder layer this builds on
+ */
+
 /* C2 data registers */
 
-/* --- GTE Data Registers (Coprocessor 2) --- */
+/* --- GTE Data Registers (Coprocessor 2) ---
+ * Preprocessor-visible integer ids for the COP2 data register file.
+ * Each enum value is bound to a parallel `_Code` `#define` so the
+ * preprocessor can stringify the integer (for `reg_str`/`rgcc` paths).
+ * Same pattern as the GPR `_Code` set in mips.h. */
+#define C2_VXY0_Code  0
+#define C2_VZ0_Code   1
+#define C2_VXY1_Code  2
+#define C2_VZ1_Code   3
+#define C2_VXY2_Code  4
+#define C2_VZ2_Code   5
+#define C2_RGB_Code   6
+#define C2_OTZ_Code   7
+#define C2_IR0_Code   8
+#define C2_IR1_Code   9
+#define C2_IR2_Code  10
+#define C2_IR3_Code  11
+#define C2_SXY0_Code 12
+#define C2_SXY1_Code 13
+#define C2_SXY2_Code 14
+#define C2_SXYP_Code 15
+#define C2_SZ0_Code  16
+#define C2_SZ1_Code  17
+#define C2_SZ2_Code  18
+#define C2_SZ3_Code  19
+#define C2_RGB0_Code 20
+#define C2_RGB1_Code 21
+#define C2_RGB2_Code 22
+#define C2_RES1_Code 23
+#define C2_MAC0_Code 24
+#define C2_MAC1_Code 25
+#define C2_MAC2_Code 26
+#define C2_MAC3_Code 27
+#define C2_IRGB_Code 28
+#define C2_ORGB_Code 29
+#define C2_LZCS_Code 30
+#define C2_LZCR_Code 31
+
 enum {
-	C2_VXY0 = 0,  C2_VZ0  = 1,  C2_VXY1 = 2,  C2_VZ1  = 3,
-	C2_VXY2 = 4,  C2_VZ2  = 5,  C2_RGB  = 6,  C2_OTZ  = 7,
-	C2_IR0  = 8,  C2_IR1  = 9,  C2_IR2  = 10, C2_IR3  = 11,
-	C2_SXY0 = 12, C2_SXY1 = 13, C2_SXY2 = 14, C2_SXYP = 15,
-	C2_SZ0  = 16, C2_SZ1  = 17, C2_SZ2  = 18, C2_SZ3  = 19,
-	C2_RGB0 = 20, C2_RGB1 = 21, C2_RGB2 = 22, C2_RES1 = 23,
-	C2_MAC0 = 24, C2_MAC1 = 25, C2_MAC2 = 26, C2_MAC3 = 27,
-	C2_IRGB = 28, C2_ORGB = 29, C2_LZCS = 30, C2_LZCR = 31
+	C2_VXY0 = C2_VXY0_Code, C2_VZ0  = C2_VZ0_Code,  C2_VXY1 = C2_VXY1_Code, C2_VZ1  = C2_VZ1_Code,
+	C2_VXY2 = C2_VXY2_Code, C2_VZ2  = C2_VZ2_Code,  C2_RGB  = C2_RGB_Code,  C2_OTZ  = C2_OTZ_Code,
+	C2_IR0  = C2_IR0_Code,  C2_IR1  = C2_IR1_Code,  C2_IR2  = C2_IR2_Code,  C2_IR3  = C2_IR3_Code,
+	C2_SXY0 = C2_SXY0_Code, C2_SXY1 = C2_SXY1_Code, C2_SXY2 = C2_SXY2_Code, C2_SXYP = C2_SXYP_Code,
+	C2_SZ0  = C2_SZ0_Code,  C2_SZ1  = C2_SZ1_Code,  C2_SZ2  = C2_SZ2_Code,  C2_SZ3  = C2_SZ3_Code,
+	C2_RGB0 = C2_RGB0_Code, C2_RGB1 = C2_RGB1_Code, C2_RGB2 = C2_RGB2_Code, C2_RES1 = C2_RES1_Code,
+	C2_MAC0 = C2_MAC0_Code, C2_MAC1 = C2_MAC1_Code, C2_MAC2 = C2_MAC2_Code, C2_MAC3 = C2_MAC3_Code,
+	C2_IRGB = C2_IRGB_Code, C2_ORGB = C2_ORGB_Code, C2_LZCS = C2_LZCS_Code, C2_LZCR = C2_LZCR_Code
 };
 
 /* Semantic Aliases for GTE Data Registers */
@@ -104,24 +209,86 @@ enum {
 	gte_shift_cmd =  0,  gte_width_cmd = 6,  gte_mask_cmd = 0x3F,
 };
 
-/* --- GTE Control Register Indices (for ctc2/cfc2) --- */
+/* --- GTE Control Register Indices (for ctc2/cfc2) ---
+ * Preprocessor-visible integer ids for the COP2 control register file.
+ * Each enum value is bound to a parallel `_Code` `#define` so the
+ * preprocessor can stringify the integer (for `reg_str`/`rgcc` paths).
+ * Same pattern as the GPR `_Code` set in mips.h. Note: indices 21-23
+ * are reserved/unused on real hardware, so there's a gap. */
+#define gte_cr_RT11_Code  0
+#define gte_cr_RT12_Code  1
+#define gte_cr_RT13_Code  2
+#define gte_cr_RT21_Code  3
+#define gte_cr_RT22_Code  4
+#define gte_cr_RT23_Code  5
+#define gte_cr_RT31_Code  6
+#define gte_cr_RT32_Code  7
+#define gte_cr_RT33_Code  8
+#define gte_cr_TRX_Code   9
+#define gte_cr_TRY_Code  10
+#define gte_cr_TRZ_Code  11
+#define gte_cr_L11_Code  12
+#define gte_cr_L12_Code  13
+#define gte_cr_L13_Code  14
+#define gte_cr_L21_Code  15
+#define gte_cr_L22_Code  16
+#define gte_cr_L23_Code  17
+#define gte_cr_LR1_Code  18
+#define gte_cr_LR2_Code  19
+#define gte_cr_LR3_Code  20
+#define gte_cr_RBK_Code  24
+#define gte_cr_GBK_Code  25
+#define gte_cr_BBK_Code  26
+#define gte_cr_RFC_Code  27
+#define gte_cr_GFC_Code  28
+#define gte_cr_BFC_Code  29
+#define gte_cr_OFX_Code  30
+#define gte_cr_OFY_Code  31
 
 enum {
-    gte_cr_RT11 = 0,  gte_cr_RT12 = 1,  gte_cr_RT13 = 2,
-    gte_cr_RT21 = 3,  gte_cr_RT22 = 4,  gte_cr_RT23 = 5,
-    gte_cr_RT31 = 6,  gte_cr_RT32 = 7,  gte_cr_RT33 = 8,
-    gte_cr_TRX  = 9,  gte_cr_TRY  = 10, gte_cr_TRZ  = 11,
-    gte_cr_L11  = 12, gte_cr_L12  = 13, gte_cr_L13  = 14,
-    gte_cr_L21  = 15, gte_cr_L22  = 16, gte_cr_L23  = 17,
-    gte_cr_LR1  = 18, gte_cr_LR2  = 19, gte_cr_LR3  = 20,
-    gte_cr_RBK  = 24, gte_cr_GBK  = 25, gte_cr_BBK  = 26,
-    gte_cr_RFC  = 27, gte_cr_GFC  = 28, gte_cr_BFC  = 29,
-    gte_cr_OFX  = 30, gte_cr_OFY  = 31,
+    gte_cr_RT11 = gte_cr_RT11_Code, gte_cr_RT12 = gte_cr_RT12_Code, gte_cr_RT13 = gte_cr_RT13_Code,
+    gte_cr_RT21 = gte_cr_RT21_Code, gte_cr_RT22 = gte_cr_RT22_Code, gte_cr_RT23 = gte_cr_RT23_Code,
+    gte_cr_RT31 = gte_cr_RT31_Code, gte_cr_RT32 = gte_cr_RT32_Code, gte_cr_RT33 = gte_cr_RT33_Code,
+    gte_cr_TRX  = gte_cr_TRX_Code,  gte_cr_TRY  = gte_cr_TRY_Code,  gte_cr_TRZ  = gte_cr_TRZ_Code,
+    gte_cr_L11  = gte_cr_L11_Code,  gte_cr_L12  = gte_cr_L12_Code,  gte_cr_L13  = gte_cr_L13_Code,
+    gte_cr_L21  = gte_cr_L21_Code,  gte_cr_L22  = gte_cr_L22_Code,  gte_cr_L23  = gte_cr_L23_Code,
+    gte_cr_LR1  = gte_cr_LR1_Code,  gte_cr_LR2  = gte_cr_LR2_Code,  gte_cr_LR3  = gte_cr_LR3_Code,
+    gte_cr_RBK  = gte_cr_RBK_Code,  gte_cr_GBK  = gte_cr_GBK_Code,  gte_cr_BBK  = gte_cr_BBK_Code,
+    gte_cr_RFC  = gte_cr_RFC_Code,  gte_cr_GFC  = gte_cr_GFC_Code,  gte_cr_BFC  = gte_cr_BFC_Code,
+    gte_cr_OFX  = gte_cr_OFX_Code,  gte_cr_OFY  = gte_cr_OFY_Code,
 };
 
-/* COP2 (GTE) Transfer Format
- * Opcode is always op_cop2. The 'sub' field determines direction (MT/MF). */
-#define enc_cop2_tx(sub, rt, rd) enc_op(op_cop2) | enc_rs(sub) | enc_rt(rt) | enc_rd(rd)
+enum { _C2_OPS_ = 0
+
+	, op_lwc2    = 0x32 /* Load Word to Coprocessor 2 (GTE) */
+	, op_swc2    = 0x3A /* Store Word from Coprocessor 2 (GTE) */
+};
+
+/* COP2 (GTE) Transfer Format: ctc2 rt, rd or cfc2 rt, rd
+ * Layout: [op_cop2:6][sub:5][rt:5][rd:5][0:11]
+ *   - sub: cop_mf (0x00) for cfc2, cop_mt (0x04) for ctc2
+ *   - rt:  GPR source/dest
+ *   - rd:  COP2 control register index (0..31) */
+#define enc_cop2_tx(sub, rt, rd) (enc_op(op_cop2) | enc_rs(sub) | enc_rt(rt) | enc_rd(rd))
+
+/* COP2 Data Load (lwc2): `lwc2 rt, off(rs)`
+ * Layout: [op_lwc2:6][rs:5][rt:5][imm:16]
+ *   - rs: GPR base address
+ *   - rt: COP2 data register index (0..31)
+ *   - imm: signed 16-bit offset
+ * NOTE: When `rs` is a runtime register, the encoding cannot be pre-baked
+ * into a .word — use the string-style `gte_load_v0` macro below instead. */
+#define enc_cop2_lwc2(rt, base, off)  enc_i(op_lwc2, (base), (rt), (off))
+#define enc_cop2_swc2(rt, base, off)  enc_i(op_swc2, (base), (rt), (off))
+
+/* Semantic aliases for the COP2 data load/store. The `c2` in `lwc2`/
+ * `swc2` is redundant when we're already inside the `gte_` namespace.
+ *   gte_lw rt, base, off  →  lwc2 rt, off(base)
+ *   gte_sw rt, base, off  →  swc2 rt, off(base)
+ * For the typical user-facing vector-level load (xy + z as two
+ * instructions), use the higher-level `gte_load_vN` macros below. */
+#define gte_lw(rt, base, off)          enc_cop2_lwc2(rt, base, off)
+#define gte_sw(rt, base, off)          enc_cop2_swc2(rt, base, off)
 
 /* GTE Command Format (The math engine trigger)
  * Opcode is always MIPS_OP_COP2, RS is always 1 (CO).
@@ -145,7 +312,7 @@ enum {
 #define enc_gte_cmd(cmd)     (((cmd) & gte_mask_cmd) << gte_shift_cmd)
 
 /* Composite: all six GTE fields + the COP2/CO base. */
-#define enc_gte_cmd(sf, mx, v, cv, lm, cmd) ( \
+#define enc_gte_cmdw(sf, mx, v, cv, lm, cmd) ( \
      gte_cmd_base     \
    | enc_gte_sf(sf)   \
    | enc_gte_mx(mx)   \
@@ -155,6 +322,147 @@ enum {
    | enc_gte_cmd(cmd) \
 )
 
+/**
+ * @brief Loads a single SVECTOR to GTE vector register V0
+ *
+ * @details Loads values from an SVECTOR struct to GTE data registers C2_VXY0
+ * (XY at offset 0) and C2_VZ0 (Z at offset 4) using `lwc2`.
+ *
+ * Uses string-style GCC inline asm with `%0` substitution because the
+ * base register `r0` is a runtime GPR chosen by the compiler — it cannot
+ * be encoded into a static `.word` constant.
+ *
+ * Usage:
+ *   asm_gte_load_v0(svector_ptr);
+ */
+
+/* Pre-baked lwc2 encoding helpers parameterized on the base GPR.
+ *
+ * gte_lwc2_v0(base)  → lwc2 $0,  0(base)   ; C2_VXY0
+ * gte_lwc2_v0z(base) → lwc2 $1,  4(base)   ; C2_VZ0
+ * gte_lwc2_v1(base)  → lwc2 $2,  0(base)   ; C2_VXY1
+ * gte_lwc2_v1z(base) → lwc2 $3,  4(base)   ; C2_VZ1
+ * gte_lwc2_v2(base)  → lwc2 $4,  0(base)   ; C2_VXY2
+ * gte_lwc2_v2z(base) → lwc2 $5,  4(base)   ; C2_VZ2
+ *
+ * `base` is the GPR number to bake into the .word constant's `rs` field.
+ * These are pure compile-time integers; the C compiler constant-folds
+ * them into .word directives. */
+#define gte_lwc2_v0(base)   enc_cop2_lwc2(gte_in_v0_xy, (base), 0)
+#define gte_lwc2_v0z(base)  enc_cop2_lwc2(gte_in_v0_z,  (base), 4)
+#define gte_lwc2_v1(base)   enc_cop2_lwc2(gte_in_v1_xy, (base), 0)
+#define gte_lwc2_v1z(base)  enc_cop2_lwc2(gte_in_v1_z,  (base), 4)
+#define gte_lwc2_v2(base)   enc_cop2_lwc2(gte_in_v2_xy, (base), 0)
+#define gte_lwc2_v2z(base)  enc_cop2_lwc2(gte_in_v2_z,  (base), 4)
+
+/* gte_load_vN(r_ptr, base) — placeholder-punned lwc2 loaders
+ *
+ * Emits `.word` constants encoding `lwc2 $N, off(<base>)` for the chosen
+ * GTE vector register, where `<base>` is the GPR number you pass in
+ * (typically one of R_T4..R_T9 for the standard "3-pointer" pattern).
+ *
+ * The caller MUST bind `r_ptr` to that same GPR via a register variable:
+ *
+ *     register V3_S2* p_in_12 __asm__("$12") = my_ptr;
+ *     gte_load_v0(p_in_12, R_T4);   // R_T4 = 12, base is $12
+ *
+ * Then `"r"(r_ptr)` inside the asm binds to $12 (the only register
+ * `p_in_12` can live in), which is exactly the register the .word
+ * constants expect. A `"$12"` clobber would conflict with the
+ * register-variable binding ("asm specifier for variable conflicts
+ * with asm clobber list"), so we omit it. The other ABI-clobbers
+ * ($2/$8/$9/$31) stay because the GTE instructions don't touch
+ * caller-saved GPRs but the kernel does treat them as volatile.
+ *
+ * WHICH REGISTER TO PICK
+ * ----------------------
+ * Any caller-saved GPR is safe. Recommended default for an RTPT-style
+ * 3-pointer pipeline:
+ *   gte_load_v0(p0, R_T4);  // $12
+ *   gte_load_v1(p1, R_T5);  // $13
+ *   gte_load_v2(p2, R_T6);  // $14
+ * Avoid $0 (zero), $1 (at), $26/$27 (k0/k1), $28-$31 (gp/sp/fp/ra).
+ *
+ * Shape of the generated `asm volatile (...)`:
+ *   code section       : ".word %0, %1"                 (from asm_inline)
+ *   outputs section    : (empty, the 2nd colon)
+ *   inputs section     : "i"(w0), "i"(w1), "r"(r_ptr)   — r_ptr bound to <base>
+ *   clobbers section   : "$2", "$8", ..., "memory"      (from asm_clobber)
+ *   3 colons total, GCC-legal. No string-syntax mnemonics in the .word body.
+ *
+ * The `asm_clobber(...)` helper from gcc_asm.h prepends the colon that
+ * starts the clobbers section. */
+#define gte_load_v0(r_ptr, base) \
+    asm volatile(                                              \
+        asm_inline( gte_lwc2_v0(base), gte_lwc2_v0z(base) )     \
+        , "r"(r_ptr)                                           \
+        asm_clobber( reg_str(R_V0_Code), reg_str(R_T0_Code), reg_str(R_T1_Code), reg_str(R_RA_Code), "memory" )  \
+    )
+
+#define gte_load_v1(r_ptr, base) \
+    asm volatile(                                              \
+        asm_inline( gte_lwc2_v1(base), gte_lwc2_v1z(base) )     \
+        , "r"(r_ptr)                                           \
+        asm_clobber( reg_str(R_V0_Code), reg_str(R_T0_Code), reg_str(R_T1_Code), reg_str(R_RA_Code), "memory" )  \
+    )
+
+#define gte_load_v2(r_ptr, base) \
+    asm volatile(                                              \
+        asm_inline( gte_lwc2_v2(base), gte_lwc2_v2z(base) )     \
+        , "r"(r_ptr)                                           \
+        asm_clobber( reg_str(R_V0_Code), reg_str(R_T0_Code), reg_str(R_T1_Code), reg_str(R_RA_Code), "memory" )  \
+    )
+
+/* gte_load_v0v1v2(p0, p1, p2, b0, b1, b2) — the canonical prelude to gte_cmd_rtpt.
+ *
+ * Loads all three GTE input vectors (6 words) from three separate pointers,
+ * one per GTE vector register, each loaded from its own base GPR. Caller
+ * must bind each `pN` to `bN` via a register variable.
+ *
+ *   register V3_S2* p0 rgcc(R_T4) = verts[0].ptr;  // → __asm__("$12")
+ *   register V3_S2* p1 rgcc(R_T5) = verts[1].ptr;  // → __asm__("$13")
+ *   register V3_S2* p2 rgcc(R_T6) = verts[2].ptr;  // → __asm__("$14")
+ *   gte_load_v0v1v2(p0, p1, p2, R_T4, R_T5, R_T6);
+ *   gte_rtpt();
+ */
+#define gte_load_v0v1v2(p0, p1, p2, b0, b1, b2) \
+    asm volatile(                                              \
+        asm_inline( gte_lwc2_v0(b0), gte_lwc2_v0z(b0),          \
+                    gte_lwc2_v1(b1), gte_lwc2_v1z(b1),          \
+                    gte_lwc2_v2(b2), gte_lwc2_v2z(b2) )         \
+        , "r"(p0), "r"(p1), "r"(p2)                            \
+        asm_clobber( reg_str(R_V0_Code), reg_str(R_T0_Code), reg_str(R_T1_Code), reg_str(R_RA_Code), "memory" )  \
+    )
+
+#define gte_rtpt()    \
+    __asm__ volatile( \
+        "nop;"        \
+        "nop;"        \
+        "cop2 0x0280030;")
+
+#define gte_nclip()   \
+    __asm__ volatile( \
+        "nop;"        \
+        "nop;"        \
+        "cop2 0x01400006;")
+
+#define gte_stotz(r0) __asm__ volatile("swc2   $7, 0( %0 )" : : "r"(r0) : "memory")
+
+#define gte_stsxy3(r0, r1, r2)      \
+    __asm__ volatile(               \
+        "swc2   $12, 0( %0 );"      \
+        "swc2   $13, 0( %1 );"      \
+        "swc2   $14, 0( %2 )"       \
+        :                           \
+        : "r"(r0), "r"(r1), "r"(r2) \
+        : "memory")
+
+#define gte_avsz3()   \
+    __asm__ volatile( \
+        "nop;"        \
+        "nop;"        \
+        "cop2 0x0158002D;")
+
 /* asm_gte_matrix_set_rotation(r0)
  *
  * Loads the 3x3 rotation matrix at `r0` into the GTE's rotation-matrix
@@ -178,6 +486,22 @@ enum {
  *   ctc2 $13,  $3         ; → C2_RT21
  *   ctc2 $14,  $4         ; → C2_RT22
  *
+ * Same contract as gte_load_v0: caller MUST bind `r0` to $12 via a
+ * register variable (`rgcc(R_T4)`) for the `lw $12, off(...)`
+ * instructions to read from the right base. The `"r"(r0)` constraint
+ * alone doesn't force a specific GPR — it just lets GCC pick one.
+ * The .word constants here bake R_T4/R_T5/R_T6 into the `rs` field
+ * of each lw, so the lw instructions will only do the right thing
+ * if $12/$13/$14 hold the matrix base at runtime.
+ *
+ *   M3_S2* m = ...;
+ *   register M3_S2* m_in_12 rgcc(R_T4) = m;
+ *   asm_gte_matrix_set_rotation(m_in_12);
+ *
+ * We clobber $12/$13/$14 (the ones we use as scratch inside the
+ * inline asm) plus the system clobbers; we don't clobber `r0` because
+ * the `rgcc` binding already says "this variable lives in $12".
+ *
  * WARNING: Incomplete by design. The source macro only writes RT11..RT22
  * (5 of 9 rotation elements); RT23 and the entire RT3x row are left
  * untouched. Real libpsn00b SetRotMatrix writes all 9. Use only when the
@@ -185,7 +509,7 @@ enum {
  * get stale-RT2x/RT3x artifacts in RTPS/RTPT/MVMVA output.
  */
 #define asm_gte_matrix_set_rotation(r0) \
-	asm volatile(                         \
+	asm volatile( \
 		asm_inline(                         \
 			 load_imm(R_T4, r0,  0),          \
 			 load_imm(R_T5, r0,  4),          \
@@ -198,7 +522,7 @@ enum {
 			 enc_cop2_tx(cop_mt, R_T5,  3),   \
 			 enc_cop2_tx(cop_mt, R_T6,  4)    \
 		)                                   \
-		asm_clobber( clb_system, "$12", "$13", "$14") \
-		:                                             \
-		: "r"(r0)                                     \
+		asm_clobber( clb_system, reg_str(R_T4_Code), reg_str(R_T5_Code), reg_str(R_T6_Code) ) \
+		: \
+		: "r"(r0) \
 	)

code/duffle/mips.h

@@ -4,17 +4,67 @@
 # include "gcc_asm.h"
 #endif
 
+/* ============================================================================
+ *  REGISTER INTEGER IDS (preprocessor-visible)
+ * ============================================================================
+ *  Every R_* enum below has a parallel R_*_Code `#define` so that the
+ *  preprocessor can stringify the integer (e.g. for asm clobber lists and
+ *  register-variable declarations via `rgcc(R_X)`). The enum value is
+ *  bound to the `#define` so the two forms cannot drift apart.
+ *
+ *  Only registers that get stringified need a `_Code` form; the rest are
+ *  plain enum values. If you need to add a new one, follow the pattern:
+ *      #define R_T7_Code 15
+ *      R_T7 = R_T7_Code,        // in the enum
+ *
+ *  User code should always reference the enum form (`R_T4`) at arithmetic
+ *  sites and let `reg_str(R_T4_Code)` / `rgcc(R_T4)` handle the stringify
+ *  cases — never write the bare number `12`.
+ * ============================================================================ */
+#define R_0_Code    0
+#define R_AT_Code   1
+#define R_V0_Code   2
+#define R_V1_Code   3
+#define R_A0_Code   4
+#define R_A1_Code   5
+#define R_A2_Code   6
+#define R_A3_Code   7
+#define R_T0_Code   8
+#define R_T1_Code   9
+#define R_T2_Code  10
+#define R_T3_Code  11
+#define R_T4_Code  12
+#define R_T5_Code  13
+#define R_T6_Code  14
+#define R_T7_Code  15
+#define R_S0_Code  16
+#define R_S1_Code  17
+#define R_S2_Code  18
+#define R_S3_Code  19
+#define R_S4_Code  20
+#define R_S5_Code  21
+#define R_S6_Code  22
+#define R_S7_Code  23
+#define R_T8_Code  24
+#define R_T9_Code  25
+#define R_K0_Code  26
+#define R_K1_Code  27
+#define R_GP_Code  28
+#define R_SP_Code  29
+#define R_FP_Code  30
+#define R_RA_Code  31
+
 enum {
 /* --- MIPS CPU Registers --- */
 
-	R_0  = 0,  R_AT = 1,   R_V0 = 2,   R_V1 = 3,
-	R_A0 = 4,  R_A1 = 5,   R_A2 = 6,   R_A3 = 7,
-	R_T0 = 8,  R_T1 = 9,   R_T2 = 10,  R_T3 = 11,
-	R_T4 = 12, R_T5 = 13,  R_T6 = 14,  R_T7 = 15,
-	R_S0 = 16, R_S1 = 17,  R_S2 = 18,  R_S3 = 19,
-	R_S4 = 20, R_S5 = 21,  R_S6 = 22,  R_S7 = 23,
-	R_T8 = 24, R_T9 = 25,  R_K0 = 26,  R_K1 = 27,
-	R_GP = 28, R_SP = 29,  R_FP = 30,  R_RA = 31
+	R_0  = R_0_Code,  R_AT = R_AT_Code,   R_V0 = R_V0_Code,   R_V1 = R_V1_Code,
+	R_A0 = R_A0_Code,  R_A1 = R_A1_Code,   R_A2 = R_A2_Code,   R_A3 = R_A3_Code,
+	R_T0 = R_T0_Code,  R_T1 = R_T1_Code,   R_T2 = R_T2_Code,  R_T3 = R_T3_Code,
+	R_T4 = R_T4_Code,  R_T5 = R_T5_Code,   R_T6 = R_T6_Code,  R_T7 = R_T7_Code,
+	R_S0 = R_S0_Code,  R_S1 = R_S1_Code,   R_S2 = R_S2_Code,  R_S3 = R_S3_Code,
+	R_S4 = R_S4_Code,  R_S5 = R_S5_Code,   R_S6 = R_S6_Code,  R_S7 = R_S7_Code,
+	R_T8 = R_T8_Code,  R_T9 = R_T9_Code,   R_K0 = R_K0_Code,  R_K1 = R_K1_Code,
+	R_GP = R_GP_Code,  R_SP = R_SP_Code,   R_FP = R_FP_Code,  R_RA = R_RA_Code
 
 /* Semantic Aliases for MIPS Registers (O32 ABI) */
 
@@ -28,7 +78,17 @@ enum {
 	, rtmp_0        = R_T0 /* Temporary (Caller saved) */
 	, rtmp_1        = R_T1 /* Temporary (Caller saved) */
 	, rtmp_2        = R_T2 /* Temporary (Caller saved) */
-	, rsaved_0      = R_S0 /* Saved register (Callee saved) */
+	, rtmp_3        = R_T3 /* Temporary (Caller saved) */
+	, rtmp_4        = R_T4 /* Temporary (Caller saved) — common GTE base pointer */
+	, rstatic_0     = R_S0 /* Static (Callee saved, preserved across calls) */
+	, rstatic_1     = R_S1
+	, rstatic_2     = R_S2
+	, rstatic_3     = R_S3
+	, rstatic_4     = R_S4
+	, rstatic_5     = R_S5
+	, rstatic_6     = R_S6
+	, rstatic_7     = R_S7
+	, rsaved_0      = R_S0 /* Alias for rstatic_0 (alternate vocabulary) */
 	, rstack_ptr    = R_SP /* Stack Pointer */
 	, rret_addr     = R_RA /* Return Address (populated by JAL) */
 
@@ -63,6 +123,7 @@ enum {
 	, op_sh      = 0x29 /* Store Halfword */
 	, op_sw      = 0x2B /* Store Word */
 
+
 	, op_load_addr  = op_la
 	, op_load_imm   = op_li
 	, op_jump       = op_j
@@ -142,67 +203,242 @@ enum { _BitOffsets = 0
 /* MIPS I-Type Instruction Format (Immediate/Constant) */
 #define enc_i(op, rs, rt, imm)           (enc_op(op) | enc_rs(rs) | enc_rt(rt) | enc_imm(imm))
 
-/* COP0 (System) Transfer Format */
-#define enc_cop0_tx(sub, rt, rd) enc_op(op_cop0) | enc_rs(sub) | enc_rt(rt) | enc_rd(rd)
+/* COP0 (System) Transfer Format: mtc0 rt, rd or mfc0 rt, rd
+ * `sub` is the COP0 sub-opcode (cop_mf=0 or cop_mt=4), placed in rs slot.
+ * `rt` is the GPR operand (in rt slot).
+ * `rd` is the COP0 register index (in rd slot at bits 15..11). */
+#define enc_cop0_tx(sub, rt, rd) enc_i(op_cop0, (sub), (rt), ((rd) << 11))
+
+/* Semantic aliases for COP0 transfer. `sys_` is the namespace marker
+ * for system-control instructions (analogous to `gte_` for COP2).
+ *   sys_mov_to_cop0   rt, rd  →  mtc0 rt, rd
+ *   sys_mov_from_cop0 rt, rd  →  mfc0 rt, rd
+ *   sys_rfe                  →  rfe (return from exception) */
+#define sys_mov_to_cop0(rt, rd)   enc_cop0_tx(cop_mt, (rt), (rd))
+#define sys_mov_from_cop0(rt, rd) enc_cop0_tx(cop_mf, (rt), (rd))
+#define sys_rfe()                 enc_rfe()
 
 /* COP0 Return From Exception (rfe) */
 #define enc_rfe() 0x42000010
 
-#define load_imm(rs,rt,imm)   enc_i(op_lw,    rs, rt, imm)
-#define store_word(rs,rt,imm) enc_i(op_sw,    rs, rt, imm)
-#define add_ui(rs,rt,imm)     enc_i(op_addiu, rs, rt, imm)
-#define shift_ll(rs,rt,rd)    enc_r(op_special, rs, rt, rd, 0, fc_sll)
+/* --- Semantic Encoders (MIPS mnemonics) ---
+ * Argument order matches the MIPS assembly syntax:
+ *   dest-first, then source operands, then immediate last.
+ *
+ *   load_word(rt, base, off)   → lw   rt, off(base)
+ *   store_word(rt, base, off)  → sw   rt, off(base)
+ *   add_ui(rt, rs, imm)        → addiu rt, rs, imm
+ *   shift_ll(rd, rt, shamt)    → sll   rd, rt, shamt
+ *   jump_reg(rs)               → jr    rs
+ *   jump_link(rs, rd)          → jalr  rs        (link in rd, default $ra)
+ *   nop()                      → sll   $0, $0, 0
+ */
+#define load_word(rt, base, off)   enc_i(op_lw,    (base), (rt), (off))
+#define load_byte(rt, base, off)   enc_i(op_lb,    (base), (rt), (off))
+#define load_half(rt, base, off)   enc_i(op_lh,    (base), (rt), (off))
+#define load_byte_u(rt, base, off) enc_i(op_lbu,   (base), (rt), (off))
+#define load_half_u(rt, base, off) enc_i(op_lhu,   (base), (rt), (off))
+#define store_word(rt, base, off)  enc_i(op_sw,    (base), (rt), (off))
+#define add_ui(rt, rs, imm)        enc_i(op_addiu, (rs),   (rt), (imm))
+#define andi_op(rt, rs, imm)       enc_i(op_andi,  (rs),   (rt), (imm))
+#define ori_op(rt, rs, imm)        enc_i(op_ori,   (rs),   (rt), (imm))
+#define xori_op(rt, rs, imm)       enc_i(op_xori,  (rs),   (rt), (imm))
+#define lui_op(rt, imm)            enc_i(op_lui,   R_0,    (rt), (imm))
 
-#define jump_reg(rs)          enc_r(op_special, rs, R_0, R_0, 0, fc_jr)
-#define jump_nreg(rs,rt,rd)   enc_r(op_special, rs, rt, rd, 0, fc_jalr)
+/* Shift family (R-type). shift_ll/lr/ra: `sll rd, rt, shamt` */
+#define shift_ll(rd, rt, shamt)    enc_r(op_special, R_0,  (rt), (rd), (shamt), fc_sll)
+#define shift_lr(rd, rt, shamt)    enc_r(op_special, R_0,  (rt), (rd), (shamt), fc_srl)
+#define shift_ra(rd, rt, shamt)    enc_r(op_special, R_0,  (rt), (rd), (shamt), fc_sra)
 
-#define nop() shift_ll(rdiscard, rdiscard, rdiscard)
+/* jr rs — jump to address in rs. */
+#define jump_reg(rs)               enc_r(op_special, (rs), R_0, R_0, 0, fc_jr)
 
-// FI_ void emit_load_imm(U4 rs, U4 rt, U4 imm) { emit(load_imm()); }
+/* jalr rs, rd — link in rd (default $ra) and jump to address in rs.
+ * Layout: [op_special][rs:5][rt=0:5][rd:5][shamt=0:5][fc_jalr=0x09] */
+#define jump_link(rs, rd)          enc_r(op_special, (rs), R_0, (rd), 0, fc_jalr)
+
+/* jalr rs — link in $ra and jump to address in rs (most common form). */
+#define jump_nreg(rs)              jump_link((rs), R_RA)
+
+/* j target — absolute jump within the current 256MB region. */
+#define jump(off)                   enc_i(op_j,     R_0, R_0, (off))
+
+/* jal target — absolute call within the current 256MB region. */
+#define jump_nlink(off)             enc_i(op_jal,   R_0, R_0, (off))
+
+/* --- Store family (mirrors the load family) --- */
+#define store_byte(rt, base, off)  enc_i(op_sb,    (base), (rt), (off))
+#define store_half(rt, base, off)  enc_i(op_sh,    (base), (rt), (off))
+/* store_word already exists above */
+
+/* --- Arithmetic R-type (signed/unsigned split: _s traps, _u doesn't) ---
+ * add_s rd, rs, rt  → add   rd, rs, rt   (overflow traps)
+ * add_u rd, rs, rt  → addu  rd, rs, rt   (overflow silent)
+ * sub_s / sub_u  → sub / subu
+ * mult_s / mult_u → mult / multu   (writes HI/LO; result in LO)
+ * div_s / div_u   → div / divu     (LO = quot, HI = rem)
+ *
+ * NOTE: dsl.h defines `add_s`/`sub_s`/`mut_s`/`gt_s`/etc. as
+ * _Generic-based signed integer-arithmetic helpers for U1/U2/U4. Those
+ * live in a different conceptual layer (generic arithmetic on DSL
+ * types) and would collide with the instruction encoders here. The
+ * `#undef` below lets the gas-style names below win; if a file needs
+ * both, the dsl.h versions can be reached via their long forms
+ * (e.g. `def_signed_op`-style or the underlying `add_s1/s2/s4`). */
+#undef add_s
+#undef sub_s
+#define add_s(rd, rs, rt)          enc_r(op_special, (rs), (rt), (rd), 0, fc_add)
+#define add_u(rd, rs, rt)          enc_r(op_special, (rs), (rt), (rd), 0, fc_addu)
+#define sub_s(rd, rs, rt)          enc_r(op_special, (rs), (rt), (rd), 0, fc_sub)
+#define sub_u(rd, rs, rt)          enc_r(op_special, (rs), (rt), (rd), 0, fc_subu)
+#define mult_s(rd, rs, rt)         enc_r(op_special, (rs), (rt), (rd), 0, fc_mult)
+#define mult_u(rd, rs, rt)         enc_r(op_special, (rs), (rt), (rd), 0, fc_multu)
+#define div_s(rd, rs, rt)          enc_r(op_special, (rs), (rt), (rd), 0, fc_div)
+#define div_u(rd, rs, rt)          enc_r(op_special, (rs), (rt), (rd), 0, fc_divu)
+
+/* --- Arithmetic I-type (immediate) --- */
+#define add_si(rt, rs, imm)         enc_i(op_addi,  (rs), (rt), (imm))
+/* add_ui already exists above as add_ui */
+
+/* --- Set on less than (R-type and I-type) --- */
+#define slt_s(rd, rs, rt)          enc_r(op_special, (rs), (rt), (rd), 0, fc_slt)
+#define slt_u(rd, rs, rt)          enc_r(op_special, (rs), (rt), (rd), 0, fc_sltu)
+#define slt_si(rt, rs, imm)         enc_i(op_slti,  (rs), (rt), (imm))
+#define slt_ui(rt, rs, imm)         enc_i(op_sltiu, (rs), (rt), (imm))
+
+/* --- Move from/to HI/LO (mult/div results) --- */
+#define mov_from_high(rd)          enc_r(op_special, R_0, R_0, (rd), 0, fc_mfhi)
+#define mov_from_low(rd)           enc_r(op_special, R_0, R_0, (rd), 0, fc_mflo)
+#define mov_to_high(rs)             enc_r(op_special, (rs), R_0, R_0, 0, fc_mthi)
+#define mov_to_low(rs)              enc_r(op_special, (rs), R_0, R_0, 0, fc_mtlo)
+
+/* --- Atomic branches (no pseudos like bgt/bge; compose with slt_* + branch_ne) ---
+ * branch_equal  rs, rt, off → beq   rs, rt, off
+ * branch_ne      rs, rt, off → bne   rs, rt, off
+ * branch_lt_zero rs, off     → bltz  rs, off
+ * branch_gt_zero rs, off     → bgtz  rs, off
+ * branch_le_zero rs, off     → blez  rs, off
+ * branch_ge_zero rs, off     → bgez  rs, off
+ * (For `bgez`, the opcode is `op_bcond` with rt=1 to invert the bltz condition.) */
+#define branch_equal(rs, rt, off)   enc_i(op_beq,   (rs), (rt), (off))
+#define branch_ne(rs, rt, off)       enc_i(op_bne,   (rs), (rt), (off))
+#define branch_lt_zero(rs, off)      enc_i(op_bltz,  R_0, (rs), (off))
+#define branch_gt_zero(rs, off)      enc_i(op_bgtz,  R_0, (rs), (off))
+#define branch_le_zero(rs, off)      enc_i(op_blez,  R_0, (rs), (off))
+#define branch_ge_zero(rs, off)      enc_i(op_bcond, R_0, (rs), (1u << 16) | ((off) & 0xFFFF))
+
+/* --- System (kernel) instructions --- */
+#define syscall()                   enc_r(op_special, R_0, R_0, R_0, 0, fc_syscall)
+#define breakpoint()                enc_r(op_special, R_0, R_0, R_0, 0, fc_break)
+
+/* --- Shift-amount alias (matches the gas convention `\p3 = shamt`) --- */
+#define shamt(rd, rt, n)           shift_ll(rd, rt, n)
+
+/* nop — canonical sll $0, $0, 0 */
+#define nop() shift_ll(rdiscard, rdiscard, 0)
+
+/* load_imm rt, imm — true `li` semantics (assembler `li` pseudo)
+ *
+ * Dispatches at compile time on the immediate's range, picking the
+ * smallest single-instruction form when possible:
+ *
+ *   imm in   0 ..  0x7FFF  →  addi  rt, $0, imm   (1 word)
+ *   imm in 0x8000 .. 0xFFFF →  ori   rt, $0, imm   (1 word; sign-bit must be zeroed)
+ *   imm in  0x10000 ..  0xFFFFFFFF  →  lui + (ori | addi)  (2 words)
+ *
+ * Statement-level (not expression-level): the macro emits its own
+ * `asm volatile(...)` block with 1 or 2 .word constants. Callers can
+ * group multiple `load_imm` calls in a single volatile by using the
+ * lower-level encoders directly:
+ *
+ *      load_imm(R_T4, 0x12345678);          // emits 2 .words
+ *
+ * Falls back to a 2-word form if `imm` is not a compile-time constant,
+ * but that path is unusual (load_imm is most useful with literal
+ * addresses and magic numbers). */
+#define load_imm(rt, imm) do {                                              \
+    if (__builtin_constant_p(imm) && ((U4)(imm) <= 0x7FFFU)) {              \
+        /* Small positive: addi rt, $0, imm */                             \
+        asm volatile(asm_inline(add_si((rt), R_0, (imm)))                   \
+                       asm_clobber(reg_str(R_AT_Code), "memory"));           \
+    } else if (__builtin_constant_p(imm) && ((U4)(imm) <= 0xFFFFU)) {       \
+        /* 0x8000..0xFFFF: ori rt, $0, imm (zero-extends) */                \
+        asm volatile(asm_inline(ori_op((rt), R_0, (imm)))                   \
+                       asm_clobber(reg_str(R_AT_Code), "memory"));           \
+    } else {                                                                \
+        /* > 16 bits: lui + (ori | addi).                                  \
+         * If lo16 is in [0, 0x7FFF] use addi (sign-ext is harmless        \
+         * since the high half cleared bits 15..0). Otherwise ori. */       \
+        U4 _li_imm_ = (U4)(imm);                                            \
+        U4 _li_lo_  = _li_imm_ & 0xFFFFU;                                  \
+        U4 _li_hi_  = _li_imm_ >> 16;                                       \
+        if (_li_lo_ <= 0x7FFFU) {                                          \
+            asm volatile(                                                   \
+                asm_inline(lui_op((rt), _li_hi_),                          \
+                            add_si((rt), (rt), (S2)(U2)_li_lo_))          \
+                asm_clobber(reg_str(R_AT_Code), "memory"));                  \
+        } else {                                                            \
+            asm volatile(                                                   \
+                asm_inline(lui_op((rt), _li_hi_),                          \
+                            ori_op((rt), (rt), (U2)_li_lo_))              \
+                asm_clobber(reg_str(R_AT_Code), "memory"));                  \
+        }                                                                   \
+    }                                                                       \
+} while (0)
 
 // Binary Metaprogramming
 
 typedef U4 const Code;
 #define CodeBlob_(sym) tmpl(codeblob,sym) [] align_(4) =
 
-// #define def_code_blob(func_name, func_signature, ...) \
-// internal U4 const \
-// tmpl(func_name,blob) [] align(4) \
-// = { \
-// 		__VA_ARGS__ \
-// }; \
-// internal func_signature func_name = (func_signature)func_name##_blob;
-
 enum {
 	bios_flushcache = 0x44,
 	bios_table_addr = 0xA0,
 };
 
-/* Flushes the Instruction Cache */
-I_
+/* Flushes the Instruction Cache (PSX A-function 0x44 via BIOS stub at 0xA0).
+ *
+ * Sequence (per MIPS ABI; arguments in arg registers, RA pushed to stack):
+ *   1. sp -= 8;  sw $ra, 4($sp)        ; save RA
+ *   2. $a0 = bios_flushcache (arg0)
+ *   3. $t0 = bios_table_addr           ; t0 = &BIOS A-function table
+ *   4. jalr $t0, $ra                    ; call BIOS(flushcache)
+ *      nop                              ; branch delay slot
+ *   5. lw $ra, 4($sp);  jr $ra          ; restore & return
+ *   6. sp += 8
+ */
+internal
 Code CodeBlob_(mips_flush_icache) {
-	add_ui(rstack_ptr, rstack_ptr, -8),
-	store_word(rstack_ptr, rret_addr, 4),
-	add_ui(rdiscard, rret_0, bios_flushcache), add_ui(rdiscard, rtmp_0, bios_table_addr),
-	jump_nreg(rtmp_0, rdiscard, rret_addr), 
-	nop(), load_imm(rstack_ptr, rret_addr, 4), jump_reg(rret_addr),
-	add_ui(rstack_ptr, rstack_ptr, 8)
+	add_ui(rstack_ptr, rstack_ptr, -8),        /* sp -= 8         */
+	store_word(rret_addr, rstack_ptr, 4),      /* sw  $ra, 4($sp) */
+	add_ui(rret_0, rdiscard, bios_flushcache), /* addiu $a0, $0, 0x44 */
+	add_ui(rtmp_0, rdiscard, bios_table_addr), /* addiu $t0, $0, 0xA0 */
+	jump_link(rtmp_0, rret_addr),              /* jalr $t0, $ra   */
+	nop(),                                     /* BD slot         */
+	load_word(rret_addr, rstack_ptr, 4),       /* lw  $ra, 4($sp) */
+	jump_reg(rret_addr),                       /* jr   $ra        */
+	add_ui(rstack_ptr, rstack_ptr, 8)          /* sp += 8 (BD)    */
 };
 FI_ void mips_flush_icache(void) { C_(VoidFn*, codeblob_mips_flush_icache)(); }
 
-#define clb_system "$2", "$8", "$9", "$31", "memory"
+/* Standard clobber list for pure-MIPS asm volatile blocks: caller-saved
+ * GPRs that the kernel treats as volatile (v0/v1/t0/t1/ra) plus the
+ * "memory" barrier. The register ids are passed through `reg_str` so
+ * the R_*_Code `#define`s are stringified into "$N" at expansion time. */
+#define clb_system \
+	reg_str(R_V0_Code), reg_str(R_T0_Code), reg_str(R_T1_Code), reg_str(R_RA_Code), "memory"
 
-#define asm_mips_flush_icache() asm volatile( \
-	asm_inline( \
-			add_ui(rstack_ptr, rstack_ptr, -8) \
-		, store_word(rstack_ptr, rret_addr, 4) \
-		, add_ui(rdiscard, rret_0, bios_flushcache), add_ui(rdiscard, rtmp_0, bios_table_addr) \
-		, jump_nreg(rtmp_0, rdiscard, rret_addr)  \
-		, nop(), load_imm(rstack_ptr, rret_addr, 4), jump_reg(rret_addr) \
-		, add_ui(rstack_ptr, rstack_ptr, 8) \
-	) \
-	asm_clobber( clb_system ) \
-)
+#define asm_mips_flush_icache() asm volatile( asm_inline( \
+		add_ui(rstack_ptr, rstack_ptr, -8)        \
+	, store_word(rret_addr, rstack_ptr, 4)      \
+	, add_ui(rret_0, rdiscard, bios_flushcache) \
+	, add_ui(rtmp_0, rdiscard, bios_table_addr) \
+	, jump_link(rtmp_0, rret_addr)              \
+	, nop()                                     \
+	, load_word(rret_addr, rstack_ptr, 4)       \
+	, jump_reg(rret_addr)                       \
+	, add_ui(rstack_ptr, rstack_ptr, 8)         \
+) asm_clobber( clb_system ) )
 
 void test_mips_asm() {
 	asm_mips_flush_icache();

code/gte_hello/hello_gte.c

@@ -8,7 +8,10 @@
 #include "duffle/dsl.h"
 #include "duffle/memory.h"
 #include "duffle/math.h"
+#include "duffle/gcc_asm.h"
+#include "duffle/mips.h"
 #include "duffle/gp.h"
+#include "duffle/gte.h"
 #include "hello_gte.h"
 
 enum {
@@ -161,26 +164,6 @@ void gp_display_frame(DoubleBuffer* screen_buf, S2* active_buf_id, U4* ordering_
 void render(void) {
 }
 
-// #define gte_ldv0(r0)          \
-//     __asm__ volatile(         \
-//         "lwc2   $0, 0( %0 );" \
-//         "lwc2   $1, 4( %0 )"  \
-//         :                     \
-//         : "r"(r0))
-
-/**
- * @brief Loads a single V3_S2 to GTE vector register V0
- *
- * @details Loads values from an V3_S2 struct to GTE data registers C2_VXY0
- * and C2_VZ0.
- */
-// #define gte_ldv0( r0 ) __asm__ volatile ( \
-// 	"lwc2	$0, 0( %0 );"	\
-// 	"lwc2	$1, 4( %0 );"	\
-// 	:						\
-// 	: "r"( r0 )				\
-// 	: "$t0" )
-
 void update(PrimitiveArena* pa, U4* ordering_buf) 
 {
 	orderingtbl_clear_reverse(ordering_buf, OrderingTbl_Len);
@@ -243,7 +226,7 @@ void update(PrimitiveArena* pa, U4* ordering_buf)
 		// static_mem.cube.rot.x +=  6;
 		// static_mem.cube.rot.y +=  8;
 		// static_mem.cube.rot.z += 12;
-		static_mem.cube.rot.y += 0;
+		static_mem.cube.rot.y += 20;
 	}
 	// Draw Floor
 	{
@@ -258,20 +241,35 @@ void update(PrimitiveArena* pa, U4* ordering_buf)
 			tri->color   = rgb8(255, 255, 255);
 
 			V3_S2* face = & static_mem.floor.faces[face_id];
-			V3_S2* p0   = & static_mem.floor.verts[face->x];
-			V3_S2* p1   = & static_mem.floor.verts[face->y];
-			V3_S2* p2   = & static_mem.floor.verts[face->z];
+			register V3_S2* p0 rgcc(R_T4) = & static_mem.floor.verts[face->x];
+			register V3_S2* p1 rgcc(R_T5) = & static_mem.floor.verts[face->y];
+			register V3_S2* p2 rgcc(R_T6) = & static_mem.floor.verts[face->z];
 
-			nclip = rtp_avg_nclip_a3_v3s2(p0, p1, p2
-				, & tri->p0, & tri->p1, & tri->p2
-				, & p, & orderingtbl_z, & flag
-			);
-			if (nclip <= 0) {
-				continue;
-			}
+			// Three independent bases — full register discretion at the call site
+			gte_load_v0(p0, R_T4);
+			gte_load_v1(p1, R_T5);
+			gte_load_v2(p2, R_T6);
 
-			if ((orderingtbl_z > 0) && (orderingtbl_z < OrderingTbl_Len)) {
-				orderingtbl_add_primitive(ordering_buf[orderingtbl_z], tri);
+			gte_rtpt();
+			gte_nclip();
+			gte_stotz(& nclip);
+
+			// nclip = rtp_avg_nclip_a3_v3s2(p0, p1, p2
+			// 	, & tri->p0, & tri->p1, & tri->p2
+			// 	, & p, & orderingtbl_z, & flag
+			// );
+			// if (nclip <= 0) {
+			// 	continue;
+			// }
+
+			if (nclip > 0 ) {
+				gte_stsxy3(& tri->p0, & tri->p1, & tri->p2);
+				gte_avsz3();
+				gte_stotz(& orderingtbl_z);
+
+				if ((orderingtbl_z > 0) && (orderingtbl_z < OrderingTbl_Len)) {
+					orderingtbl_add_primitive(ordering_buf[orderingtbl_z], tri);
+				}
 			}
 		}
 		static_mem.floor.rot.y += 5;

code/gte_hello/hello_gte.s

@@ -1,170 +0,0 @@
-// .include "./toolchain/pcsx-redux/src/mips/common/crt0/crt0.s"
-
-.include "./asmdd/dsl.s"
-.include "./asmdd/math.s"
-.include "./asmdd/io.s"
-.include "./asmdd/gp.s"
-
-# DrawEnv_Packed { U4 tag; U4 code[15]; }
-.equ DrawEnv_Packed_tag,  0
-.equ DrawEnv_Packed_code, DrawEnv_Packed_tag + U4
-.equ DrawEnv_Packed,      64
-# DrawEnv { Rect_S2 clip; V2_S2 ofs; Rect_S2 tw; U2 tpage; U8 dtd; U8 dfe; U8 tme; U8 r0,g0,b0; DR_ENV dr_env; }
-.equ DrawEnv_clip_area,             /* 0  */ Rect_S2        * 0
-.equ DrawEnv_drawing_offset,        /* 8  */ V2_S2          * 0 + Rect_S2
-.equ DrawEnv_texture_window,        /* 12 */ Rect_S2        * 0 + A2_S2    + DrawEnv_drawing_offset
-.equ DrawEnv_texture_page,          /* 20 */ S1             * 0 + Rect_S2  + DrawEnv_texture_window
-.equ DrawEnv_flag_dither,           /* 22 */ B1             * 0 + S2       + DrawEnv_texture_page
-.equ DrawEnv_flag_draw_on_display,  /* 23 */ B1             * 0 + B1       + DrawEnv_flag_dither
-.equ DrawEnv_enable_auto_clear,     /* 24 */ B1             * 0 + B1       + DrawEnv_flag_draw_on_display
-.equ DrawEnv_initial_bg_color,      /* 25 */ RGB8           * 0 + B1       + DrawEnv_enable_auto_clear
-.equ DrawEnv_dr_env,                /* 28 */ DrawEnv_Packed * 0 + RGB8     + DrawEnv_initial_bg_color
-.equ DrawEnv,                       /* 92 */ DrawEnv_dr_env + DrawEnv_Packed
-# DisplayEnv { Rect_S16 disp; Rect_S16 screen; U8 isinter; U8 isrgb24; U8 pad[2]; }
-.equ DisplayEnv_display_area, Rect_S2  * 0
-.equ DisplayEnv_screen,       Rect_S2  * 0 + Rect_S2 + DisplayEnv_display_area
-.equ DisplayEnv_vinterlace,   B1       * 0 + Rect_S2 + DisplayEnv_screen
-.equ DisplayEnv_color24,      B1       * 0 + B1      + DisplayEnv_vinterlace
-.equ DisplayEnv_pad0,         B1       * 0 + B1      + DisplayEnv_color24
-.equ DisplayEnv_pad1,         B1       * 0 + B1      + DisplayEnv_pad0
-.equ DisplayEnv,              DisplayEnv_pad1 + B1
-# DoubleBuffer { DrawEnv draw[2]; DisplayEnv display[2]; }
-.equ DoubleBuffer_draw,      0
-.equ DoubleBuffer_draw_0,    (DrawEnv    * 0)
-.equ DoubleBuffer_draw_1,    (DrawEnv    * 1)
-.equ DoubleBuffer_display,   (DrawEnv    * 2)
-.equ DoubleBuffer_display_0, (DisplayEnv * 0) + DoubleBuffer_display
-.equ DoubleBuffer_display_1, (DisplayEnv * 1) + DoubleBuffer_display
-.equ DoubleBuffer,           (DisplayEnv * 2) + DoubleBuffer_display
-# Screen Constants
-.equ ScreenRes_X,       320
-.equ ScreenRes_Y,       240
-.equ ScreenRes_CenterX, (ScreenRes_X >> 1)
-.equ ScreenRes_CenterY, (ScreenRes_Y >> 1)
-
-.equ SMemory_screen_buf,        DoubleBuffer * 0
-.equ SMemory_active_screen_buf, S2           * 0 + DoubleBuffer
-
-.equ CF_Shadow, 16
-
-.extern ResetGraph
-.equ ResetGraph_mode, rarg_0
-
-.extern SetDispMask
-.equ SetDispMask_mask, rarg_0
-
-.extern PutDispEnv
-.extern PutDrawEnv
-.equ PutDispEnv_env, rarg_0
-.equ PutDrawEnv_env, rarg_0
-
-.extern SetDefDispEnv
-.equ SetDefDispEnv_env, rarg_0
-.equ SetDefDispEnv_x,   rarg_1
-.equ SetDefDispEnv_y,   rarg_2
-.equ SetDefDispEnv_w,   rarg_3
-.equ SetDefDispEnv_h,   CF_Shadow
-.set SetDefDispEnv_sp_size, CF_Shadow + S4
-
-.extern SetDefDrawEnv
-.equ SetDefDrawEnv_env, rarg_0
-.equ SetDefDrawEnv_x,   rarg_1
-.equ SetDefDrawEnv_y,   rarg_2
-.equ SetDefDrawEnv_w,   rarg_3
-.equ SetDefDrawEnv_h,   CF_Shadow
-.set SetDefDrawEnv_sp_size, CF_Shadow + S4
-
-.extern SetGeomOffset
-.equ SetGeomOffset_x, rarg_0
-.equ SetGeomOffset_y, rarg_1
-
-.extern SetGeomScreen
-.equ SetGeomScreen_h, rarg_0
-
-.global gp_screen_init_asm
-.type gp_screen_init_asm, @function
-gp_screen_init_asm:
-	.equiv rio_offset, rtmp_0
-	load_imm rtmp_0, IO_BASE_ADDR
-	#define gp0 gpio_port0(rio_offset)
-	#define gp1 gpio_port1(rio_offset)
-
-	def_cf_sp_size 0x18; // Should be enough for all calls within this proc, for some reason SetDefDispEnv needs the offset to be CF_Shadow..
-	stack_alloc cf_ssize
-	store_word rret_addr, 0($sp)
-
-	// Note(Ed): Cannot be used psyq manages things related to vblank and other things so the api must be called instead
-	// gcmd_push gp1, rtmp_1, gp_Reset          // ResetGraph(0)
-	// gcmd_push gp1, rtmp_1, gp_DisplayEnabled // SetDispMask(1)
-	load_imm ResetGraph_mode,  gp_Reset; jump_nlink ResetGraph
-	load_imm SetDispMask_mask, 1;        jump_nlink SetDispMask
-
-		// First buffer area
-			load_addr rtmp_0, static_mem; add_ui SetDefDispEnv_env, rtmp_0, SMemory_screen_buf + DoubleBuffer_display_0
-			move      SetDefDispEnv_x, $zero
-			move      SetDefDispEnv_y, $zero 
-			load_imm  SetDefDispEnv_w, ScreenRes_X
-			load_imm  rtmp_0, ScreenRes_Y; store_word rtmp_0, SetDefDispEnv_h($sp)
-		jump_nlink SetDefDispEnv
-			load_addr rtmp_0, static_mem; add_ui SetDefDrawEnv_env, rtmp_0, SMemory_screen_buf + DoubleBuffer_draw_0
-			move      SetDefDrawEnv_x, $zero
-			load_imm  SetDefDrawEnv_y, ScreenRes_Y
-			load_imm  SetDefDrawEnv_w, ScreenRes_X
-			load_imm  rtmp_0, ScreenRes_Y; store_word rtmp_0, SetDefDrawEnv_h($sp)
-		jump_nlink SetDefDrawEnv
-		// Second buffer area
-			load_addr rtmp_0, static_mem; add_ui SetDefDispEnv_env, rtmp_0, SMemory_screen_buf + DoubleBuffer_display_1
-			move      SetDefDispEnv_x, $zero
-			load_imm  SetDefDispEnv_y, ScreenRes_Y
-			load_imm  SetDefDispEnv_w, ScreenRes_X
-			load_imm  rtmp_0, ScreenRes_Y; store_word rtmp_0, SetDefDispEnv_h($sp)
-		jump_nlink SetDefDispEnv
-			load_addr rtmp_0, static_mem; add_ui SetDefDrawEnv_env, rtmp_0, SMemory_screen_buf + DoubleBuffer_draw_1
-			move      SetDefDrawEnv_x, $zero
-			move      SetDefDrawEnv_y, $zero 
-			load_imm  SetDefDrawEnv_w, ScreenRes_X
-			load_imm  rtmp_0, ScreenRes_Y; store_word rtmp_0, SetDefDrawEnv_h($sp)
-		jump_nlink SetDefDrawEnv
-
-	// Set the back/drawing buffer
-	load_imm   rtmp_1, true
-	load_addr  rtmp_0, static_mem; // At SMemory_screen_buf
-	store_word rtmp_1, DoubleBuffer_draw_0 + DrawEnv_enable_auto_clear(rtmp_0)
-	store_word rtmp_1, DoubleBuffer_draw_1 + DrawEnv_enable_auto_clear(rtmp_0)
-
-	// Set background clear color
-	load_imm rtmp_1, 28; load_imm rtmp_2, 22; load_imm rtmp_3, 25
-	// 63, 0, 127
-	store_byte rtmp_2, DoubleBuffer_draw_0 + DrawEnv_initial_bg_color + RGB8_r(rtmp_0)
-	store_byte rtmp_1, DoubleBuffer_draw_0 + DrawEnv_initial_bg_color + RGB8_g(rtmp_0)
-	store_byte rtmp_3, DoubleBuffer_draw_0 + DrawEnv_initial_bg_color + RGB8_b(rtmp_0)
-	// 127, 63, 0
-	store_byte rtmp_3, DoubleBuffer_draw_1 + DrawEnv_initial_bg_color + RGB8_r(rtmp_0)
-	store_byte rtmp_2, DoubleBuffer_draw_1 + DrawEnv_initial_bg_color + RGB8_g(rtmp_0)
-	store_byte rtmp_1, DoubleBuffer_draw_1 + DrawEnv_initial_bg_color + RGB8_b(rtmp_0)
-	load_addr  rtmp_0, static_mem; store_word rtmp_1, SMemory_active_screen_buf(rtmp_0)
-
-		load_addr rtmp_1, static_mem; load_half rtmp_1, SMemory_active_screen_buf(rtmp_1); // rtmp_1  = active_screen_buffer
-		load_imm  rtmp_2, DisplayEnv; mult_u rtmp_1, rtmp_2; mov_from_low rtmp_2           // rtmp_2  = DisplayEnv.type_size * active_screen_Buffer (rtmp_1)
-		add_ui    rtmp_2, rtmp_2, DoubleBuffer_display                                     // rtmp_2 += DoubleBuffer.display
-		load_addr rtmp_0, static_mem; add_u PutDispEnv_env, rtmp_0, rtmp_2                 // rarg_0  = rtmp_0 (screen_buffer) + rtmp_2 (.display[active_screen-buffer])
-	jump_nlink PutDispEnv
-		load_addr rtmp_1, static_mem; load_half rtmp_1, SMemory_active_screen_buf(rtmp_1);
-		load_imm  rtmp_2, DrawEnv; mult_u rtmp_1, rtmp_2; mov_from_low rtmp_2;
-		add_ui rtmp_2, rtmp_2, DoubleBuffer_draw
-		load_addr rtmp_0, static_mem; add_u PutDrawEnv_env, rtmp_0, rtmp_2
-	jump_nlink PutDrawEnv
-
-	// Initialize and setup the GTE geometry offsets
-	jump_nlink InitGeom
-		load_imm SetGeomOffset_x, ScreenRes_CenterX
-		load_imm SetGeomOffset_y, ScreenRes_CenterY
-	jump_nlink SetGeomOffset
-		load_imm SetGeomScreen_h, ScreenRes_CenterX
-	jump_nlink SetGeomScreen
-
-	load_word     rret_addr, 0($sp)
-	stack_release cf_ssize
-	jump_reg rret_addr;
-.Lgp_screen_init_end:
-.size gp_screen_init_asm, . - gp_screen_init_asm

scripts/build_psyq.ps1

@@ -325,10 +325,10 @@ function build-gte_hello {
 	$module_asm_crt = join-path $path_build         'crt0.o'
 	# assemble-unit $src_asm_crt $module_asm_crt $includes $assemble_args
 
-	$src_asm    = join-path $path_module 'hello_gte.s'
-	$module_asm = join-path $path_build  'hello_gte.o'
+	# $src_asm    = join-path $path_module 'hello_gte.s'
+	# $module_asm = join-path $path_build  'hello_gte.o'
 
-	assemble-unit $src_asm $module_asm $includes $assemble_args
+	# assemble-unit $src_asm $module_asm $includes $assemble_args
 
 	$src_c    = join-path $path_module 'hello_gte.c'
 	$module_c = join-path $path_build  'hello_gte_c.o'
@@ -348,7 +348,7 @@ function build-gte_hello {
 	$link_args = @()
 	$link_args += $f_debug
 	# $link_args += $f_optimize_size
-	link-modules @($module_asm_crt, $module_asm, $module_c) $elf $link_args
+	link-modules @($module_asm_crt, $module_c) $elf $link_args
 	make-binary $elf $exe
 }
 build-gte_hello