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https://github.com/Ed94/pikuma_ps1.git
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Curating duffle, preparing to update metaprogram for latest atom asm ideation. Reviewing the resolve_look_at atoms further...
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+24
-30
@@ -33,7 +33,7 @@
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* gte.h — Geometry Transformation Engine (COP2) for the PS1
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* ============================================================================
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*
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* Hand-rolled DSL for emitting GTE/MIPS instruction words as raw `.word` constants from C.
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* Hand-rolled DSL for emitting GTE/MIPS instruction words from C.
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* No GCC inline-assembly string syntax in the code body.
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*
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* STYLE NOTES
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@@ -191,27 +191,22 @@ enum {
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};
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/* --- GTE Control Register Aliases (Pitfall 1) ---
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* Three pairs of aliases map to the SAME C2 control-register slot on real silicon:
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* Three pairs of aliases map to the C2 control-register slot:
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* C2[24] = gte_cr_RBK (background R) | gte_cr_OFX (screen offset X)
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* C2[25] = gte_cr_GBK (background G) | gte_cr_OFY (screen offset Y)
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* C2[26] = gte_cr_BBK (background B) | gte_cr_H (projection plane distance H)
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* Cross-alias writes inside one atom body, or across the wave-context boundary,
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* silently clobber each other. The metaprogram's check_gte_cr_alias_writes
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* (CHECK_RULES row) warns about each pair per source. See
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* docs/gte_reference.md §"Control-register alias table" for the silicon
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* rationale and the libgte outer-product convention.
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* Cross-alias writes inside one atom body, or across the wave-context boundary, silently clobber each other.
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* The metaprogram's check_gte_cr_alias_writes (CHECK_RULES row) warns about each pair per source.
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* See psx-spx docs/gte_reference.md §"Control-register alias table" for the silicon rationale and the libgte outer-product convention.
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*/
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/* --- RT-matrix packed-slot convention (Pitfall 4) ---
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* The silicon packs two 16-bit RT elements per 32-bit C2 slot:
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* C2[2] = (RT22 << 16) | RT13 (gte_cr_RT13 writes the low half, gte_cr_RT22 writes the high half)
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* C2[4] = (RT33 << 16) | RT22 (gte_cr_RT22 writes the low half — clobbers prior RT22 value if RT13 was also written)
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* OP and MVMVA read D1/D2/D3 from these packed slots. The libgte outer-product
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* convention (see ac_apply_matrix_lv at gte.atom.c:108-122) writes C2[2] then
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* C2[4] in sequence; the SECOND write's low half is RT22, not RT13. An agent
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* who writes gte_cr_RT13 then gte_cr_RT22 to the SAME source GPR clobbers the
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* RT13 value. See docs/gte_reference.md §"RT-matrix packed-slot convention"
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* for the canonical write pattern.
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* OP and MVMVA read D1/D2/D3 from these packed slots.
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* The libgte outer-product convention (see ac_apply_matrix_lv at gte.atom.c:108-122) writes C2[2] then C2[4] in sequence;
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* the SECOND write's low half is RT22, not RT13.
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*/
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/* --- GTE Control Register Indices (for ctc2/cfc2) ---
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@@ -300,8 +295,7 @@ enum { _C2_TX_SUBS_ = 0
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// #define gte_mv_from_data_r(rt, rd) enc_gte_tx(cop_mf, (rt), (rd)) /* Move GTE Control Register (rd) to GPR (rt) */
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/* GTE Data vs Control Register Transfers
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*
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* Each macro emits a single .word constant for one of MFC2/CFC2/MTC2/CTC2.
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* Each macro emits a single instruction for one of MFC2/CFC2/MTC2/CTC2.
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*
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* `rd` is the C2 register index in the file the sub-opcode names:
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* gte_mv_from_data_r / gte_mv_to_data_r → C2 data register file
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@@ -316,14 +310,14 @@ enum { _C2_TX_SUBS_ = 0
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#define gte_mv_from_ctrl_r(rt, rd) enc_gte_tx(sub_cfc2, (rt), (rd)) /* Copy From ctrl reg */
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#define gte_mv_to_data_r(rt, rd) enc_gte_tx(sub_mtc2, (rt), (rd)) /* Move To data reg */
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#define gte_mv_to_ctrl_r(rt, rd) enc_gte_tx(sub_ctc2, (rt), (rd)) /* Copy To ctrl reg */
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#define DmaSlot_ // Annotate an instruction as filling a CPU <-> GTE DMA delay slot/s
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/* COP2 Data Load (lwc2): `lwc2 rt, off(rs)`
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* Layout: [op_lwc2:6][rs:5][rt:5][imm:16]
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* - rs: GPR base address
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* - rt: COP2 data register index (0..31)
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* - imm: signed 16-bit offset
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* NOTE: When `rs` is a runtime register, the encoding cannot be pre-baked
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* into a .word — use the string-style `gte_load_v0` macro below instead. */
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* NOTE: When `rs` is a runtime register, the encoding cannot be pre-baked into a .word — use the string-style `gte_load_v0` macro below instead. */
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#define enc_gte_lw(rt, base, off) enc_i(op_lwc2, (base), (rt), (off))
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/* Store Word */
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#define enc_gte_sw(rt, base, off) enc_i(op_swc2, (base), (rt), (off))
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@@ -332,8 +326,7 @@ enum { _C2_TX_SUBS_ = 0
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* `swc2` is redundant when we're already inside the `gte_` namespace.
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* gte_lw rt, base, off → lwc2 rt, off(base)
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* gte_sw rt, base, off → swc2 rt, off(base)
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* For the typical user-facing vector-level load (xy + z as two instructions),
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* use the higher-level `gte_load_vN` macros below. */
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* For the typical user-facing vector-level load (xy + z as two instructions), use the higher-level `gte_load_vN` macros below. */
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#define gte_lw(rt, base, off) enc_gte_lw(rt, base, off)
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#define gte_sw(rt, base, off) enc_gte_sw(rt, base, off)
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@@ -350,13 +343,13 @@ enum { _C2_TX_SUBS_ = 0
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#define gte_cmd_base (enc_op(op_cop2) | (1 << 25))
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/* Per-field encoders. Each one does (value & mask) << shift on its own. */
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#define enc_gte_sf(sf) ((sf) << gte_shift_sf )
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#define enc_gte_mx(mx) ((mx) << gte_shift_mx )
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#define enc_gte_v(v) ((v) << gte_shift_v )
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#define enc_gte_cv(cv) ((cv) << gte_shift_cv )
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#define enc_gte_lm(lm) ((lm) << gte_shift_lm )
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#define enc_gte_cmd(cmd) ((cmd) << gte_shift_cmd )
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#define enc_gte_fake_cmd(x) ((x) << gte_shift_fake_cmd)
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#define enc_gte_sf(sf) ((sf) << gte_shift_sf )
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#define enc_gte_mx(mx) ((mx) << gte_shift_mx )
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#define enc_gte_v(v) ((v) << gte_shift_v )
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#define enc_gte_cv(cv) ((cv) << gte_shift_cv )
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#define enc_gte_lm(lm) ((lm) << gte_shift_lm )
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#define enc_gte_cmd(cmd) ((cmd) << gte_shift_cmd )
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#define enc_gte_fake_cmd(x) ((x) << gte_shift_fake_cmd)
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/* Composite: all six GTE fields + the COP2/CO base. */
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#define enc_gte_cmdw(sf, mx, v, cv, lm, cmd) ( \
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@@ -408,10 +401,11 @@ enum { _C2_TX_SUBS_ = 0
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#define gte_cmdw_rtpt (gte_cmd_base | enc_gte_cmd(gte_cmd_rtpt ) | gte_cmdw_psyq_compat)
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#define gte_cmdw_nclip (gte_cmd_base | enc_gte_cmd(gte_cmd_nclip))
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#define gte_cmdw_op (gte_cmd_base | enc_gte_cmd(gte_cmd_op ))
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#define gte_cmdw_outer_product gte_cmdw_op /* "outer product" -- NOCASH/Sdk terminology */
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#define gte_cmdw_wedge gte_cmdw_op /* "wedge product" -- geometric-algebra terminology.
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* RGA(Lengyel): the GTE OP is a 3D signed-16-bit D x IR cross, not a generic RGA exterior product.
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* The wedge alias is the 3D complement interpretation of the same 3 scalars (MAC1..MAC3). */
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#define gte_cmdw_outer_product gte_cmdw_op /* "outer product" -- PSY-Q terminology */
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#define gte_cmdw_wedge gte_cmdw_op /* "wedge product" -- geometric-algebra terminology. */
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#define gte_cmdw_cross gte_cmdw_op /* "cross product" -- geometric-algebra terminology.
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* RGA(Lengyel): The GTE OP is a 3D signed-16-bit D x IR cross, not a generic RGA exterior product.
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* The wedge alias is a 3D complement interpretation of the same 3 scalars (MAC1..MAC3). */
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#define gte_cmdw_mvmva (gte_cmd_base | enc_gte_cmd(gte_cmd_mvmva))
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/* MVMVA with sf=0 (no shift, full-integer), cv=3 (no translation), v=3 (IR vector input).
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