mirror of
https://github.com/Ed94/pikuma_ps1.git
synced 2026-08-25 02:20:33 +00:00
Curating duffle, preparing to update metaprogram for latest atom asm ideation. Reviewing the resolve_look_at atoms further...
This commit is contained in:
+30
-17
@@ -84,6 +84,13 @@ WORD_COUNT(mac_load_v3s4, 3)
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, store_word(rt_z, base, offset + O_(V3_S4,z))
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WORD_COUNT(mac_store_v3s4, 3)
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/* atom_dbg_skip */
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#define mac_add_si_v3s4(rt_x, rt_y, rt_z, base, offset) \
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add_si(rt_x, base, O_(V3_S4,x)) \
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, add_si(rt_y, base, O_(V3_S4,y)) \
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, add_si(rt_z, base, O_(V3_S4,z))
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WORD_COUNT(mac_add_si_v3s4, 3)
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/* atom_dbg_skip */
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#define mac_sub_v3s4(rds_x, rds_y, rds_z, rt_x, rt_y, rt_z) \
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sub_s(rds_x, rds_x, rt_x) \
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@@ -105,6 +112,24 @@ WORD_COUNT(mac_store_rects2, 4)
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, or_i_self( dst, u4_lo(imm))
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WORD_COUNT(mac_load_word_imm, 2)
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#define mac_shift_aright_v3_self(dt_x, dt_y, dt_z, shift_amount) \
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shift_aright(dt_x, dt_x, shift_amount) \
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, shift_aright(dt_y, dt_y, shift_amount) \
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, shift_aright(dt_z, dt_z, shift_amount)
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WORD_COUNT(mac_shift_aright_v3_self, 3)
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#define mac_shift_aright_var_v3(rd_v0, rd_v1, rd_v2, rs_v0, rs_v1, rs_v2, r_shift) \
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shift_aright_var(rd_v0, rs_v0, r_shift) \
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, shift_aright_var(rd_v1, rs_v1, r_shift) \
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, shift_aright_var(rd_v2, rs_v2, r_shift)
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WORD_COUNT(mac_shift_aright_var_v3, 3)
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#define mac_shift_aright_var_v3_self(rds_v0, rds_v1, rds_v2, r_shift) \
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shift_aright_var(rds_v0, rds_v0, r_shift) \
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, shift_aright_var(rds_v1, rds_v1, r_shift) \
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, shift_aright_var(rds_v2, rds_v2, r_shift)
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WORD_COUNT(mac_shift_aright_var_v3_self, 3)
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/* atom_dbg_skip */
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#define mac_load_tri_indices(r_face_cusor, r_i0, r_i1, r_i2) \
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load_half_u(r_i0, r_face_cusor, 0 * S_(S2)) \
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@@ -125,19 +150,19 @@ WORD_COUNT(mac_gte_store_f3, 3)
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, add_u_self(R_AT, r_vert_base) \
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, load_word(R_V0, R_AT, O_(V3_S2,x)) \
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, load_word(R_V1, R_AT, O_(V3_S2,z)) \
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, gte_mv_to_data_r(R_V0, C2_VXY0) \
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, LdSlot_ gte_mv_to_data_r(R_V0, C2_VXY0) \
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, gte_mv_to_data_r(R_V1, C2_VZ0) \
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, shift_lleft(R_AT, r_v1, v3s2_byteoff) \
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, add_u_self(R_AT, r_vert_base) \
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, load_word(R_V0, R_AT, O_(V3_S2,x)) \
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, load_word(R_V1, R_AT, O_(V3_S2,z)) \
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, gte_mv_to_data_r(R_V0, C2_VXY1) \
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, LdSlot_ gte_mv_to_data_r(R_V0, C2_VXY1) \
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, gte_mv_to_data_r(R_V1, C2_VZ1) \
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, shift_lleft(R_AT, r_v2, v3s2_byteoff) \
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, add_u_self(R_AT, r_vert_base) \
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, load_word(R_V0, R_AT, O_(V3_S2,x)) \
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, load_word(R_V1, R_AT, O_(V3_S2,z)) \
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, gte_mv_to_data_r(R_V0, C2_VXY2) \
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, LdSlot_ gte_mv_to_data_r(R_V0, C2_VXY2) \
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, gte_mv_to_data_r(R_V1, C2_VZ2)
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WORD_COUNT(mac_gte_load_tri_verts, 18)
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@@ -162,11 +187,11 @@ WORD_COUNT(mac_gte_store_g4_p3, 1)
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WORD_COUNT(mac_gte_sqr_v3, 8)
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/* atom_dbg_skip */
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#define mac_gte_sqr_v3s4(r_sx, r_sy, r_sz, nop_slot) \
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#define mac_gte_sqr_v3s4(r_sx, r_sy, r_sz, delay_slot) \
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gte_mv_to_data_r(r_sx, C2_IR1) \
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, gte_mv_to_data_r(r_sy, C2_IR2) \
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, gte_mv_to_data_r(r_sz, C2_IR3) \
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, nop_slot \
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, delay_slot \
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, gte_cmdw_sqr
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WORD_COUNT(mac_gte_sqr_v3s4, 5)
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@@ -204,18 +229,6 @@ WORD_COUNT(mac_trans_mt3s3s4, 6)
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, shift_aright(r_mag_sq, r_mag_sq, 1)
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WORD_COUNT(mac_lzcr_round_even_half_shift, 5)
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#define mac_shift_aright_var_v3(rd_v0, rd_v1, rd_v2, rs_v0, rs_v1, rs_v2, r_shift) \
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shift_aright_var(rd_v0, rs_v0, r_shift) \
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, shift_aright_var(rd_v1, rs_v1, r_shift) \
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, shift_aright_var(rd_v2, rs_v2, r_shift)
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WORD_COUNT(mac_shift_aright_var_v3, 3)
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#define mac_shift_aright_var_v3_self(rds_v0, rds_v1, rds_v2, r_shift) \
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shift_aright_var(rds_v0, rds_v0, r_shift) \
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, shift_aright_var(rds_v1, rds_v1, r_shift) \
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, shift_aright_var(rds_v2, rds_v2, r_shift)
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WORD_COUNT(mac_shift_aright_var_v3_self, 3)
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#define mac_gte_general_purpose_interopolation(to_ir0, to_ir1, to_ir2, to_ir3, fr_mac1, fr_mac2, fr_mac3, nop_slot1, nop_slot2) \
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gte_mv_to_data_r(to_ir0, C2_IR0) \
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, gte_mv_to_data_r(to_ir1, C2_IR1) /* IR1 = src.x (preserved in r_tmp — r_mac2_scratch was clobbered to MAC2 in stage 1.5) */ \
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@@ -25,6 +25,14 @@
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#pragma region duffle
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// --- atom: example_atom (10 words) ---
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#define _atom_offset_example_atom_proc_skip 2
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enum {
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atom_offset_example_atom_proc_skip = _atom_offset_example_atom_proc_skip,
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};
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// --- atom: normalize_v3s4 (47 words) ---
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#define _atom_offset_aligned_done_srav_path 3
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@@ -44,7 +44,8 @@ atom_dbg_skip MipsAtomComp_Proc_(ab, {
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})
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/* Words: 11; Correctly inserts a primitive into the Ordering Table linked list. */
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I_ Slice_MipsCode ac_insert_ot_tag(AtomBuilder_R ab, U4 r_ot_base, U4 r_prim_cursor, U4 poly_size) MipsAtomComp_Proc_(ab, {
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// TODO(Ed): Expose R_T1 as a r_t0, r_V0 as r_t2
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I_ Slice_MipsCode ac_insert_ot_tag(AtomBuilder_R ab, Reg r_ot_base, Reg r_prim_cursor, U2 poly_size) MipsAtomComp_Proc_(ab, {
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shift_lleft( R_T1, R_T1, S_(U4)/2), // T1 = otz * S_(U4) (otz arg is implicit R_T1)
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add_u_self( R_T1, r_ot_base), // T1 = & OrderingTable[OTZ]
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load_word( R_AT, R_T1, O_(PolyTag,code)), // AT = old_ot_head
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+3
-6
@@ -418,14 +418,11 @@ typedef Struct_(PolyTag) {
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};
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};
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/* DSL cast convention: every cast uses `C_()`, every pointer qualifier is `R_` (restrict) or `V_` (volatile).
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* No raw C-style casts. RHS values are assumed to be `U4` — caller passes a `U4` directly. */
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#define set_len(tag,v) (C_(PolyTag_R,tag)->len = u4_(v))
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#define set_addr(tag,v) (C_(PolyTag_R,tag)->addr = u4_(v))
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/* `set_code` is no longer in the new PolyTag design — the code byte lives in the primitive body
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/* `set_code` is no longer in the new PolyTag design
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* (e.g. `((Poly_F3*)(p))->code`), not in the tag.
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* Use the typed primitive structs (Poly_F3, Poly_G4, etc.) and the `set_poly_*` setters,
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* which set both the tag's length and the code. */
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* Use the typed primitive structs (Poly_F3, Poly_G4, etc.) and the `set_poly_*` setters, which set both the tag's length and the code. */
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#define get_len(tag) C_(U4,C_(PolyTag_R,tag)->len)
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#define get_addr(tag) C_(U4,C_(PolyTag_R,tag)->addr)
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@@ -572,7 +569,7 @@ enum {
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/* Default TPage value libpsyx's SetDefDrawEnv writes (matches the `li v1, 10; sh v1, 20(v0)` sequence at C11_only.elf:0x8001273C). */
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gp0_tpage_default = 10,
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/* TPage semi-transparency mode payload values (NOT bit positions). */
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/* TPage semi-transparency mode payload values. */
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gp0_tpage_semi_trans_none = 0x0,
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gp0_tpage_semi_trans_alpha = 0x1,
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gp0_tpage_semi_trans_add = 0x2,
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+12
-34
@@ -28,9 +28,9 @@ FI_ Slice_MipsCode ac_gte_store_f3(AtomBuilder_R ab, U4 r_primitive_cursor) atom
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/* Words: 18; Translates indices to vertex addresses and pushes them to GTE */
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I_ Slice_MipsCode ac_gte_load_tri_verts(AtomBuilder_R ab, U4 r_vert_base, U4 r_v0, U4 r_v1, U4 r_v2) atom_dbg_skip MipsAtomComp_Proc_(ab, {
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shift_lleft(R_AT, r_v0, v3s2_byteoff), add_u_self(R_AT, r_vert_base), load_word(R_V0, R_AT, O_(V3_S2,x)), load_word(R_V1, R_AT, O_(V3_S2,z)), gte_mv_to_data_r(R_V0, C2_VXY0), gte_mv_to_data_r(R_V1, C2_VZ0),
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shift_lleft(R_AT, r_v1, v3s2_byteoff), add_u_self(R_AT, r_vert_base), load_word(R_V0, R_AT, O_(V3_S2,x)), load_word(R_V1, R_AT, O_(V3_S2,z)), gte_mv_to_data_r(R_V0, C2_VXY1), gte_mv_to_data_r(R_V1, C2_VZ1),
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shift_lleft(R_AT, r_v2, v3s2_byteoff), add_u_self(R_AT, r_vert_base), load_word(R_V0, R_AT, O_(V3_S2,x)), load_word(R_V1, R_AT, O_(V3_S2,z)), gte_mv_to_data_r(R_V0, C2_VXY2), gte_mv_to_data_r(R_V1, C2_VZ2),
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shift_lleft(R_AT, r_v0, v3s2_byteoff), add_u_self(R_AT, r_vert_base), load_word(R_V0, R_AT, O_(V3_S2,x)), load_word(R_V1, R_AT, O_(V3_S2,z)), LdSlot_ gte_mv_to_data_r(R_V0, C2_VXY0), gte_mv_to_data_r(R_V1, C2_VZ0),
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shift_lleft(R_AT, r_v1, v3s2_byteoff), add_u_self(R_AT, r_vert_base), load_word(R_V0, R_AT, O_(V3_S2,x)), load_word(R_V1, R_AT, O_(V3_S2,z)), LdSlot_ gte_mv_to_data_r(R_V0, C2_VXY1), gte_mv_to_data_r(R_V1, C2_VZ1),
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shift_lleft(R_AT, r_v2, v3s2_byteoff), add_u_self(R_AT, r_vert_base), load_word(R_V0, R_AT, O_(V3_S2,x)), load_word(R_V1, R_AT, O_(V3_S2,z)), LdSlot_ gte_mv_to_data_r(R_V0, C2_VXY2), gte_mv_to_data_r(R_V1, C2_VZ2),
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})
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/* Words: 3; Stores the 3 transformed (V2_S2 screen) vertices of the
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@@ -38,7 +38,7 @@ I_ Slice_MipsCode ac_gte_load_tri_verts(AtomBuilder_R ab, U4 r_vert_base, U4 r_v
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* PIPELINE: post-RTPT, pre-RTPS (SXY0=v0.screen, SXY1=v1.screen, SXY2=v2.screen).
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* MUST be called BEFORE V3-RTPS, otherwise SXY0/1/2 get overwritten with v3
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* (RTPS writes only to SXY2, but to keep the three registers aligned with v0/v1/v2 you must store before RTPS). */
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FI_ Slice_MipsCode ac_gte_store_g4_p012(AtomBuilder_R ab, U4 r_primitive_cursor) atom_dbg_skip MipsAtomComp_Proc_(ab, {
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FI_ Slice_MipsCode ac_gte_store_g4_p012(AtomBuilder_R ab, Reg r_primitive_cursor) atom_dbg_skip MipsAtomComp_Proc_(ab, {
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gte_sw(C2_SXY0, r_primitive_cursor, O_(Poly_G4,p0)),
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gte_sw(C2_SXY1, r_primitive_cursor, O_(Poly_G4,p1)),
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gte_sw(C2_SXY2, r_primitive_cursor, O_(Poly_G4,p2)),
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@@ -65,12 +65,12 @@ FI_ Slice_MipsCode ac_gte_sqr_v3(AtomBuilder_R ab, U4 r_sx, U4 r_sy, U4 r_sz, U4
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* The SQR command always squares IR1/IR2/IR3 — those C2 registers are fixed.
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* The GPRs holding the source vector are caller-determined.
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* Words: 5 (3 mtc2 + 1 nop hazard + 1 cmd). */
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FI_ Slice_MipsCode ac_gte_sqr_v3s4(AtomBuilder_R ab, Reg r_sx, Reg r_sy, Reg r_sz, MipsCode nop_slot)
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FI_ Slice_MipsCode ac_gte_sqr_v3s4(AtomBuilder_R ab, Reg r_sx, Reg r_sy, Reg r_sz, MipsCode delay_slot)
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atom_dbg_skip MipsAtomComp_Proc_(ab, {
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gte_mv_to_data_r(r_sx, C2_IR1),
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gte_mv_to_data_r(r_sy, C2_IR2),
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gte_mv_to_data_r(r_sz, C2_IR3),
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nop_slot, gte_cmdw_sqr,
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delay_slot, gte_cmdw_sqr,
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})
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/* ─── STAGE 4 of normalize: mtc2 IR0..3 + GPF + mfc2 MAC + srav finalize ───
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@@ -132,8 +132,7 @@ FI_ Slice_MipsCode ac_trans_mt3s3s4(AtomBuilder_R ab
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FI_ Slice_MipsCode ac_lzcr_round_even_half_shift(AtomBuilder_R ab,
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U4 r_shift,
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U4 r_mag_sq,
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U4 r_mag_sq_copy
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)
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U4 r_mag_sq_copy)
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atom_dbg_skip MipsAtomComp_Proc_(ab, {
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and_i(r_shift, r_shift, gte_lzcr_even_mask),
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or_u(r_mag_sq_copy, r_mag_sq, 0),
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@@ -142,25 +141,6 @@ atom_dbg_skip MipsAtomComp_Proc_(ab, {
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shift_aright(r_mag_sq, r_mag_sq, 1),
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})
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FI_ Slice_MipsCode ac_shift_aright_var_v3(AtomBuilder_R ab
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, Reg rd_v0, Reg rd_v1, Reg rd_v2
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, Reg rs_v0, Reg rs_v1, Reg rs_v2
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, Reg r_shift)
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MipsAtomComp_Proc_(ab, {
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shift_aright_var(rd_v0, rs_v0, r_shift),
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shift_aright_var(rd_v1, rs_v1, r_shift),
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shift_aright_var(rd_v2, rs_v2, r_shift),
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})
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FI_ Slice_MipsCode ac_shift_aright_var_v3_self(AtomBuilder_R ab
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, Reg rds_v0, Reg rds_v1, Reg rds_v2
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, Reg r_shift)
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MipsAtomComp_Proc_(ab, {
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shift_aright_var(rds_v0, rds_v0, r_shift),
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shift_aright_var(rds_v1, rds_v1, r_shift),
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shift_aright_var(rds_v2, rds_v2, r_shift),
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})
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FI_ Slice_MipsCode ac_gte_general_purpose_interopolation(AtomBuilder_R ab
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, Reg to_ir0, Reg to_ir1, Reg to_ir2, Reg to_ir3
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, Reg fr_mac1, Reg fr_mac2, Reg fr_mac3
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@@ -178,9 +158,8 @@ MipsAtomComp_Proc_(ab, {
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gte_mv_from_data_r(fr_mac3, C2_MAC3),
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})
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FI_ Slice_MipsCode gte_mv_from_data_r_mac123(AtomBuilder_R ab
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, Reg fr_mac1, Reg fr_mac2, Reg fr_mac3
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)
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||||
FI_ Slice_MipsCode ac_gte_mv_from_data_r_mac123(AtomBuilder_R ab
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, Reg fr_mac1, Reg fr_mac2, Reg fr_mac3)
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MipsAtomComp_Proc_(ab, {
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gte_mv_from_data_r(fr_mac1, C2_MAC1),
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gte_mv_from_data_r(fr_mac2, C2_MAC2),
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@@ -257,9 +236,8 @@ internal S2 const gte_normalize_sqr_tbl[192] align_(2) = {
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0x0820, 0x081c, 0x0818, 0x0814, 0x0810, 0x080c, 0x0808, 0x0804,
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||||
};
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||||
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||||
#define RegUse_(proc_name) (tmpl(RegUse,proc_name))
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typedef Struct_(RegUse_normalize_v3s4_proc) {
|
||||
Reg scratch; // Scratch base carrier.
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Reg const scratch; // Scratch base carrier.
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Reg src_ptr;
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Reg dst_ptr;
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||||
Reg recip_est; // |v|² sum + shift-input + sqrtbl[index]
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@@ -267,7 +245,7 @@ typedef Struct_(RegUse_normalize_v3s4_proc) {
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Reg src_x;
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union { Reg mac1_scratch; } t3;
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union { Reg mac2_scratch; } t4;
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||||
union { Reg shift_count, btarget, lookup_addr, src_z; } t5;
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union { Reg btarget, shift_count, lookup_addr, src_z; } t5;
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||||
};
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||||
/* ─── Full normalize (all 4 stages inline) ───
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* Generic 4-stage GTE normalize (SQR → sum+LZCR → align+sqrtbl → GPF+srav).
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@@ -306,7 +284,7 @@ MipsAtom_Proc_(aa, {
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||||
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||||
/* Load src.x/y/z from r_src_ptr (caller-determined address) into r_tmp/r_recip_est/r_branch_tmp.
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||||
* r.rt1_src_x holds src.x throughout stages 1-2 — r_mac2_scratch is clobbered to MAC2 in stage 1.5 (line below). */
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||||
mac_load_v3s4(r.src_x, r.recip_est, r.t5.lookup_addr, r.src_ptr, 0),
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mac_load_v3s4(r.src_x, r.recip_est, r.t5.src_z, r.src_ptr, 0),
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||||
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||||
/* Stage 1: mtc2 src → IR1/2/3, SQR fires. */
|
||||
LdSlot_ mac_gte_sqr_v3s4(r.src_x, r.recip_est, r.t5.src_z, LdSlot_ nop),
|
||||
|
||||
+24
-30
@@ -33,7 +33,7 @@
|
||||
* gte.h — Geometry Transformation Engine (COP2) for the PS1
|
||||
* ============================================================================
|
||||
*
|
||||
* Hand-rolled DSL for emitting GTE/MIPS instruction words as raw `.word` constants from C.
|
||||
* Hand-rolled DSL for emitting GTE/MIPS instruction words from C.
|
||||
* No GCC inline-assembly string syntax in the code body.
|
||||
*
|
||||
* STYLE NOTES
|
||||
@@ -191,27 +191,22 @@ enum {
|
||||
};
|
||||
|
||||
/* --- GTE Control Register Aliases (Pitfall 1) ---
|
||||
* Three pairs of aliases map to the SAME C2 control-register slot on real silicon:
|
||||
* Three pairs of aliases map to the C2 control-register slot:
|
||||
* C2[24] = gte_cr_RBK (background R) | gte_cr_OFX (screen offset X)
|
||||
* C2[25] = gte_cr_GBK (background G) | gte_cr_OFY (screen offset Y)
|
||||
* C2[26] = gte_cr_BBK (background B) | gte_cr_H (projection plane distance H)
|
||||
* Cross-alias writes inside one atom body, or across the wave-context boundary,
|
||||
* silently clobber each other. The metaprogram's check_gte_cr_alias_writes
|
||||
* (CHECK_RULES row) warns about each pair per source. See
|
||||
* docs/gte_reference.md §"Control-register alias table" for the silicon
|
||||
* rationale and the libgte outer-product convention.
|
||||
* Cross-alias writes inside one atom body, or across the wave-context boundary, silently clobber each other.
|
||||
* The metaprogram's check_gte_cr_alias_writes (CHECK_RULES row) warns about each pair per source.
|
||||
* See psx-spx docs/gte_reference.md §"Control-register alias table" for the silicon rationale and the libgte outer-product convention.
|
||||
*/
|
||||
|
||||
/* --- RT-matrix packed-slot convention (Pitfall 4) ---
|
||||
* The silicon packs two 16-bit RT elements per 32-bit C2 slot:
|
||||
* C2[2] = (RT22 << 16) | RT13 (gte_cr_RT13 writes the low half, gte_cr_RT22 writes the high half)
|
||||
* C2[4] = (RT33 << 16) | RT22 (gte_cr_RT22 writes the low half — clobbers prior RT22 value if RT13 was also written)
|
||||
* OP and MVMVA read D1/D2/D3 from these packed slots. The libgte outer-product
|
||||
* convention (see ac_apply_matrix_lv at gte.atom.c:108-122) writes C2[2] then
|
||||
* C2[4] in sequence; the SECOND write's low half is RT22, not RT13. An agent
|
||||
* who writes gte_cr_RT13 then gte_cr_RT22 to the SAME source GPR clobbers the
|
||||
* RT13 value. See docs/gte_reference.md §"RT-matrix packed-slot convention"
|
||||
* for the canonical write pattern.
|
||||
* OP and MVMVA read D1/D2/D3 from these packed slots.
|
||||
* The libgte outer-product convention (see ac_apply_matrix_lv at gte.atom.c:108-122) writes C2[2] then C2[4] in sequence;
|
||||
* the SECOND write's low half is RT22, not RT13.
|
||||
*/
|
||||
|
||||
/* --- GTE Control Register Indices (for ctc2/cfc2) ---
|
||||
@@ -300,8 +295,7 @@ enum { _C2_TX_SUBS_ = 0
|
||||
// #define gte_mv_from_data_r(rt, rd) enc_gte_tx(cop_mf, (rt), (rd)) /* Move GTE Control Register (rd) to GPR (rt) */
|
||||
|
||||
/* GTE Data vs Control Register Transfers
|
||||
*
|
||||
* Each macro emits a single .word constant for one of MFC2/CFC2/MTC2/CTC2.
|
||||
* Each macro emits a single instruction for one of MFC2/CFC2/MTC2/CTC2.
|
||||
*
|
||||
* `rd` is the C2 register index in the file the sub-opcode names:
|
||||
* gte_mv_from_data_r / gte_mv_to_data_r → C2 data register file
|
||||
@@ -316,14 +310,14 @@ enum { _C2_TX_SUBS_ = 0
|
||||
#define gte_mv_from_ctrl_r(rt, rd) enc_gte_tx(sub_cfc2, (rt), (rd)) /* Copy From ctrl reg */
|
||||
#define gte_mv_to_data_r(rt, rd) enc_gte_tx(sub_mtc2, (rt), (rd)) /* Move To data reg */
|
||||
#define gte_mv_to_ctrl_r(rt, rd) enc_gte_tx(sub_ctc2, (rt), (rd)) /* Copy To ctrl reg */
|
||||
#define DmaSlot_ // Annotate an instruction as filling a CPU <-> GTE DMA delay slot/s
|
||||
|
||||
/* COP2 Data Load (lwc2): `lwc2 rt, off(rs)`
|
||||
* Layout: [op_lwc2:6][rs:5][rt:5][imm:16]
|
||||
* - rs: GPR base address
|
||||
* - rt: COP2 data register index (0..31)
|
||||
* - imm: signed 16-bit offset
|
||||
* NOTE: When `rs` is a runtime register, the encoding cannot be pre-baked
|
||||
* into a .word — use the string-style `gte_load_v0` macro below instead. */
|
||||
* NOTE: When `rs` is a runtime register, the encoding cannot be pre-baked into a .word — use the string-style `gte_load_v0` macro below instead. */
|
||||
#define enc_gte_lw(rt, base, off) enc_i(op_lwc2, (base), (rt), (off))
|
||||
/* Store Word */
|
||||
#define enc_gte_sw(rt, base, off) enc_i(op_swc2, (base), (rt), (off))
|
||||
@@ -332,8 +326,7 @@ enum { _C2_TX_SUBS_ = 0
|
||||
* `swc2` is redundant when we're already inside the `gte_` namespace.
|
||||
* gte_lw rt, base, off → lwc2 rt, off(base)
|
||||
* gte_sw rt, base, off → swc2 rt, off(base)
|
||||
* For the typical user-facing vector-level load (xy + z as two instructions),
|
||||
* use the higher-level `gte_load_vN` macros below. */
|
||||
* For the typical user-facing vector-level load (xy + z as two instructions), use the higher-level `gte_load_vN` macros below. */
|
||||
#define gte_lw(rt, base, off) enc_gte_lw(rt, base, off)
|
||||
#define gte_sw(rt, base, off) enc_gte_sw(rt, base, off)
|
||||
|
||||
@@ -350,13 +343,13 @@ enum { _C2_TX_SUBS_ = 0
|
||||
#define gte_cmd_base (enc_op(op_cop2) | (1 << 25))
|
||||
|
||||
/* Per-field encoders. Each one does (value & mask) << shift on its own. */
|
||||
#define enc_gte_sf(sf) ((sf) << gte_shift_sf )
|
||||
#define enc_gte_mx(mx) ((mx) << gte_shift_mx )
|
||||
#define enc_gte_v(v) ((v) << gte_shift_v )
|
||||
#define enc_gte_cv(cv) ((cv) << gte_shift_cv )
|
||||
#define enc_gte_lm(lm) ((lm) << gte_shift_lm )
|
||||
#define enc_gte_cmd(cmd) ((cmd) << gte_shift_cmd )
|
||||
#define enc_gte_fake_cmd(x) ((x) << gte_shift_fake_cmd)
|
||||
#define enc_gte_sf(sf) ((sf) << gte_shift_sf )
|
||||
#define enc_gte_mx(mx) ((mx) << gte_shift_mx )
|
||||
#define enc_gte_v(v) ((v) << gte_shift_v )
|
||||
#define enc_gte_cv(cv) ((cv) << gte_shift_cv )
|
||||
#define enc_gte_lm(lm) ((lm) << gte_shift_lm )
|
||||
#define enc_gte_cmd(cmd) ((cmd) << gte_shift_cmd )
|
||||
#define enc_gte_fake_cmd(x) ((x) << gte_shift_fake_cmd)
|
||||
|
||||
/* Composite: all six GTE fields + the COP2/CO base. */
|
||||
#define enc_gte_cmdw(sf, mx, v, cv, lm, cmd) ( \
|
||||
@@ -408,10 +401,11 @@ enum { _C2_TX_SUBS_ = 0
|
||||
#define gte_cmdw_rtpt (gte_cmd_base | enc_gte_cmd(gte_cmd_rtpt ) | gte_cmdw_psyq_compat)
|
||||
#define gte_cmdw_nclip (gte_cmd_base | enc_gte_cmd(gte_cmd_nclip))
|
||||
#define gte_cmdw_op (gte_cmd_base | enc_gte_cmd(gte_cmd_op ))
|
||||
#define gte_cmdw_outer_product gte_cmdw_op /* "outer product" -- NOCASH/Sdk terminology */
|
||||
#define gte_cmdw_wedge gte_cmdw_op /* "wedge product" -- geometric-algebra terminology.
|
||||
* RGA(Lengyel): the GTE OP is a 3D signed-16-bit D x IR cross, not a generic RGA exterior product.
|
||||
* The wedge alias is the 3D complement interpretation of the same 3 scalars (MAC1..MAC3). */
|
||||
#define gte_cmdw_outer_product gte_cmdw_op /* "outer product" -- PSY-Q terminology */
|
||||
#define gte_cmdw_wedge gte_cmdw_op /* "wedge product" -- geometric-algebra terminology. */
|
||||
#define gte_cmdw_cross gte_cmdw_op /* "cross product" -- geometric-algebra terminology.
|
||||
* RGA(Lengyel): The GTE OP is a 3D signed-16-bit D x IR cross, not a generic RGA exterior product.
|
||||
* The wedge alias is a 3D complement interpretation of the same 3 scalars (MAC1..MAC3). */
|
||||
#define gte_cmdw_mvmva (gte_cmd_base | enc_gte_cmd(gte_cmd_mvmva))
|
||||
|
||||
/* MVMVA with sf=0 (no shift, full-integer), cv=3 (no translation), v=3 (IR vector input).
|
||||
|
||||
@@ -105,7 +105,7 @@ typedef U2 Reg; // Register parameter used with atom or atom component procedure
|
||||
typedef U4 const MipsCode; // Underlying type to mips asm words.
|
||||
typedef Slice_(MipsCode);
|
||||
|
||||
typedef U4 const MipsAtom;
|
||||
typedef U4 const MipsAtom; // Underlying type to a mips atom defnition
|
||||
typedef Slice_(MipsAtom);
|
||||
// Sometimes a user will define a bundle of atoms that represent a procedure of work as:
|
||||
// MipsAtom* <identifier>[...];
|
||||
@@ -242,6 +242,7 @@ atom_dbg_skip MipsAtomComp_(ac_yield_tail) {
|
||||
add_ui_self(R_TapePtr, S_(MipsCode)),
|
||||
jump_reg( R_AtomJmp), nop,
|
||||
};
|
||||
|
||||
#pragma endregion Macro Atom Components
|
||||
|
||||
#pragma region Atom Builder
|
||||
@@ -378,6 +379,27 @@ FI_ void regfile_reset_mask(RegFile_R rf, U4 mask) {
|
||||
#pragma endregion RegFileArena (Register File Allocator)
|
||||
|
||||
#pragma region Mips Atom Procs
|
||||
/* RegUse structs are a convention to organize register allocations for a mips atom procedure.
|
||||
Unlike the usual enum-based declarations, they provide a namespaced scope
|
||||
and have view types via union declarations.
|
||||
*/
|
||||
#define RegUse_(proc_name) (tmpl(RegUse,proc_name))
|
||||
|
||||
typedef Struct_(RegUse_example_atom_proc) {
|
||||
Reg const ro_register; // Scratch base carrier.
|
||||
Reg usual_modifiable;
|
||||
union { Reg view_1, view_2, view_3; } t1;
|
||||
};
|
||||
internal MipsAtom* example_atom_proc(AtomArena_R aa, U2 offset, RegUse_example_atom_proc r)
|
||||
MipsAtom_Proc_(aa, {
|
||||
add_si(r.usual_modifiable, r.ro_register, offset),
|
||||
or_u(r.t1.view_1, r.ro_register, 0),
|
||||
branch_lt_zero(r.t1.view_1, atom_offset(example_atom_proc, skip)), BdSlot_ nop,
|
||||
li_s(r.t1.view_2, 100),
|
||||
atom_label(skip)
|
||||
add_si(r.t1.view_3, r.usual_modifiable, 10),
|
||||
mac_yield(),
|
||||
})
|
||||
|
||||
#pragma endregion Mips Atom Procs
|
||||
|
||||
|
||||
@@ -39,6 +39,13 @@ FI_ Slice_MipsCode ac_store_v3s4(AtomBuilder_R ab, U4 rt_x, U4 rt_y, U4 rt_z, U4
|
||||
#define ac_store_p3s4 ac_store_v3s4
|
||||
#define mac_store_p3s4 mac_store_v3s4
|
||||
|
||||
FI_ Slice_MipsCode ac_add_si_v3s4(AtomBuilder_R ab, Reg rt_x, Reg rt_y, Reg rt_z, Reg base, U2 offset)
|
||||
atom_dbg_skip MipsAtomComp_Proc_(ab, {
|
||||
add_si(rt_x, base, O_(V3_S4,x)),
|
||||
add_si(rt_y, base, O_(V3_S4,y)),
|
||||
add_si(rt_z, base, O_(V3_S4,z)),
|
||||
})
|
||||
|
||||
FI_ Slice_MipsCode ac_sub_v3s4(AtomBuilder_R ab, U4 rds_x, U4 rds_y, U4 rds_z, U4 rt_x, U4 rt_y, U4 rt_z) atom_dbg_skip MipsAtomComp_Proc_(ab, {
|
||||
sub_s(rds_x, rds_x, rt_x),
|
||||
sub_s(rds_y, rds_y, rt_y),
|
||||
|
||||
@@ -16,6 +16,32 @@ atom_dbg_skip MipsAtomComp_Proc_(ab, {
|
||||
or_i_self( dst, u4_lo(imm)),
|
||||
})
|
||||
|
||||
FI_ Slice_MipsCode ac_shift_aright_v3_self(AtomBuilder_R ab, Reg dt_x, Reg dt_y, Reg dt_z, U2 shift_amount)
|
||||
MipsAtomComp_Proc_( ab, {
|
||||
shift_aright(dt_x, dt_x, shift_amount),
|
||||
shift_aright(dt_y, dt_y, shift_amount),
|
||||
shift_aright(dt_z, dt_z, shift_amount),
|
||||
})
|
||||
|
||||
FI_ Slice_MipsCode ac_shift_aright_var_v3(AtomBuilder_R ab
|
||||
, Reg rd_v0, Reg rd_v1, Reg rd_v2
|
||||
, Reg rs_v0, Reg rs_v1, Reg rs_v2
|
||||
, Reg r_shift)
|
||||
MipsAtomComp_Proc_(ab, {
|
||||
shift_aright_var(rd_v0, rs_v0, r_shift),
|
||||
shift_aright_var(rd_v1, rs_v1, r_shift),
|
||||
shift_aright_var(rd_v2, rs_v2, r_shift),
|
||||
})
|
||||
|
||||
FI_ Slice_MipsCode ac_shift_aright_var_v3_self(AtomBuilder_R ab
|
||||
, Reg rds_v0, Reg rds_v1, Reg rds_v2
|
||||
, Reg r_shift)
|
||||
MipsAtomComp_Proc_(ab, {
|
||||
shift_aright_var(rds_v0, rds_v0, r_shift),
|
||||
shift_aright_var(rds_v1, rds_v1, r_shift),
|
||||
shift_aright_var(rds_v2, rds_v2, r_shift),
|
||||
})
|
||||
|
||||
#pragma endregion MACs (Mips Atom Components)
|
||||
|
||||
#pragma region Baked Atoms
|
||||
|
||||
+2
-2
@@ -64,8 +64,8 @@ NI_ void pad_bios_init_start(PadBiosRaw* raw0, PadBiosRaw* raw1)
|
||||
asm_words(
|
||||
add_ui( R_T1, R_0, bios_start_pad_2), /* $t1 = 0x13 */
|
||||
add_ui( R_T2, R_0, bios_btable_addr), /* $t2 = 0xB0 (re-load) */
|
||||
call_reg(R_T2), /* jalr $t2, $ra */
|
||||
nop /* BD slot */
|
||||
call_reg(R_T2), /* jalr $t2, $ra */
|
||||
nop /* BD slot */
|
||||
)
|
||||
asm_clobber:
|
||||
rlit(R_AT),
|
||||
|
||||
Reference in New Issue
Block a user