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spamming load delay slots for now as a fix...
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@@ -182,17 +182,14 @@ NI_ void pad_bios_init_start(PadBiosRaw* raw0, PadBiosRaw* raw1)
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asm_rpins, r_use(p0), r_use(p1)
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asm_clobber:
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rlit(R_AT),
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rlit(R_V0), rlit(R_V1),
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rlit(R_V0), rlit(R_V1),
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rlit(R_T0), rlit(R_T1), rlit(R_T2), rlit(R_T3), rlit(R_T4),
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rlit(R_T5), rlit(R_T6), rlit(R_T7), rlit(R_T8), rlit(R_T9),
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rlit(R_RA),
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clb_mem_drain
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);
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/* BIOS clobbered $a0..$a3, $ra, and the volatile GPRs above.
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* The compiler keeps raw0 + raw1 in callee-saved registers (or the outer frame's saved slots)
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* because the asm volatile blocks only clobber the volatile GPRs above.
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* The C-level writes re-load the pointers via the parameter names and write 0xFF to each
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/* The C-level writes re-load the pointers via the parameter names and write 0xFF to each
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* buffer's status byte to mark the initial-state hazard documented in kernelbios.md:1621-1624. */
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u1_v(raw0)[0] = 0xFF;
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u1_v(raw1)[0] = 0xFF;
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