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resolve_look_at__cross_uz_ux_to_up_proc reviewed

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ed
2026-08-15 19:53:08 -04:00
parent a16c727db2
commit d9b9241e2c
8 changed files with 64 additions and 70 deletions
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code/duffle/gen/macs.h
+2 -2
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@@ -250,8 +250,8 @@ WORD_COUNT(mac_lzcr_round_even_half_shift, 5)
, gte_mv_to_data_r(to_ir1, C2_IR1) /* IR1 = src.x (preserved in r_tmp — r_mac2_scratch was clobbered to MAC2 in stage 1.5) */ \
, gte_mv_to_data_r(to_ir2, C2_IR2) \
, gte_mv_to_data_r(to_ir3, C2_IR3) /* IR3 = src.z (reloaded) */ \
, DmaSlot_ nop_slot1 \
, DmaSlot_ nop_slot2 \
, GteDelay_ nop_slot1 \
, GteDelay_ nop_slot2 \
, gte_cmdw_gpf \
, gte_mv_from_data_r(fr_mac1, C2_MAC1) \
, gte_mv_from_data_r(fr_mac2, C2_MAC2) \
code/duffle/gen/offsets.h
+2 -2
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@@ -25,7 +25,7 @@
#pragma region duffle
// --- atom: example_atom (10 words) ---
// --- atom: example_atom_proc (10 words) ---
#define _atom_offset_example_atom_proc_skip 2
@@ -33,7 +33,7 @@ enum {
atom_offset_example_atom_proc_skip = _atom_offset_example_atom_proc_skip,
};
// --- atom: normalize_v3s4 (47 words) ---
// --- atom: normalize_v3s4_proc (61 words) ---
#define _atom_offset_aligned_done_srav_path 3
#define _atom_offset_srav_path_aligned_done 4
code/duffle/gp.h
+1
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@@ -68,6 +68,7 @@ enum {
#define gp0_send(word) (HW_GP0[0] = (word))
#define gp1_send(word) (HW_GP1[0] = (word))
#define DmaSlot_ // Annotate an instruction as filling a CPU <-> Command DMA delay slot/s
/* ============================================================================
* GP0 command byte constants + Layer 1 (GPU bitfield shifts)
code/duffle/gte.atom.c
+6 -6
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@@ -150,8 +150,8 @@ MipsAtomComp_Proc_(ab, {
gte_mv_to_data_r(to_ir1, C2_IR1), /* IR1 = src.x (preserved in r_tmp — r_mac2_scratch was clobbered to MAC2 in stage 1.5) */
gte_mv_to_data_r(to_ir2, C2_IR2),
gte_mv_to_data_r(to_ir3, C2_IR3), /* IR3 = src.z (reloaded) */
DmaSlot_ nop_slot1,
DmaSlot_ nop_slot2,
GteDelay_ nop_slot1,
GteDelay_ nop_slot2,
gte_cmdw_gpf,
gte_mv_from_data_r(fr_mac1, C2_MAC1),
gte_mv_from_data_r(fr_mac2, C2_MAC2),
@@ -293,8 +293,8 @@ MipsAtom_Proc_(aa, {
mac_gte_mv_from_data_r_mac123(r.t3.mac1_scratch, r.t4.mac2_scratch, r.norm), LdSlot_ nop,
add_u_self( r.norm, r.t3.mac1_scratch),
add_u_self( r.norm, r.t4.mac2_scratch),
gte_mv_to_data_r( r.norm, C2_LZCS), DmaSlot_ nop2,
gte_mv_from_data_r(r.shift, C2_LZCR), DmaSlot_ nop,
gte_mv_to_data_r( r.norm, C2_LZCS), GteDelay_ nop2,
gte_mv_from_data_r(r.shift, C2_LZCR), GteDelay_ nop,
/* Stage 3: round LZCR to even, compute half-shift, align |v|² to bit 24.
* r_norm holds |v|² sum; r_shift holds the LZCR count from mfc2.
@@ -328,8 +328,8 @@ MipsAtom_Proc_(aa, {
r.recip_est,
r.t5.src_z, /* IR3 = src.z (reloaded) */
r.t4.mac2_scratch, r.recip_est, r.t5.src_z,
DmaSlot_ add_si(r.dst_ptr, r.scratch, dst_offset), // pre-laoding destination to register here.
DmaSlot_ nop
GteDelay_ add_si(r.dst_ptr, r.scratch, dst_offset), // pre-laoding destination to register here.
GteDelay_ nop
),
/* sra by r_shift = (31-LZCR)/2 (saved before sqrtbl lookup) */
mac_shift_aright_var_v3_self(r.t4.mac2_scratch, r.recip_est, r.t5.src_z, r.shift),
code/duffle/gte.h
+1 -1
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@@ -310,7 +310,7 @@ enum { _C2_TX_SUBS_ = 0
#define gte_mv_from_ctrl_r(rt, rd) enc_gte_tx(sub_cfc2, (rt), (rd)) /* Copy From ctrl reg */
#define gte_mv_to_data_r(rt, rd) enc_gte_tx(sub_mtc2, (rt), (rd)) /* Move To data reg */
#define gte_mv_to_ctrl_r(rt, rd) enc_gte_tx(sub_ctc2, (rt), (rd)) /* Copy To ctrl reg */
#define DmaSlot_ // Annotate an instruction as filling a CPU <-> GTE DMA delay slot/s
#define GteDelay_ // Annotate an instruction as filling a CPU <-> GTE DMA delay slot/s
/* COP2 Data Load (lwc2): `lwc2 rt, off(rs)`
* Layout: [op_lwc2:6][rs:5][rt:5][imm:16]