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Rename _shift enums to _pos (may change to offset, but in either case not as accurate to call them _shift, and _shift_smount is longer).

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ed
2026-08-19 13:17:08 -04:00
parent 3440c9b59e
commit cf78cfa120
3 changed files with 80 additions and 80 deletions
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code/duffle/gp.h
+52 -52
View File
@@ -21,7 +21,7 @@
* 4. Semantic encoders gp0_word_poly_f3(r,g,b) * 4. Semantic encoders gp0_word_poly_f3(r,g,b)
* 3. Composite encoders enc_color_word(cmd, r, g, b) * 3. Composite encoders enc_color_word(cmd, r, g, b)
* 2. Per-field encoders enc_gp0_color_r(r), enc_gp0_color_g(g), ... * 2. Per-field encoders enc_gp0_color_r(r), enc_gp0_color_g(g), ...
* 1. Bitfield layout consts gp0_color_red_shift = 0, gp0_color_red_width = 8 * 1. Bitfield layout consts gp0_color_red_pos = 0, gp0_color_red_width = 8
* 0. Opcode IDs gp0_cmd_poly_f3 = 0x20 * 0. Opcode IDs gp0_cmd_poly_f3 = 0x20
* *
* Vendor mnemonics (gte_mtc2, gte_mfc2, etc.) are NOT in this header. * Vendor mnemonics (gte_mtc2, gte_mfc2, etc.) are NOT in this header.
@@ -75,7 +75,7 @@ enum {
* ============================================================================ * ============================================================================
* 8-bit GP0 opcodes (the upper byte of a primitive's first word). These are the BYTE only. * 8-bit GP0 opcodes (the upper byte of a primitive's first word). These are the BYTE only.
* NO macro body past this point uses a raw shift or raw mask. * NO macro body past this point uses a raw shift or raw mask.
* Mirrors the OPCODE_SHIFT / RS_SHIFT convention from mips.h. * Mirrors the OPCODE_POS / RS_POS convention from mips.h.
* ============================================================================ */ * ============================================================================ */
enum { enum {
gp0_cmd_Nop = 0x00, gp0_cmd_Nop = 0x00,
@@ -117,9 +117,9 @@ enum {
gp0_cmd_SetDrawOffset = 0xE5, gp0_cmd_SetDrawOffset = 0xE5,
gp0_cmd_SetMaskBit = 0xE6, gp0_cmd_SetMaskBit = 0xE6,
/* bitfield shifts / widths ---- /* bitfield offset pos / widths ----
* Generic GP0/GP1 command byte (upper 8 bits of every word sent to either port). */ * Generic GP0/GP1 command byte (upper 8 bits of every word sent to either port). */
gp0_cmd_shift = 24, gp0_cmd_pos = 24,
gp0_cmd_width = 8, gp0_cmd_width = 8,
/* Color word layout (lives in Poly_F3.color, Poly_G4.c0..c3, etc.): /* Color word layout (lives in Poly_F3.color, Poly_G4.c0..c3, etc.):
@@ -127,10 +127,10 @@ enum {
* bits 23..16 = BLUE * bits 23..16 = BLUE
* bits 15..08 = GREEN * bits 15..08 = GREEN
* bits 07..00 = RED (PSX GPU is BGR, NOT RGB) */ * bits 07..00 = RED (PSX GPU is BGR, NOT RGB) */
gp0_color_cmd_shift = 24, gp0_color_cmd_width = 8, gp0_color_cmd_pos = 24, gp0_color_cmd_width = 8,
gp0_color_blue_shift = 16, gp0_color_blue_width = 8, gp0_color_blue_pos = 16, gp0_color_blue_width = 8,
gp0_color_green_shift = 8, gp0_color_green_width = 8, gp0_color_green_pos = 8, gp0_color_green_width = 8,
gp0_color_red_shift = 0, gp0_color_red_width = 8, gp0_color_red_pos = 0, gp0_color_red_width = 8,
}; };
/* ============================================================================ /* ============================================================================
@@ -143,12 +143,12 @@ enum {
* ============================================================================ */ * ============================================================================ */
/* ---- Layer 1.5: per-field encoders ---- */ /* ---- Layer 1.5: per-field encoders ---- */
#define enc_gp0_cmd(cmd) ((cmd) << gp0_cmd_shift) #define enc_gp0_cmd(cmd) ((cmd) << gp0_cmd_pos)
#define enc_gp0_color_cmd(cmd) ((cmd) << gp0_color_cmd_shift) #define enc_gp0_color_cmd(cmd) ((cmd) << gp0_color_cmd_pos)
#define enc_gp0_color_r(r) ((r) << gp0_color_red_shift) #define enc_gp0_color_r(r) ((r) << gp0_color_red_pos)
#define enc_gp0_color_g(g) ((g) << gp0_color_green_shift) #define enc_gp0_color_g(g) ((g) << gp0_color_green_pos)
#define enc_gp0_color_b(b) ((b) << gp0_color_blue_shift) #define enc_gp0_color_b(b) ((b) << gp0_color_blue_pos)
/* ---- Layer 2: composite encoders ---- */ /* ---- Layer 2: composite encoders ---- */
#define enc_color_word(cmd, r, g, b) (enc_gp0_color_cmd(cmd) | enc_gp0_color_r(r) | enc_gp0_color_g(g) | enc_gp0_color_b(b)) #define enc_color_word(cmd, r, g, b) (enc_gp0_color_cmd(cmd) | enc_gp0_color_r(r) | enc_gp0_color_g(g) | enc_gp0_color_b(b))
@@ -212,37 +212,37 @@ enum {
gp1_disp_VInterlace = 0x1, gp1_disp_VInterlace = 0x1,
/* ---- Layer 1: GP1 display-mode + range + draw-area shifts/widths ---- */ /* ---- Layer 1: GP1 display-mode + range + draw-area shifts/widths ---- */
gp1_disp_hres_shift = 0, gp1_disp_hres_width = 2, gp1_disp_hres_pos = 0, gp1_disp_hres_width = 2,
gp1_disp_vres_shift = 2, gp1_disp_vres_width = 1, gp1_disp_vres_pos = 2, gp1_disp_vres_width = 1,
gp1_disp_color_shift = 4, gp1_disp_color_width = 1, gp1_disp_color_pos = 4, gp1_disp_color_width = 1,
gp1_disp_interlace_shift = 5, gp1_disp_interlace_width = 1, gp1_disp_interlace_pos = 5, gp1_disp_interlace_width = 1,
/* GP1 horizontal display range: bits 0..11 = X2, bits 12..23 = X1 */ /* GP1 horizontal display range: bits 0..11 = X2, bits 12..23 = X1 */
gp1_hrange_x1_shift = 12, gp1_hrange_x1_width = 12, gp1_hrange_x1_pos = 12, gp1_hrange_x1_width = 12,
gp1_hrange_x2_shift = 0, gp1_hrange_x2_width = 12, gp1_hrange_x2_pos = 0, gp1_hrange_x2_width = 12,
/* GP1 vertical display range: bits 0..9 = Y2, bits 10..19 = Y1 */ /* GP1 vertical display range: bits 0..9 = Y2, bits 10..19 = Y1 */
gp1_vrange_y1_shift = 10, gp1_vrange_y1_width = 10, gp1_vrange_y1_pos = 10, gp1_vrange_y1_width = 10,
gp1_vrange_y2_shift = 0, gp1_vrange_y2_width = 10, gp1_vrange_y2_pos = 0, gp1_vrange_y2_width = 10,
/* GP1 draw area (top-left or bottom-right): bits 0..9 = X, bits 10..19 = Y /* GP1 draw area (top-left or bottom-right): bits 0..9 = X, bits 10..19 = Y
* (10-bit signed — caller pre-signs) */ * (10-bit signed — caller pre-signs) */
gp1_draw_x_shift = 0, gp1_draw_x_width = 10, gp1_draw_x_pos = 0, gp1_draw_x_width = 10,
gp1_draw_y_shift = 10, gp1_draw_y_width = 10, gp1_draw_y_pos = 10, gp1_draw_y_width = 10,
}; };
/* ---- Layer 1.5: GP1 per-field encoders ---- */ /* ---- Layer 1.5: GP1 per-field encoders ---- */
#define enc_gp1_disp_hres(h) ((h) << gp1_disp_hres_shift) #define enc_gp1_disp_hres(h) ((h) << gp1_disp_hres_pos)
#define enc_gp1_disp_vres(v) ((v) << gp1_disp_vres_shift) #define enc_gp1_disp_vres(v) ((v) << gp1_disp_vres_pos)
#define enc_gp1_disp_color(c) ((c) << gp1_disp_color_shift) #define enc_gp1_disp_color(c) ((c) << gp1_disp_color_pos)
#define enc_gp1_disp_interlace(i) ((i) << gp1_disp_interlace_shift) #define enc_gp1_disp_interlace(i) ((i) << gp1_disp_interlace_pos)
#define enc_gp1_hrange_x1(x1) ((x1) << gp1_hrange_x1_shift) #define enc_gp1_hrange_x1(x1) ((x1) << gp1_hrange_x1_pos)
#define enc_gp1_hrange_x2(x2) ((x2) << gp1_hrange_x2_shift) #define enc_gp1_hrange_x2(x2) ((x2) << gp1_hrange_x2_pos)
#define enc_gp1_vrange_y1(y1) ((y1) << gp1_vrange_y1_shift) #define enc_gp1_vrange_y1(y1) ((y1) << gp1_vrange_y1_pos)
#define enc_gp1_vrange_y2(y2) ((y2) << gp1_vrange_y2_shift) #define enc_gp1_vrange_y2(y2) ((y2) << gp1_vrange_y2_pos)
#define enc_gp1_draw_x(x) ((x) << gp1_draw_x_shift) #define enc_gp1_draw_x(x) ((x) << gp1_draw_x_pos)
#define enc_gp1_draw_y(y) ((y) << gp1_draw_y_shift) #define enc_gp1_draw_y(y) ((y) << gp1_draw_y_pos)
/* ---- Layer 2: GP1 composite encoders ---- */ /* ---- Layer 2: GP1 composite encoders ---- */
#define enc_gp1_disp_mode_word(h, v, c, i) (enc_gp0_cmd(gp1_cmd_DisplayMode) | enc_gp1_disp_hres(h) | enc_gp1_disp_vres(v) | enc_gp1_disp_color(c) | enc_gp1_disp_interlace(i)) #define enc_gp1_disp_mode_word(h, v, c, i) (enc_gp0_cmd(gp1_cmd_DisplayMode) | enc_gp1_disp_hres(h) | enc_gp1_disp_vres(v) | enc_gp1_disp_color(c) | enc_gp1_disp_interlace(i))
@@ -553,16 +553,16 @@ typedef Struct_(Poly_GT4) {
* ============================================================================ */ * ============================================================================ */
enum { enum {
/* ---- Layer 1: TPage bitfield shifts / widths ---- */ /* ---- Layer 1: TPage bitfield shifts / widths ---- */
gp0_tpage_x_shift = 0, gp0_tpage_x_width = 4, gp0_tpage_x_pos = 0, gp0_tpage_x_width = 4,
gp0_tpage_y_shift = 4, gp0_tpage_y_width = 1, gp0_tpage_y_pos = 4, gp0_tpage_y_width = 1,
gp0_tpage_semi_trans_shift = 5, gp0_tpage_semi_trans_width = 2, gp0_tpage_semi_trans_pos = 5, gp0_tpage_semi_trans_width = 2,
gp0_tpage_color_depth_shift = 7, gp0_tpage_color_depth_width = 2, gp0_tpage_color_depth_pos = 7, gp0_tpage_color_depth_width = 2,
gp0_tpage_dither_shift = 9, gp0_tpage_dither_width = 1, gp0_tpage_dither_pos = 9, gp0_tpage_dither_width = 1,
gp0_tpage_draw_to_disp_shift = 10, gp0_tpage_draw_to_disp_width = 1, gp0_tpage_draw_to_disp_pos = 10, gp0_tpage_draw_to_disp_width = 1,
gp0_tpage_tex_disable_shift = 11, gp0_tpage_tex_disable_width = 1, gp0_tpage_tex_disable_pos = 11, gp0_tpage_tex_disable_width = 1,
/* TPage color-depth payload values (NOT bit positions — these go in /* TPage color-depth payload values (NOT bit positions — these go in
* the 2-bit field at gp0_tpage_color_depth_shift). */ * the 2-bit field at gp0_tpage_color_depth_pos). */
gp0_tpage_color_4bpp = 0x0, gp0_tpage_color_4bpp = 0x0,
gp0_tpage_color_8bpp = 0x1, gp0_tpage_color_8bpp = 0x1,
gp0_tpage_color_16bpp = 0x2, gp0_tpage_color_16bpp = 0x2,
@@ -578,13 +578,13 @@ enum {
}; };
/* ---- Layer 1.5: TPage per-field encoders. Mirrors enc_gte_sf/mx/v in gte.h. ---- */ /* ---- Layer 1.5: TPage per-field encoders. Mirrors enc_gte_sf/mx/v in gte.h. ---- */
#define enc_gp0_tpage_x(x) ((x) << gp0_tpage_x_shift) #define enc_gp0_tpage_x(x) ((x) << gp0_tpage_x_pos)
#define enc_gp0_tpage_y(y) ((y) << gp0_tpage_y_shift) #define enc_gp0_tpage_y(y) ((y) << gp0_tpage_y_pos)
#define enc_gp0_tpage_semi_trans(s) ((s) << gp0_tpage_semi_trans_shift) #define enc_gp0_tpage_semi_trans(s) ((s) << gp0_tpage_semi_trans_pos)
#define enc_gp0_tpage_color_depth(c) ((c) << gp0_tpage_color_depth_shift) #define enc_gp0_tpage_color_depth(c) ((c) << gp0_tpage_color_depth_pos)
#define enc_gp0_tpage_dither(d) ((d) << gp0_tpage_dither_shift) #define enc_gp0_tpage_dither(d) ((d) << gp0_tpage_dither_pos)
#define enc_gp0_tpage_draw_to_disp(d) ((d) << gp0_tpage_draw_to_disp_shift) #define enc_gp0_tpage_draw_to_disp(d) ((d) << gp0_tpage_draw_to_disp_pos)
#define enc_gp0_tpage_tex_disable(t) ((t) << gp0_tpage_tex_disable_shift) #define enc_gp0_tpage_tex_disable(t) ((t) << gp0_tpage_tex_disable_pos)
/* ---- Layer 2: TPage composite encoder. Mirrors enc_gte_cmdw in gte.h ---- */ /* ---- Layer 2: TPage composite encoder. Mirrors enc_gte_cmdw in gte.h ---- */
#define enc_gp0_tpage_word(x, y, semi_trans, color_depth, dither, draw_to_disp, tex_disable) \ #define enc_gp0_tpage_word(x, y, semi_trans, color_depth, dither, draw_to_disp, tex_disable) \
@@ -615,16 +615,16 @@ typedef Struct_(TexturePage) { U4 raw; };
* ============================================================================ */ * ============================================================================ */
enum { enum {
/* ---- Layer 1: CLUT bitfield shifts / widths ---- */ /* ---- Layer 1: CLUT bitfield shifts / widths ---- */
gp0_clut_y_shift = 0, gp0_clut_y_width = 6, gp0_clut_y_pos = 0, gp0_clut_y_width = 6,
gp0_clut_x_shift = 6, gp0_clut_x_width = 9, gp0_clut_x_pos = 6, gp0_clut_x_width = 9,
/* CLUT-load cmd-byte variants — the upper byte of the GP0 word. */ /* CLUT-load cmd-byte variants — the upper byte of the GP0 word. */
gp0_clut_cmd_Load4bpp = 0x20, gp0_clut_cmd_Load4bpp = 0x20,
gp0_clut_cmd_Load8bpp = 0x25, gp0_clut_cmd_Load8bpp = 0x25,
}; };
/* ---- Layer 1.5: CLUT per-field encoders ---- */ /* ---- Layer 1.5: CLUT per-field encoders ---- */
#define enc_gp0_clut_x(x) ((x) << gp0_clut_x_shift) #define enc_gp0_clut_x(x) ((x) << gp0_clut_x_pos)
#define enc_gp0_clut_y(y) ((y) << gp0_clut_y_shift) #define enc_gp0_clut_y(y) ((y) << gp0_clut_y_pos)
/* ---- Layer 2: CLUT composite encoder ---- */ /* ---- Layer 2: CLUT composite encoder ---- */
#define enc_gp0_clut_word(cmd, x, y) (enc_gp0_cmd(cmd) | enc_gp0_clut_x(x) | enc_gp0_clut_y(y)) #define enc_gp0_clut_word(cmd, x, y) (enc_gp0_cmd(cmd) | enc_gp0_clut_x(x) | enc_gp0_clut_y(y))
code/duffle/gte.h
+16 -16
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@@ -170,20 +170,20 @@ enum {
* +------------+--+-----+------+------+------+------+---+--------+----------+ * +------------+--+-----+------+------+------+------+---+--------+----------+
* \_____ GTE_PAYLOAD _____/ \__ GTE_CMD __/ * \_____ GTE_PAYLOAD _____/ \__ GTE_CMD __/
* *
* Shifts/masks below are the *bit positions* and *bit widths* of each configurable field, used by the ENC_GTE_CMD encoder. * Offset position & masks below are the *bit positions* and *bit widths* of each configurable field, used by the ENC_GTE_CMD encoder.
* Mirrors the OPCODE_SHIFT / RS_SHIFT convention used in mips.h. * Mirrors the OPCODE_POS / RS_POS convention used in mips.h.
*/ */
gte_shift_sf = 19, gte_width_sf = 1, gte_pos_sf = 19, gte_width_sf = 1,
gte_shift_mx = 17, gte_width_mx = 2, gte_pos_mx = 17, gte_width_mx = 2,
gte_shift_v = 15, gte_width_v = 2, gte_pos_v = 15, gte_width_v = 2,
gte_shift_cv = 13, gte_width_cv = 2, gte_pos_cv = 13, gte_width_cv = 2,
gte_shift_lm = 10, gte_width_lm = 1, gte_pos_lm = 10, gte_width_lm = 1,
gte_shift_cmd = 0, gte_width_cmd = 6, gte_pos_cmd = 0, gte_width_cmd = 6,
/* Fake command number (bits 24-20) — IGNORED by the GTE hardware per PSX-SPX `geometrytransformationenginegte.md` line 48. /* Fake command number (bits 24-20) — IGNORED by the GTE hardware per PSX-SPX `geometrytransformationenginegte.md` line 48.
* libgte's compiler emits non-zero values in this field as a disassembly signature. */ * libgte's compiler emits non-zero values in this field as a disassembly signature. */
gte_shift_fake_cmd = 20, gte_pos_fake_cmd = 20,
gte_width_fake_cmd = 5, gte_width_fake_cmd = 5,
}; };
@@ -340,13 +340,13 @@ enum { _C2_TX_SUBS_ = 0
#define gte_cmd_base (enc_op(op_cop2) | (1 << 25)) #define gte_cmd_base (enc_op(op_cop2) | (1 << 25))
/* Per-field encoders. Each one does (value & mask) << shift on its own. */ /* Per-field encoders. Each one does (value & mask) << shift on its own. */
#define enc_gte_sf(sf) ((sf) << gte_shift_sf ) #define enc_gte_sf(sf) ((sf) << gte_pos_sf )
#define enc_gte_mx(mx) ((mx) << gte_shift_mx ) #define enc_gte_mx(mx) ((mx) << gte_pos_mx )
#define enc_gte_v(v) ((v) << gte_shift_v ) #define enc_gte_v(v) ((v) << gte_pos_v )
#define enc_gte_cv(cv) ((cv) << gte_shift_cv ) #define enc_gte_cv(cv) ((cv) << gte_pos_cv )
#define enc_gte_lm(lm) ((lm) << gte_shift_lm ) #define enc_gte_lm(lm) ((lm) << gte_pos_lm )
#define enc_gte_cmd(cmd) ((cmd) << gte_shift_cmd ) #define enc_gte_cmd(cmd) ((cmd) << gte_pos_cmd )
#define enc_gte_fake_cmd(x) ((x) << gte_shift_fake_cmd) #define enc_gte_fake_cmd(x) ((x) << gte_pos_fake_cmd)
/* Composite: all six GTE fields + the COP2/CO base. */ /* Composite: all six GTE fields + the COP2/CO base. */
#define enc_gte_cmdw(sf, mx, v, cv, lm, cmd) ( \ #define enc_gte_cmdw(sf, mx, v, cv, lm, cmd) ( \
code/duffle/mips.h
+12 -12
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@@ -252,12 +252,12 @@ enum {
enum { _BitOffsets = 0 enum { _BitOffsets = 0
/* Bit Offsets for MIPS Instruction Fields */ /* Bit Offsets for MIPS Instruction Fields */
, OPCODE_SHIFT = 26 , OPCODE_POS = 26
, RS_SHIFT = 21 , RS_POS = 21
, RT_SHIFT = 16 , RT_POS = 16
, RD_SHIFT = 11 , RD_POS = 11
, SHAMT_SHIFT = 6 /* Shift Amount */ , SHAMT_POS = 6 /* Shift Amount: Offset Position */
, FC_SHIFT = 0 , FC_POS = 0
/* IMM_MASK is the 16-bit two's-complement truncation for the immediate field. /* IMM_MASK is the 16-bit two's-complement truncation for the immediate field.
* It is NOT a range guard — it is load-bearing for negative branch offsets * It is NOT a range guard — it is load-bearing for negative branch offsets
@@ -268,12 +268,12 @@ enum { _BitOffsets = 0
, IMM_MASK = 0xFFFF , IMM_MASK = 0xFFFF
}; };
#define enc_op(op) ((op) << OPCODE_SHIFT) #define enc_op(op) ((op) << OPCODE_POS)
#define enc_rs(rs) ((rs) << RS_SHIFT) #define enc_rs(rs) ((rs) << RS_POS)
#define enc_rt(rt) ((rt) << RT_SHIFT) #define enc_rt(rt) ((rt) << RT_POS)
#define enc_rd(rd) ((rd) << RD_SHIFT) #define enc_rd(rd) ((rd) << RD_POS)
#define enc_shamt(shamt) ((shamt) << SHAMT_SHIFT) #define enc_shamt(shamt) ((shamt) << SHAMT_POS)
#define enc_fc(fc) ((fc) << FC_SHIFT) #define enc_fc(fc) ((fc) << FC_POS)
#define enc_imm(imm) ((imm) & IMM_MASK) #define enc_imm(imm) ((imm) & IMM_MASK)
/* MIPS R-Type Instruction Format (Register-to-Register) */ /* MIPS R-Type Instruction Format (Register-to-Register) */